Uninterruptible Power Supply Topology Based on Single-Phase Matrix Converter with Active Power Filter Functionality

Abstract

This study introduces a novel uninterruptible power supply (UPS) configuration that integrates active power filter (APF) capabilities within a single-phase matrix converter (SPMC) framework. Power disruptions, particularly affecting critical loads, can lead to substantial economic damages. Historically, conventional UPS systems utilized dual separate converters to function as a rectifier and an inverter, without incorporating any power factor correction (PFC) mechanisms. Such configurations suffered from diminished power density, compromised reliability, and spatial limitations. To address these issues, this research proposes an enhanced UPS design that incorporates APF features into the SPMC. The focus of this investigation is on the efficiency of alternating current (AC) to direct current (DC) conversion and the reverse process utilizing this advanced UPS model. The SPMC is selected to supplant the rectifier and inverter units traditionally employed in UPS architectures. A novel integrated switching strategy is formulated to facilitate the operation of the UPS in either rectifier (charging) or inverter (discharging) modes, contingent upon the operational state. The performance and efficacy of the devised circuit design and switching technique are substantiated through simulations conducted in MATLAB/Simulink 2019 and empirical evaluations using a test rig. The findings demonstrate that the voltage generated is sinusoidal and synchronized with the supply current, thereby minimizing the total harmonic distortion (THD) and enhancing both the power factor and the transition efficiency of the UPS system between its charging and discharging states.

1. Introduction

The reliability and quality of electricity supply are crucial determinants of sustainable energy delivery. In recent times, the adoption of uninterruptible power supply (UPS) systems has surged, largely propelled by advancements in the global manufacturing landscape [1,2]. Within this domain, the demand for a dependable and high-quality power source is paramount, particularly for operations deemed critical and susceptible to disruptions [3,4,5,6].

A traditional UPS framework is characterized by three principal elements: a rectifier, an inverter, and a static bypass switch, depicted in Figure 1. The static bypass switch is designed to seamlessly transition the power source for critical loads to an auxiliary supply, effectively segregating it from the primary source until reintegration with the grid is achieved. The rectification process is facilitated by a bridge diode configuration, devoid of any sophisticated control mechanisms [7,8]. However, such conventional UPS configurations are beleaguered by challenges, including substantial physical bulkiness due to the amalgamation of three distinct components, elevated levels of total harmonic distortion (THD), and diminished power factor efficiency [9].

The matrix converter (MC) has garnered significant interest for its efficacy in AC–AC conversion processes [10,11,12], with its conceptual foundations laid by Gyugyi in 1976 [13]. It operates across all four quadrants of switching technology, presenting a viable alternative to the conventional voltage source inverter approach [14,15]. Following its inception, the single-phase matrix converter (SPMC) was conceptualized by Zuckerberger [16], necessitating four bidirectional switches for its assembly as illustrated in Figure 2. These switches are adept at facilitating bidirectional current flow while also being capable of voltage blockade in both directions [11,17], utilizing insulated gate bipolar transistors (IGBT) switches renowned for their appropriateness in medium-frequency switching and high-current applications suitable for medium power scenarios.

Recent scholarly endeavours have explored various topologies to enhance rectifier and inverter functionalities. Among these, the SPMC stands out as a singular solution for both controlled rectification and inversion processes, as explored in this study. The discourse extends to control algorithms for both processes within the SPMC framework, incorporating secure commutation techniques to mitigate voltage and current surges potentially harmful to switching apparatus [18,19,20].

The foundational premise of utilizing SPMCs for UPS applications was posited in 2006 [21], introducing novel switching integration algorithms for rectification and inversion functions. Subsequent enhancements to these algorithms aimed at optimizing UPS operations were documented [22]. Nonetheless, these investigations did not adequately address power quality, contributing to considerable harmonic disturbances.

Advancements in employing SPMCs as a UPS system have evolved to include active power filter (APF) capabilities, initially introduced in [2]. This initiative was modelled and simulated via MATLAB/Simulink, employing secure commutation strategies within the switching algorithms while integrating APF features. Additionally, pioneering research on wireless power transfer (WPT) from UPS to load demonstrated more than 90% efficiency in power transfer, though it remained confined to simulation stages [23].

Notwithstanding these developments, the absence of empirical verification in laboratory settings has left the efficacy of the switching strategies unconfirmed. An initial evaluation of these strategies, as outlined in [24], reveals significant opportunities for refinement in the UPS system’s switching mechanisms.

Consequently, this paper articulates the development of an innovative switching integration algorithm, enhancing an UPS circuit topology that amalgamates rectifier and inverter functions within a singular framework predicated on SPMCs. This novel approach, incorporating APF capabilities, aims at rectifying distorted supply currents. This study marks the inaugural laboratory validation of the proposed system, offering an exhaustive assessment of its harmonics mitigation efficacy.

2. Bidirectional Switch Power Losses

The SPMCs are controlled utilizing a combination of power semiconductor devices, namely insulated gate bipolar transistors (IGBTs) and diodes, which operate as switching elements alternating between the conduction, blocking, and switching states in cyclical fashion. In each of these states, a power dissipation component is generated, resulting in heating of the semiconductor devices and contributing to the total power losses. The power dissipation of the devices is contingent upon the operating conditions of the converter (output frequency, switching frequency, modulation strategy, voltage and current operating levels, load characteristics, etc.). An analytical modeling approach for semiconductor losses in matrix converters is described and presented in [25]. The conduction and switching losses are modeled through simple mathematical expressions based on the ideal behavior of the device. The total average power losses over a fundamental period for any device has been formulated in [26] as:

$$P_{avg}=\frac{1}{T}{\int }_0^{T}p\left(t\right)dt$$

(1)

where

• $p\left(t\right)$ is devices instantaneous dissipated power.
• $T$ is fundamental output current period.

The power dissipation of a semiconductor device at an arbitrary time instant t is equivalent to the mean conduction and switching losses incurred within the device over the switching period $t+T_{sw}$ subsequent to t [27], as illustrated in Figure 3. This methodology facilitates the derivation of simplified continuous time power loss expressions by approximating the instantaneous power losses as:

$$P\left(t\right)\cong P_{cond }\left(t\right)+P_{sw }\left(t\right)=P_{cond }\left(t\right)+P_{on }\left(t\right)+P_{off }\left(t\right)$$

(2)

where $P_{cond }\left(t\right)$ and $P_{sw}\left(t\right)$ are the average conduction losses and average switching losses at each switching period, respectively. In this research, the UPS circuit schematic using SPMC topology is depicted in Figure 4. The power losses for IGBTs and diodes are enough to consider just one IGBT (for example S1a) and one diode (for example D1b) to calculate SPMCs’ power losses. In general operation of SPMCs for the positive cycle, the current flows through S1a and D1b and S4a and D4b, and for negative cycle, S2a and D2b and S3a and D3b. The total average power losses of IGBTs (S1a) can be expressed as follows:

$$P_{S1a}\left(t\right)\cong P_{cond/S1a }\left(t\right)+P_{sw/S1a }\left(t\right)=P_{cond/S1a }\left(t\right)+P_{on/S1a }\left(t\right)+P_{off/S1a }\left(t\right)$$

(3)

The detail expression explanation has been described in [28] and Appendix D. Thus, the average power losses of the IGBT $P_{S1a}\left(t\right)$ can be calculated as below:

$$P_{S1a}\left(t\right)=V_{S1a}\left(t\right)I_{S1a}\left(t\right)D_{S1a}\left(t\right)+\frac{E_{on/S1a}\left(t\right)}{T_{sw}}+\frac{E_{off/S1a}\left(t\right)}{T_{sw}}$$

(4)

$$\begin{array}{l}{P}_{S1a}\left(t\right)=\left(V_{\frac{t}{S}}+a_S{I}_{S1a}^{b_S}\right)\left(I_{M }\sin \left({\omega }_{o}t\right)\right)\left(\frac{1}{2}\left[1+M\sin \left({\omega }_{o}t+{\phi }_o\right)\right]\right)\\ +\left(\frac{h{I}_{S1a}^{k }\left(t\right)}{T_{sw}}\right)+\left(\frac{m{I}_{S1a}^{n }\left(t\right)}{T_{sw}}\right)\end{array}$$

(5)

In the analysis of diode circuits, only two primary forms of power loss merit consideration: conduction losses and turn-off losses. The turn-on and blocking losses have been omitted from this analysis due to their negligible contribution to the total power dissipation described in [28,29] and Appendix D. A detail of the $D_{1b}$ schematic instantaneous dissipated power can be appreciated in Figure 5. Thus, the $P_{D1b}\left(t\right)$ can be described as below:

$$P_{D1b}\left(t\right)\cong P_{cond/D1b }\left(t\right)+P_{sw/D1b }\left(t\right)=P_{cond/D1b }\left(t\right)+P_{off/D1b }\left(t\right)$$

(6)

$$\begin{array}{l}{P}_{\frac{cond}{D1b}}\left(t\right)=\frac{1}{T_{sw}} \underset{t}{\overset{t+T_{sw}}{\int }}{V}_{D1b}\left(t\right)I_{D1b}\left(t\right)dt=\frac{1}{T_{sw}} \underset{t}{\overset{t+t_{cond/D1b}+{∆t}_{off}}{\int }}{V}_{D1b}\left(t\right)I_{D1b}\left(t\right)dt\\ ={V_{D1b}\left(t\right)I}_{D1b}\left(t\right)D_D\left(t\right)dt\end{array}$$

(7)

Total power losses diode (D1b) can be expressed as below:

$$P_{D1b}\left(t\right)\approx V_{D1b}\left(t\right)I_{D1b}\left(t\right)D_D\left(t\right)+\frac{E_{off/D1b}\left(t\right)}{T_{sw}}$$

(8)

As derived in details in Appendix D, then

$$P_{D1b}\left(t\right)=\left(V_{t/D}+a_D{I}_{D1b}^{b_D}\right)\left(I_{M }\sin \left({\omega }_{o}t\right)\right)\left(\frac{1}{2}\left[1-M\sin \left({\omega }_{o}t+{\phi }_o\right)\right]\right)+\left(\frac{0.5I_{rr }0.5V_{dc}{t}_b}{T_{sw}}\right)$$

(9)

In this work, turn-on and turn-off energy losses has been calculated under certain test conditions as well as the modelling parameters of the IGBT and diode switching losses can be found in [27] and parameter on the data sheet for IGBT BUP314D and Diode IN4118. The parameters are depicted in

Table 1. Parameter for IGBT and diode power losses.

State	IGBT Parameters	Diode Parameter
On-state	$V_{t/S}=0.875, a_S=0.028, b_s=0.745$	$V_{t/D}=0.8, a_D=0.005, b_D=1$
Turn-on	$h=1.21\times {10}^{-3} \mathrm{m}\mathrm{J}$, $k=1.65$,	-
Turn-off	${m=0.027\times 10}^{-3} \mathrm{m}\mathrm{J}$, $n=1.183$	${peak I}_{rr}$= 25, $t_b=0.030 \mu \mathrm{s}$
Applied voltage	$V_{dc}=12 \mathrm{V}$
Fundamental frequency	$f_{out}=50 \mathrm{H}\mathrm{z}$
Switching frequency	$f_{sw}=5 \mathrm{K}\mathrm{H}\mathrm{z}$
Modulation	$M=0.75$
Peak current	$I_M=1 \mathrm{A}$
Power factor	$\phi =0.74\mathrm{r}\mathrm{a}\mathrm{d}$

, and the total losses for typical dan proposed UPS are depicted in

Table 2. Number of switches used in UPS.

Device	Total Losses/Device	Proposed UPS	Typical UPS
		Number of Devices (Losses)	Number of Devices (Losses)
IGBT	41.45 W	8 (331.6 W)	4 (165.8 W)
DIODE	15.50 W	8 (124 W)	8 (124 W)
Total Losses	56.95 W	455.6 W	289.8 W

based on expressions (5) and (9).

In the context of the impact on the number of diodes and switches employed in the UPS system, Table 2 presents a comparative analysis of the devices and switches utilized in a typical UPS system and the proposed UPS system. The conventional UPS system necessitates 13 diodes and switch, comprising 8 diodes, 4 IGBTs, and a bypass switch to facilitate rectifier and inverter operations. Conversely, the proposed UPS system incorporates 4 bi-directional switches, encompassing 8 diodes and 8 IGBTs, which enable the system to execute both rectifier and inverter operations, while the proposed system has 18.75% more devices and switches than the conventional system. The total power losses for the proposed UPS are 455.6W, while those for the typical UPS are 289.8W. However, it retains the salient benefits of a compact system size, high power quality, low harmonic, and unity power factor. The proposed UPS notably, the paramount feature of the proposed novel advancement in single-phase UPS system design is the utilization of a singular circuit topology to perform both rectifier and inverter operations. Both operations can be controlled accordingly which cannot be done by the typical UPS system, in which the rectifier is based on uncontrolled operation. This attribute contributes to the realization of a high-power density power converter system, aligning with the power electronics technological roadmap, which aims to increase power density, efficiency dan reliability, and robustness.

3. Topology of UPS System

The envisioned UPS architecture, utilizing the SPMC topology, is illustrated in Figure 6. This diagram, as previously noted, showcases a system solely comprising a single converter based on the SPMC topology, capable of functioning both as a controlled rectifier and a controlled inverter. The SPMC is strategically designed to switch roles between a rectifier (under standard conditions) and an inverter (during power disruptions), thereby obviating the necessity for distinct rectifier and inverter circuits found in conventional UPS designs. Figure 7 provides an intricate view of the circuit layout for the proposed rectifier and inverter configuration, notably absent of any filtering mechanisms. To facilitate its role in the UPS, a voltage sensor apparatus is employed to monitor the supply waveform within the circuit. This sensor plays a pivotal role in managing the transition between charging (rectifier mode) and discharging (inverter mode) operations within the UPS system.

4. Topology of UPS System with APF Functionality

The enhancement of the UPS framework is achieved through the integration of SPMC topology alongside APF capabilities. The APF feature is specifically designed to mitigate harmonic distortions arising from non-linear load activities. In this research, the elimination of harmonic constituents from the non-sinusoidal supply current is facilitated through an innovatively designed APF, which leverages a current control loop (CCL) strategy employing a boost technique. This APF function effectively compensates the supply current, rendering it sinusoidal and synchronized with the supply voltage waveform, as depicted in Figure 8a and Figure 8b, respectively. To ensure system stability and enhance performance, the switching frequency for the controlled rectifier equipped with APF functionality was predetermined at 10 kHz, complemented by proportional and integral (PI) gains.

Figure 9 presents an intricate schematic of the circuit design for the rectifier function, enhanced with APF capabilities. To fulfill the requirements of the APF, an additional component, an inductor labeled L1, is incorporated to serve as the boost inductor. Furthermore, a current sensing device is deployed to monitor the supply current within the CCL framework. The CCL itself is composed of several key components: an absolute circuit, a subtraction circuit, a PI controller, and a comparator. This arrangement facilitates the generation of a sinusoidal reference signal, closely aligned with the supply waveform.

4.1. APF Mathematical Treatment Modeling

The mathematical treatment of the boost inductor is formulated based on Figure 10. The circuit operation can be divided into two stages. Stage 1 represents the circuit operation during the pair of switches S1a and S3a are turned ‘ON’. During this time, the current from the supply voltage flows through S1a and S3a and is defined as I₁₃. Stage 2 represents the circuit operation during the pair of switches S1a and S4a are turned ‘ON’. At this time, the current from the AC supply flows through the pair of switches S1a and S4a and is defined as I₁₄.

The inductor current is linearly ramped from I₁₃ to I₁₄ at stage 1, as shown in Figure 11. During this period, the boost inductor charges energy. The equation for this interval (defined directly as ${\mathrm{S}}_{13}$) with relationship between voltage supply ${\mathrm{V}}_{\mathrm{a}\mathrm{c}}$ and inductor voltage ${\mathrm{V}}_{\mathrm{L}}$ can be stated as:

$${\mathrm{V}}_{\mathrm{a}\mathrm{c}}={\mathrm{V}}_{\mathrm{L}}$$

(10)

$${\mathrm{V}}_{\mathrm{a}\mathrm{c}}=\mathrm{L}\left[\frac{{\mathrm{I}}_{14-{\mathrm{I}}_{13}}}{{\mathrm{S}}_{13}}\right] \mathrm{or} \mathrm{L}\frac{∆\mathrm{I}}{{\mathrm{S}}_{13}}$$

(11)

Thus,

$${\mathrm{S}}_{13}=\frac{∆\mathrm{I}\mathrm{L}}{{\mathrm{V}}_{\mathrm{a}\mathrm{c}}}$$

(12)

Figure 12 shows the simplified circuit for the stage 2. During the pair of S1a and S4a are turned ‘ON’ (${\mathrm{S}}_{14}$), and the energy from L1 is transferred to the load voltage ${\mathrm{V}}_{\mathrm{o}}$. Therefore, the current of L1 decreases linearly during I₁₄, and thus the supply current I_S in this interval can be written as:

$${\mathrm{I}}_s ={\mathrm{I}}_{\mathrm{L}1}={\mathrm{I}}_{14}$$

(13)

Meanwhile, voltage supply ${\mathrm{V}}_{\mathrm{a}\mathrm{c}}$ is

$$\begin{array}{l}{\mathrm{V}}_{\mathrm{a}\mathrm{c}}={\mathrm{V}}_{\mathrm{L}}+{\mathrm{V}}_{\mathrm{o}}\\ {\mathrm{V}}_{\mathrm{a}\mathrm{c}}=\mathrm{L}\left[\frac{{\mathrm{I}}_{13-{\mathrm{I}}_{14}}}{{\mathrm{S}}_{14}}\right]+{\mathrm{V}}_{\mathrm{o}}\end{array}$$

(14)

or can be written as for stage 2:

$$\begin{array}{l}{\mathrm{V}}_{\mathrm{a}\mathrm{c}}=-\left(\mathrm{L}\frac{∆\mathrm{I}}{{\mathrm{S}}_{14}}\right)+{\mathrm{V}}_{\mathrm{o}}\\ {\mathrm{S}}_{14}=\frac{∆I.L}{{\mathrm{V}}_{\mathrm{o}}-V_{ac}}\end{array}$$

(15)

From Equations (13) and (14), both can be written as

$$∆\mathrm{I}=\frac{V_{ac}{S}_{13}}{L}=\frac{\left(V_o-V_{ac}\right)S_{14}}{\mathrm{L}}$$

(16)

From Equation (16), the boost inductor can be determined by

$$\mathrm{L}=\frac{V_{ac}{S}_{13}}{∆I}$$

(17)

Meanwhile, the slope of the ripple current waveform m, as shown Figure 13, is given by

$$m=\frac{2\mathrm{A}}{\mathrm{T}/2}=\frac{4\mathrm{A}}{\mathrm{T}}=4\mathrm{A}{f}_s$$

(18)

where A is the maximum permitted peak of ripple current and f_s is the switching frequency. Otherwise, m also can be written as

$$m=\frac{∆\mathrm{I}}{{\mathrm{S}}_{13}}$$

(19)

In this work, the maximum peak to peak ripple is 1% from the line current, which is 1.7 A. By rearranging Equations (18) and (19),

$$\mathrm{L}=\frac{{\mathrm{V}}_{\mathrm{a}\mathrm{c}}{\mathrm{S}}_{13}}{∆\mathrm{I}}=\frac{{\mathrm{V}}_{\mathrm{a}\mathrm{c}}}{4\mathrm{A}{\mathrm{f}}_{\mathrm{s}}}$$

(20)

Using the circuit parameters A is 0.085 A, f_s is 10 kHz and V_ac is 12 V_rms, the value of L can be determined as

$$\mathrm{L}=\frac{12}{4\times 0.085\times 10\mathrm{k}}=4\mathrm{mH}$$

If the average capacitor current i_c is same as the load current i_o and the capacitor supplies the energy to the load during S1a and S3a (S₁₃) are turned ON, the peak-to-peak ripple voltage capacitor ∆V_c can be calculated as

$$\begin{array}{l}{∆\mathrm{V}}_{\mathrm{c}}={\mathrm{V}}_{\mathrm{c}}-{\mathrm{V}}_{\mathrm{c}}\left({\mathrm{S}}_{13}\right)\\ =\frac{1}{\mathrm{c}}{\int }_0^{\mathrm{S}13}{\mathrm{i}}_{\mathrm{c}}\mathrm{d}\mathrm{t}=\frac{1}{\mathrm{c}}{\int }_0^{\mathrm{S}13}{\mathrm{i}}_{\mathrm{o}}\mathrm{d}\mathrm{t}\end{array}$$

(21)

The value of output voltage ripple for the load will be considerable during the line inductor energizing period and load capacitor discharging period. The output voltage ripple is given

$$\frac{{\mathrm{d}\mathrm{V}}_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}}{{\mathrm{V}}_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}}=\frac{\mathsf{\delta }\mathrm{T}}{\mathrm{R}\mathrm{C}}$$

(22)

where R is the load resistance, C is the capacitance, and $\delta$ is duty cycle ratio.

The mathematical treatment of APF is driven by the CCL to control the charging and discharging modes of operation of the boost inductor, as shown in Figure 14.

The V_ac can be represented as:

$$V_{ac}\left(t\right)=V_{ac}\sin \left(\omega t\right)$$

(23)

where $\omega$ is the angular frequency of the fundamental component. The summation of supply current I_s with distortion components by using RC load can be written as

$$I_s\left(t\right)={\sum }_{n=1}^{\infty }{I}_n\mathrm{s}\mathrm{i}\mathrm{n}(n\omega t+{\theta }_n)$$

(24)

where $I_n$ is amplitude of harmonic order n, and ${\theta }_n$ is its phase. For implementation of APF in the system, I_s can be written as

$$I_s\left(t\right)=I_1\sin \left(\omega t+{\theta }_1\right)+ {\sum }_{n=2}^{\infty }{I}_n\mathrm{s}\mathrm{i}\mathrm{n}(n\omega t+{\theta }_n)$$

(25)

The second part is the non-sinusoidal component and should be removed accordingly. The CCL is the crucial part of the rectifier operation to eliminate the non-sinusoidal component and to ensure that the supply current later becomes sinusoidal and in phase with $V_{ac}$. To simplify the discussion of CCL, the circuit operation can be divided into nine stages, as shown in Figure 15.

At the initial phase, the current sensor detects the supply current I_S, providing a crucial input to the CCL. This sensor is adept at identifying the waveform distortions in the supply current as previously discussed.

During the second phase, the bipolar distorted supply current waveform undergoes transformation into a unipolar waveform, courtesy of the absolute circuit. This conversion facilitates a forthcoming comparison with a unipolar carrier signal. The construction of the absolute circuit involves the utilization of two precision operational amplifiers (op-amps) and five precision resistors, as illustrated in Figure 16. In scenarios where the input signal exhibits a positive cycle, the output from op-amp A1_a1 turns negative, causing diode D1_a1 to exhibit reverse bias. Conversely, diode D2_a1 enters a state of forward bias, effectively completing the feedback circuit around op-amp A1_a1 via resistor R2_a1 and establishing an inverting amplifier configuration. The op-amp A2_a1 then aggregates the output from op-amp A1_a1, applying a gain factor of −2, alongside the input signal which is subject to a gain factor of −1, resulting in an overall gain of +1. When the input signal is in its negative cycle, diode D1_a1 assumes a forward bias, enabling the feedback loop around op-amp A1_a1, while diode D2_a1, being reverse-biased, remains non-conductive. Consequently, op-amp A2_a1 inverts the input signal, yielding a positive output voltage that encapsulates the absolute magnitude of the supply current, irrespective of whether it is in its positive or negative state.

Let us consider the case with R2_a1 = R3_a1 = R and R1_a1 = R4_a1 = R5_a1 = 2R. The circuit operation is divided into two intervals. During interval 1 (positive half-cycle), V_ac is positive, and V1_amp1 = −V_ac. The voltage at the output V0_a1 of op-amp A2_a1 can be found from:

$${\mathrm{V}0}_{\mathrm{a}1}=-\left(\frac{{\mathrm{R}3}_{\mathrm{a}1}}{{\mathrm{R}2}_{\mathrm{a}1}}{\mathrm{V}1}_{\mathrm{a}\mathrm{m}\mathrm{p}1}+\frac{{\mathrm{R}3}_{\mathrm{a}1}}{{\mathrm{R}4}_{\mathrm{a}1}}{\mathrm{V}}_{\mathrm{a}\mathrm{c}}\right)$$

(26)

${\mathrm{V}0}_{\mathrm{a}1}$ becomes

$${\mathrm{V}0}_{\mathrm{a}1}={-1\mathrm{V}1}_{\mathrm{a}\mathrm{m}\mathrm{p}1}-0.5{\mathrm{V}}_{\mathrm{a}\mathrm{c}}=-\left(-{\mathrm{V}}_{\mathrm{a}\mathrm{c}}\right)-0.5{\mathrm{V}}_{\mathrm{a}\mathrm{c}}={\mathrm{V}}_{\mathrm{a}\mathrm{c}}\mathrm{for} {\mathrm{V}}_{\mathrm{a}\mathrm{c}}\ge 0$$

(27)

During interval 2 (negative half-cycle), V_ac is negative, and V2_amp2 = 0. Thus, by using Equation (26) again and if R3_a1 = R4_a1 = 2R and R2_a1 = R, V0_a1 of op-amp A2_a1 is:

$${\mathrm{V}0}_{\mathrm{a}1}={-1\mathrm{V}1}_{\mathrm{a}\mathrm{m}\mathrm{p}1}-0.5{\mathrm{V}}_{\mathrm{a}\mathrm{c}}=-2\left(0\right)-{\mathrm{V}}_{\mathrm{a}\mathrm{c}}={-\mathrm{V}}_{\mathrm{a}\mathrm{c}}\mathrm{for} {\mathrm{V}}_{\mathrm{a}\mathrm{c}}<0$$

(28)

Next, stage 3 presents the input reference signal for the CCL. The AC supply is used as a reference signal represented as reference current I_ref. The magnitude of I_ref is determined based on the peak amplitude of the distorted supply current waveform, which is derived from the rectifier’s operation devoid of any filtering mechanism.

Stage 4 performs similarly to stage 2, in which the bipolar form of the reference signal is converted to the unipolar form. The output from the operational amplifier is a positive voltage indicative of the absolute magnitude of the input reference signal, regardless of its initial positive or negative value.

In stage 5, the output of the subtractor circuit is presented as shown in Figure 17. The subtractor circuit is used to subtract the sensed supply current (distorted current) I_dist with I_ref, in order to produce an error signal. This error signal needs to be eliminated for improving the supply current to be without distortion.

The effect of subtraction can be seen from the following qualitative observations. If V_Idist = 0, then R1sub becomes grounded and V_p is proportional V_Iref, and so we have a non-inverting amplifier with Vo_sub proportional to ${V2}_{sub}$. However, if V_Iref = 0, then V_p = 0, and so we have an inverting amplifier with ${Vo}_{sub}$ proportional to –V1sub. Thus, in general we expect the output to be different voltage.

For a quantitative analysis, the op-amp is assumed to be ideal and note that R2_sub and R3_sub form a voltage divider such that

$${\mathrm{V}}_{\mathrm{P}}=\frac{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}{\mathrm{V}2}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}2}_{\mathrm{s}\mathrm{u}\mathrm{b}}+{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}$$

(29)

Then, since an ideal op-amp has

$$\begin{array}{c}\mathrm{Vin}\left(2\right)=\mathrm{Vin}\left(3\right)=\mathrm{Vp}\mathrm{and}\mathrm{in}=0,\\ {\mathrm{i}}_3=-{\mathrm{i}}_1=-\frac{{\mathrm{V}}_{\mathrm{I}\mathrm{d}\mathrm{i}\mathrm{s}\mathrm{t}}-{\mathrm{V}}_{\mathrm{i}\mathrm{n}\left(2\right)}}{{\mathrm{R}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}}=\frac{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}2}_{\mathrm{s}\mathrm{u}\mathrm{b}}+{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}\left(\frac{{\mathrm{V}}_{\mathrm{I}\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{R}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}}\right)-\frac{{\mathrm{V}}_{\mathrm{I}\mathrm{d}\mathrm{i}\mathrm{s}\mathrm{t}}}{{\mathrm{R}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}}\end{array}$$

(30)

Therefore,

$$\begin{array}{c}{\mathrm{V}\mathrm{o}}_{\mathrm{s}\mathrm{u}\mathrm{b}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}\left(2\right)}+{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}{\mathrm{i}}_3=\frac{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}2}_{\mathrm{s}\mathrm{u}\mathrm{b}}+{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{\mathrm{V}2}_{\mathrm{s}\mathrm{u}\mathrm{b}}+\frac{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}2}_{\mathrm{s}\mathrm{u}\mathrm{b}}+{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}\left(\frac{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}}\right){\mathrm{V}2}_{\mathrm{s}\mathrm{u}\mathrm{b}}-\frac{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{\mathrm{V}}_{\mathrm{I}\mathrm{d}\mathrm{i}\mathrm{s}\mathrm{t}}\\ =\frac{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}}\left(\frac{1+\frac{{\mathrm{R}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}}{1+\frac{{\mathrm{R}2}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}}\right){\mathrm{V}}_{\mathrm{I}\mathrm{r}\mathrm{e}\mathrm{f}}-\frac{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{\mathrm{V}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}\end{array}$$

(31)

Finally, if $\frac{{\mathrm{R}2}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}=\frac{{\mathrm{R}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}$, then

$${\mathrm{V}\mathrm{o}}_{\mathrm{s}\mathrm{u}\mathrm{b}}=\left(\frac{{\mathrm{R}3}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{R}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}}\right)\left({\mathrm{V}2}_{\mathrm{s}\mathrm{u}\mathrm{b}}-{\mathrm{V}1}_{\mathrm{s}\mathrm{u}\mathrm{b}}\right)$$

(32)

Stage 6 presents the PI controller, as shown in Figure 18. With a proper tuning of proportional gain K_p and the integral gain K_i, the error signal as discussed in stage 5 can be eliminated. For this purpose, the two variable resistors R_p and R_i are used to vary the amplitude of the error signal. First, R_p is set to 80 k$\mathsf{\Omega }$ to get K_p of 8. Then, R_i is set to 400 k$\mathsf{\Omega }$ to get K_i of 27. The error from the output of the subtractor circuit is the input to the proportional controller.

Meanwhile, two important notes must be taken. First, the output of proportional controller is inverted. Also, it has no offset. The input to the integral controller is the output of the proportional controller, or is defined as below:

$${\mathrm{V}\mathrm{i}\mathrm{n}}_{\mathrm{p}\mathrm{i}}=-{\mathrm{K}}_{\mathrm{p}}{\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}$$

(33)

With initial condition of Vo_i, the output of the integral controller is

$$\begin{array}{l}{\mathrm{V}\mathrm{o}}_{\mathrm{i}}=-\frac{1}{{\mathrm{R}}_{\mathrm{i}}{\mathrm{C}}_{\mathrm{i}}}\int {\mathrm{V}\mathrm{i}\mathrm{n}}_{\mathrm{p}\mathrm{i}}\mathrm{d}\mathrm{t}+{\mathrm{V}\mathrm{o}}_{\mathrm{p}}\\ =-{\mathrm{K}}_{\mathrm{i}}\int {\mathrm{V}\mathrm{i}\mathrm{n}}_{\mathrm{p}\mathrm{i}}\mathrm{d}\mathrm{t}+{\mathrm{V}\mathrm{o}}_{\mathrm{p}}\end{array}$$

(34)

Substituting ${\mathrm{V}\mathrm{i}\mathrm{n}}_{\mathrm{p}\mathrm{i}}=-{\mathrm{K}}_{\mathrm{p}}{\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}$ into Equation (34) gives

$$\begin{array}{l}{\mathrm{V}\mathrm{o}}_{\mathrm{i}}=-{\mathrm{K}}_{\mathrm{i}}\int \left(-{\mathrm{K}}_{\mathrm{p}}{\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}\right)\mathrm{d}\mathrm{t}+{\mathrm{V}\mathrm{o}}_{\mathrm{p}}\\ {\mathrm{V}\mathrm{o}}_{\mathrm{i}}={\mathrm{K}}_{\mathrm{p}}{\mathrm{K}}_{\mathrm{i}}\int \left({\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}\right)\mathrm{d}\mathrm{t}+{\mathrm{V}\mathrm{o}}_{\mathrm{p}}\end{array}$$

(35)

The summer is actually a different amplifier, or can be defined as below:

$$\begin{array}{c}{\mathrm{V}\mathrm{o}}_{\mathrm{s}\mathrm{u}\mathrm{m}}=\frac{10\mathrm{k}}{10\mathrm{k}}\left[\left({\mathrm{K}}_{\mathrm{p}}{\mathrm{K}}_{\mathrm{i}}\int {\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}\mathrm{d}\mathrm{t}+{\mathrm{V}\mathrm{o}}_{\mathrm{p}}\right)—{\mathrm{K}}_{\mathrm{p}}{\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}\right)\\ {\mathrm{V}\mathrm{o}}_{\mathrm{s}\mathrm{u}\mathrm{m}}={\mathrm{K}}_{\mathrm{p}}{\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}+{\mathrm{K}}_{\mathrm{p}}{\mathrm{K}}_{\mathrm{i}}\int \left({\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}\right)\mathrm{d}\mathrm{t}+{\mathrm{V}\mathrm{o}}_{\mathrm{p}}\end{array}$$

(36)

The Laplace transform of Equation (34) is

$${\mathrm{V}\mathrm{o}}_{\mathrm{s}\mathrm{u}\mathrm{m}}={\mathrm{K}}_{\mathrm{p}}{\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}+\frac{{\mathrm{K}}_{\mathrm{p}}{\mathrm{K}}_{\mathrm{i}}}{\mathrm{s}}{\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}$$

By rearranging it,

$$\frac{{\mathrm{V}\mathrm{o}}_{\mathrm{s}\mathrm{u}\mathrm{m}}}{{\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}}={\mathrm{K}}_{\mathrm{p}}\frac{\mathrm{s}+{\mathrm{K}}_{\mathrm{i}}}{\mathrm{s}}={\mathrm{K}}_{\mathrm{p}}\frac{{\mathrm{T}}_{\mathrm{i}}\mathrm{s}+1}{{\mathrm{T}}_{\mathrm{i}}\mathrm{s}}$$

(37)

where

$${\mathrm{T}}_{\mathrm{i}}=\frac{1}{{\mathrm{K}}_{\mathrm{i}}}={\mathrm{R}}_{\mathrm{i}}{\mathrm{C}}_{\mathrm{i}}$$

If R_i = 400 kΩ and C_i = 0.09 µF,

$${\mathrm{K}}_{\mathrm{i}}=\frac{1}{{\mathrm{R}}_{\mathrm{i}}{\mathrm{C}}_{\mathrm{i}}}=\frac{1}{\left(400\mathrm{k}\right)\left(0.09\mathsf{\mu }\right)}=27$$

Stage 7 represents the triangular carrier signal. The 10 kHz triangular carrier signal is used to represent the switching frequency of the APF.

In stage 8, the comparator circuit is used to generate the asynchronous PWM (APWM) signal by comparing the triangular carrier signal with the output signal of the PI controller. This APWM signal is used to control switches S3a and S1b for charging and discharging of boost inductor to perform the APF function.

Finally, in stage 9, the APWM separation circuit is developed for positive and negative cycle operations, by using two gates, an AND gate and an inverter gate. The separation is performed by comparing the generated APWM signal with the phase detector signal. The positive cycle is used to control S3a, while the negative the cycle is used to control S1b.

As mentioned in Section 1, the preliminary assessment was performed on the previous switching strategy in [23]. The switching strategy was implemented in the experimental work. However, the initial findings showed the output voltage of inverter operation was lower than expected with only 8 V. The designed target should be to producing at least 24 V in order for it to be possible to step the voltage up to 230 V using the step-up transformer connected to the grid. In addition, the boost inverter was used to boost output voltage, which, however, could only rise to 12 V. Therefore, further improvement to the switching algorithm is proposed, as detailed in the next subsections. The next subsections will explain the operation of the proposed UPS system in two designed modes: controlled rectifier (charging mode) and controlled inverter (discharging mode).

4.2. Controlled Rectifier Mode (Charging Mode)

The function of the controlled rectifier mode, also known as the charging mode, is to facilitate the conversion of AC from the grid to the DC required by the load [24,30]. This conversion process, when integrated with APF capabilities, involves two distinct operational phases: the positive and negative cycles. The APF’s role is pivotal in enhancing the quality of the supply current waveform, transforming it into a continuous, sinusoidal form that is synchronized with the supply voltage waveform. This adjustment significantly diminishes the THD and augments the power factor. Figure 19 elucidates the comprehensive mechanism of the controlled rectifier mode, whereas

Table 3. Switching strategy for rectifier operation.

Switch	Rectifier Mode
	Positive Cycle	Negative Cycle
S1a	ON	Off
S1b	Off	APWM
S2a	Off	Off
S2b	Off	ON
S3a	APWM	Off
S3b	Off	ON
S4a	ON	Off
S4b	Off	Off

details the specific switching strategy employed for both the positive and negative cycles. An in-depth exploration of each cycle’s operation is provided below.

• Step 1 (Positive Cycle):

During the positive cycle, the inductor L1 initiates energy accumulation as switches S1a and S3a remain activated and turned ON. S3a’s operation is modulated by the APWM signal emanating from the CCL.

• Step 2 (Positive Cycle):

Subsequently, as L1 transitions to the de-energization phase, the previously accumulated energy is relayed to capacitor C1, with switches S1a and S4a maintaining their active turned ON states to ensure a continuous flow of supply current.

• Step 3 (Negative Cycle):

Conversely, in the negative cycle, the energization of L1 commences with the activation of switches S3b turned ON and S1b APWM Signal. The flow of supply current through S1b is governed by the APWM signal from the CCL. In this mode of operation, the line inductor (L1) starts charging the energy base on the APWM pulse signal when the pair of switches S3b and S1b are turned ON.

• Step 4 (Negative Cycle):

In this negative cycle, consistently activated S3b turned ON, leads to the subsequent de-energization phase of L1. During this phase, the energy stored is dispensed to the resistive-capacitive (RC) load, facilitated by the continuous activation of switches S3b and S2b. The graphical representation of the waveforms pertaining to the charging mode is depicted in Figure 23, with the mode’s operation spanning from 0 to 40 ms.

4.3. Managed Inverter Phase (Energy Release Mode)

The functionality of the managed inverter phase (energy release mode) pertains to the transformation of DC to AC, facilitating the conversion of DC energy from a backup source into the AC format necessary for the load [22,30]. Utilizing a boost inverter for the DC to AC conversion process, this mode produces an AC output voltage that exceeds the initial DC input; this elevation in output voltage is achieved through the modulation index of SPWMs. The switching frequency of 5 kHz will generate signals of 50 pulses for half a cycle and 100 pulses for one full cycle. Therefore, to generate the SPWM signal by using the Arduino Uno controller, the time of the pulse signals is required. Thus, the sampling time for the half-cycle of the 5 kHz SPWM signal is captured from MATLAB/Simulink. The details of sampling time for the 5-kHz SPWM signal with the modulation index of 0.5 are presented in Appendix A. The Switching frequency is set to 5 kHz for experimental dan simulation test base on the previous work published in [31].

The input voltage of 12 V from a battery incorporated with a boost inductor of 2 mH is used to develop an output AC voltage of 24 V. The voltage level is enough to send it back to the grid via a 24/230 V step up transformer. During power outage condition, the voltage sensor senses the value of the supply voltage level as zero. The UPS operation automatically changed from charging mode to discharging mode. As previously highlighted, a switching strategy was devised to guarantee the generation of a minimum output voltage of 24 V, facilitating the amplification of voltage to 230 V via a step-up transformer for grid integration. This aspect of the research has been meticulously focused on the switching technique within the managed inverter phase, ensuring its practical applicability for experimental validation on a test rig.

Figure 20 delineates the comprehensive mechanism of the managed inverter phase, incorporating a safe-commutation feature alongside innovative switching strategies for both the positive and negative cycles. Concurrently,

Table 4. Switching algorithm of inverter operation mode for UPS system.

Inverter Operation	Positive Cycle		Negative Cycle
	Switching	Starting Pulse	Switching	Starting Pulse
S1a	Off	Off	Off	Off
S1b	ON	High	Off	Off
S2a	Off	Off	ON	High
S2b	Off	Off	Off	Off
S3a	SPWM	Low	SPWM	High
S3b	Off	Off	Off	Off
S4a	Off	Off	Off	Off
S4b	SPWM	Low	SPWM	High

outlines the specified switching strategy and pulse signals designated for each cycle. An expanded explanation for the operational dynamics of each cycle is provided.

• Positive cycle:

Step 1: For the positive cycle operation, the Arduino Uno controller generates the 1st to 50th pulses of the SPWM signal. As shown in Figure 21, for S3a, the 1st pulse is generated after a delay time (OFF state) of 97 μs, then the ON state of 6 μs, before it turns to the OFF state for 188 μs. The process is continuous until the Arduino Uno controller generates the 50th pulse as illustrated in Figure 22. Figure 22 illustrates generation of the SPWM signal using the Arduino Uno controller based on the sampling time as tabulated in Appendix A.

For S4b, the 1st pulse is generated to be the ON state of 97 μs, then the OFF state of 6 μs, before it turns to the ON state for 188μs. The process is continuous until the Arduino Uno controller generates the 50th pulse as illustrated in Figure 22.

Step 2: Energy is stored in the boost inductor as current flows from the 12V battery supply through the combination of switches S3a and S4b.

Step 3: Subsequently, the energy previously accumulated is conveyed to the load via the switch pair S1b and S4b, marking the transition of DC power to the AC load during the positive half-cycle of the boost inverter operation. To facilitate this process, switch S1b is activated to the ‘ON’ position, whereas switches S3a and S4b are modulated by the SPWM signal, employing a modulation index set at 0.5.

• Negative cycle:

Step 1: For the negative cycle operation, the Arduino Uno controller generates the 51st to 100th pulses. The generation of SPWM signal for this cycle is also shown Figure 18 and Appendix A. For S3a, the 51st pulse is generated after a delay time (OFF state) of 199 μs, then the ON state of 2 μs, before it turns to the OFF state for 197 μs. The process is continuous until the 100th pulse as also illustrated in Figure 22.

For S4b, the 51st pulse in this cycle is generated to be ON state of 199 μs, then the OFF state of 2 μs, before turning to the ON state for 197 μs. The process is continuous until the the 100th pulse is generated.

Step 2: The configuration of the SPWM is designated as step 1, wherein switch S1b is deactivated, and the duo of S3a and S4b remains under the regulation of the SPWM, also in accordance with step 1. During this phase, the initiation of the SPWM signal is characterized by a high pulse pattern, specifically tailored for the negative half-cycle.

Step 3: During this phase, current is drawn from the 12V battery supply and directed towards the AC load via S3a, then returns through S2a. Consequently, this facilitates the conversion of DC power to the AC load, executing the boost function of the inverter throughout the negative half-cycle.

The waveforms of the discharging mode are shown in Figure 23, operating after the charging mode. The period assigned for this mode is from 40 to 80 ms.

5. Simulation Model and Experimental Test Rig

The developed UPS system, based on the SPMC topology, was subjected to simulation within the MATLAB/Simulink environment. As delineated in the preceding discussion, the adoption of a novel switching strategy is pivotal for amalgamating the functionalities of both the rectifier and the inverter, as detailed in Table 3 and Table 4. The specifications for the UPS under consideration are itemized in

Table 5. Parameters for experimental test rig.

Parameter	Value
AC supply voltage, Vac	24 V
DC supply voltage, Vdc	12 V
Boost inductor, Ls	2 mH
Inductor load, LL	5 mH
Capacitor load, CL	1000 μF
Resistive load, RL	300 Ω
Switching frequency for rectifier, fs	10 kHz
Switching frequency for inverter, fs	5 kHz
Proportional gain, Kp	8
Integral gain, Ki	27

, with parameter values aligned with those typically encountered in UPS systems, referencing [24,32,33,34,35].

Figure 24 delineates the circuit’s three primary components of the proposed UPS configuration. In this analysis, a step response methodology is employed to assess the transition duration between the rectifier and inverter phases. Specifically, the rectifier phase is analysed over a sample period from 0 to 0.04 s, while the inverter phase spans from 0.04 to 0.08 s.

To facilitate seamless transitions at t = 0.04 s, a pair of breaker switches are strategically implemented to concurrently manage the supply and load functionalities, as depicted in Figure 24. In the charging phase, from 0 to 0.04 s, the rectifier signal breaker (B) is activated, whereas the inverter signal breaker (A) is deactivated. The shift to inverter operation is initiated at t = 0.04 s, during which B is deactivated, and A is activated, ensuring a smooth transition between operational modes.

In the experimental work, the proposed UPS using SPMC topology was constructed and tested to validate its performance as done in the simulation. In this work, a 24 V AC supply is used to produce at least 15 V output DC voltage to charge a 12 V battery. The 12 V RS 698-8091 Pro Lead-acid batteries are used, which are also well known across several industries and for general purposes. The battery is sealed and ideal for use in UPS and emergency back-up [32].

In the first stage, the Arduino UNO controller is programmed to generate 5-kHz PWM signal to control the SPMC circuit to investigate operation of the controlled rectifier. Further construction has been developed for the controlled rectifier operation using RC load to represent the non-linear load without and with the APF function as shown in Figure 25. This work uses a 10 kHz switching frequency to generate an APWM signal [36].

Next, in the second stage, the construction and implementation of the experimental test rig are continued with the controlled inverter operation as shown in Figure 26. The 12V DC supply from the battery is used in this work, as discussed in the previous subsection. The 5-kHz SPWM signal is used to control the SPMC. The construction and implementation of the controlled inverter are using R and RL loads without and with safe-commutation strategy.

The third stage presents the construction and implementation of the proposed UPS system, as it full schematic diagram is shown in Figure 27. Meanwhile, the experimental test rig is shown in Figure 28.

6. Results

Figure 29 presents the experimental test rig results for the supply current and voltage waveforms using a controlled rectifier with a non-linear load, without the active power filter (APF) function. The results indicate a misalignment and distortion between the supply current and voltage, leading to high total harmonic distortion (THD) levels and reduced efficiency. This distortion adversely affects the supply current waveform, resulting in associated issues such as poor overall power factor, heating effects, device malfunction, and potential damage to other equipment due to nonlinear loads.

The harmonic content of the distorted supply current waveform, as determined through both simulation and experimental means, is showcased in Figure 30 and Figure 31, benchmarked against the IEEE 519-2022 standard [37]. The THD percentages recorded were 189.85% for the simulation and 114.65% for the experimental setup, both exceeding the prescribed standards. These elevated THD levels corroborate prior findings regarding significant harmonic presence, as introduced in Section 1, indicating severe distortion in the supply current that could lead to reduced power factor, overheating, equipment malfunction, and damage.

Comparative analysis of the supply current and voltage for the controlled rectifier equipped with APF functionality is presented in Figure 32 and Figure 33, showing successful harmonic compensation. In the charging mode of operation, the UPS operates with APF function consisting of the absolute circuit for supply distorted current and reference signal, subtractor circuit, PI controller circuit, comparator circuit, and APWM separation circuit to compensate for the distorted supply current waveform to become continuous, sinusoidal and in phase with the supply voltage waveform resulting in high power factor and low THD level.

Further, Figure 34 and Figure 35 display the harmonic spectrum and THD levels for the supply current, adhering to the IEEE 519-2022 Standard, from both simulation and experimental evaluations. THD percentages were found to be significantly lower at 3.59% and 7.81%, respectively, indicating compliance with the standard.

The proposed switching strategy for a controlled boost inverter with a passive filter has demonstrated its efficacy in successfully generating the desired output voltage suitable for grid supply. As evidenced in Figure 36 and Figure 37, the inverter effectively boosts the input voltage of 12 V DC from a battery to generate an output AC voltage of 38 V. This output voltage is sufficient for a transformer to step up the voltage to 415 V AC, which is the required level for grid integration.

Additionally, Figure 38 presents the simulation outcomes for the UPS system’s supply voltage during both charging and discharging phases, utilizing the developed switching algorithm and a step response block to manage transition timing. Operational timings were defined as 0 to 0.04 s for charging and 0.04 to 0.08 s for discharging, aiming to assess the system’s operational fluidity.

Experimental validations are further extended, as shown in Figure 39, which illustrates the supply voltage and current during the UPS system’s charging and discharging modes, demonstrating a harmonious correlation between simulation and experimental data. The transitions between modes were smooth, indicating the controller’s effectiveness in adapting to operational shifts. Notably, the supply current exhibited a sinusoidal form, aligning with the supply voltage, thereby reducing THD levels and enhancing power factor. Simulation results indicated a THD level of 6.59% and a power factor of 0.9996, whereas experimental findings reported a THD of 7.86% and a power factor of 0.9715, as measured by a YOKOGAWA WT333E Digital Power Meter (Yokogawa Test & Measurement Corporation, Tokyo, Japan).

Comparisons of harmonic spectra against the IEEE 519-2022 standard in Figure 40 and Figure 41 confirm that the harmonic levels are within acceptable limits and meet the standard’s requirements.

Table 6. Performance Comparison of Simulation and Experimental Test rig.

Strategies		THD (%)	Power Factor (pf)
Rectifier without APF	Simulation	189.85	0.6248
	Experimental test rig	114.65	0.6391
Rectifier with APF	Simulation	3.59	0.9996
	Experimental test rig	7.81	0.9725
UPS with APF	Simulation	3.59	0.9996
	Experimental test rig	7.86	0.9715

consolidates the comparative outcomes for the simulation and experimental setups, both with and without APF functionality, underscoring the APF’s role in diminishing THD levels and improving power factor. The observed discrepancy in THD levels between the simulation and experimental setups can be attributed to the inductive effects of the step-down transformer windings, highlighting the APF function’s critical impact on reducing THD when combined with a suitably designed switching algorithm.

7. Conclusions

This paper elaborates on the effective deployment of a UPS system utilizing SPMC circuit architecture, enhanced with APF capabilities. The designed UPS, an integrated SPMC unit, is adept at fulfilling both rectifying and inverting functions, potentially obviating the need for separate rectifier and inverter circuits found in traditional UPS configurations. The investigation encompassed the UPS’s performance in both charging (rectifier) and discharging (inverter) modes. Furthermore, the incorporation of APF functionality through a boost technique effectively mitigates the fluctuations in the supply current waveform, rendering it continuous, sinusoidal, and synchronized with the supply voltage waveform, thereby elevating the power supply system’s quality. Consequently, the THD of the supply current was significantly diminished to levels below those stipulated by the IEEE519-2022 standard. Moreover, the transition duration between the UPS’s charging and discharging modes aligns with the specifications of the IEC62040-3 standard [38]. This study’s paramount contribution lies in advancing UPS design UPS using SPMC topology, which could be extended for development of various advanced applications such as wireless power charging, fast and high-density micro charging, micro UPS, etc. This is in line with the rapidly evolving global manufacturing landscape that calls for high quality and availability of power supply and can contribute to various applications, from electric vehicles (EVs) to biological implants such as pacemakers in medical technology industries. Future studies could engage in comparative analyses with alternative topologies, assessing higher ratings and efficiency to further endorse the proposed UPS’s potential and applicability.