An Improved Cascaded Boost Converter with an Ultra-High Voltage Gain Suitable for Dielectric Quality Tests

Abstract

Dielectric quality tests require a high AC voltage with a frequency range of 0.0001 Hz to 1000 Hz. However, providing a high AC voltage with such a frequency variety is challenging. Providing a high DC voltage and then applying such a voltage to an inverter to adjust the frequency can be an acceptable solution for such a challenge. Notably, a high DC voltage is required for DC tests. This study proposes an improved form of the cascaded boost converter, whose merits are as follows: (i) the high voltage gain providing low duty cycles is possible; (ii) the input current is continuous, which decreases the current ripple of the input filter capacitor; (iii) the current stress of the semiconductors is less than the input current, and most of them have a large difference with it; (iv) the voltage stress of the semiconductors is less than the output voltage with a large difference; (v) only one switch with a simple drive circuit is used; (vi) the common ground of the load and input source decreases the EMI noise; (vii) besides the high voltage gain, the voltage density of the converter based on the number of inductors, capacitors, switches, diodes, and whole components is greater than that of the recently proposed converters; (viii) only two stacked connections of the proposed topology can provide a 2.6 kV voltage for a higher DC voltage test of dielectrics. The functional details of the converter are extracted in ideal and continuous conduction (CCM) modes. Moreover, the converter’s voltage gain and density are compared with the recently proposed converters to show the superiority of the proposed converter. Finally, the experimental results are presented to validate the theoretical relations in a 140 W output power.

1. Introduction

Isolated DC–DC converters employ high-frequency transformers to achieve high voltage gain values [1]. The coil’s turn ratio plays an essential role in increasing voltage gain [2]. However, employing isolated DC–DC converters increases the converters’ volume and mass [3]. Moreover, the load isolation from the input source leads to EMI noises. Additionally, the coils’ leakage inductance and residual current cause issues during the switch’s inactivation. In other words, a considerable voltage stress is applied to the switch, which can cause its failure [4]. Solving such a problem requires using the snubber circuits to dissipate the loss of the residual currents in an unimportant part [5,6]. Using the snubbers does not change the efficiency but increases the converter’s complexity [7]. Moreover, the input current of the isolated converters is discontinuous, which increases the current stress of the input filter capacitor [8]. All these concepts lead to the use of non-isolated DC–DC converters in such an application, which does not require the isolation of the load and input source [9].

Among classic non-isolated DC–DC converters, boost topology is the most popular one. It has a continuous input current with a negligible ripple. The common ground of the load and input source is provided. Consequently, the EMI noise problems are solved. The employed switch is low-sided with a simple drive circuit. Finally, the converter has a step-up behavior in all duty cycles. Besides all the mentioned advantages, there are some disadvantages with this topology. The first disadvantage is the voltage stress of the semiconductors in this topology. Notably, the voltage stress of the semiconductors is the same as the output voltage. In other words, an increase in output voltage leads to an increase in voltage stress. The second problem is the lack of high voltage gain providing. As the duty cycle approaches 80%, the voltage gain of the boost topology increases five-fold. Additionally, a 10-times voltage gain requires a 90% duty cycle. It can be understood that the higher voltage gain values lead to the duty cycle approaching unity. However, employing such a duty cycle is not possible. In other words, using a duty cycle close to unity decreases the conduction time of the diode to zero. However, the physical limits of the diodes do not allow for such a condition. Moreover, in a practical mode, the duty cycle approaching unity does not lead to the voltage gain’s increase due to the parasitic elements of the circuit components. Consequently, such a converter cannot provide a high voltage gain. A simple way to increase the voltage gain is the cascaded connection of two boost converters. Figure 1a presents the power circuit of the cascaded boost topology. All the advantages of the boost topology are present in this converter. Moreover, its voltage gain is the quadratic form of the boost one. Consequently, it has a higher voltage gain than a boost converter. Notably, the voltage stress of the switch and the last diode in this topology is the same as the output voltage. Consequently, the disadvantage of the boost topology is repeated. Another way to increase the voltage gain of the boost topology is the voltage lift technique. This technique uses diode–capacitor or diode–capacitor–inductor voltage multiplier cells to increase the voltage gain. In this method, a voltage is copied in the capacitors, and in the following operating mode, the capacitors’ voltages are summed up with each other. Figure 1b–e present the improved boost topologies with voltage multiplier cells. The voltage gain provided by the first to third improved boost topologies is twice that of the boost converter. Notably, the voltage gain of the fourth improved boost converter is three times that of the boost one. Besides the voltage gain increase, the voltage stress of the semiconductors is less than the output voltage in the second to fourth improved boost converters. However, the first one has the same disadvantage of the boost and cascaded boost topologies. Figure 2 presents the voltage gain comparison of the boost, cascaded boost, and improved boost topologies. All the improved and cascaded boost converters have a higher voltage gain than the boost one. Additionally, the improved boost topologies function better at low-percentage duty cycles. Moreover, the cascaded boost converter needs a duty cycle higher than 70% to provide a higher voltage gain than the rest. Another common concept about the improved topologies is that all of them require a high percentage of the duty cycle to provide a voltage gain of more than ten times.

The topologies in [10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39] combine classic non-isolated DC–DC converters. The presented topologies in [10,19,20,21,23,26,28,29,39] are the combination of buck-boost, Cuk, Sepic, and zeta converters. The function of these converters is acceptable in the step-down or pass-through modes. However, these converters’ step-up mode is unacceptable and cannot provide higher voltage gains. Additionally, their voltage gain is less than the boost converter, while the duty cycle is less than 65%. Furthermore, such a low voltage gain is provided by more components than the classic boost converter. Besides all the mentioned disadvantages, the semiconductors close to the output terminal experience a voltage stress higher than the voltage provided at the output. The presented topologies in [11,12,15,17,27,33,35,37] use a boost topology besides a buck-boost, Cuk, SEPIC, or Zeta converter. Their output voltage is higher than the last group. However, it is not higher than the boost converter in all duty cycles. Consequently, besides using more components than the boost topology, the provided voltage gain is unacceptable. Also, some semiconductors face a voltage more than the output voltage. Another common drawback in the discussed topologies is the use of Cuk, SEPIC, and Zeta converters, which increases the number of components spatially bythe magnetic base components without providing the desired voltage gain and semiconductor voltage stress. The presented topologies in [13,16,25,30,31,32,36,38] are quadratic boost topologies like the cascaded boost topology. However, the number of switches exceeds that of the cascaded boost converter. The voltage stress of the semiconductors has the same condition as in the cascaded boost topology. The presented topologies in [14,40] are the improved form of the Cuk and SEPIC converters. The voltage gain provided is twice that of the Cuk and SEPIC. However, this improvement is not sensible and unacceptable compared with the increase in the number of components. The same idea was employed in [18,22,24]; however, the achievement of [24] is better than the rest. The voltage gain is more than the cascaded boost converter. However, this voltage gain is not more than ten times at the low duty cycle percentages. Ref. [34] presents the stack connection of the boost and buck-boost topologies. The provided voltage gain is the summation of the individual converters. The voltage stresses become less than the output voltage with such a simple method. However, the voltage gain is not as high as desired. The proposed topologies in [40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60] use the inductor–diode–capacitor voltage multiplier cells to employ the voltage lift technique. The extracted voltage gain from [41,43] is four times and twice the boost converter. However, they lack the common ground of the load and input source. The number of magnetic-based components in [42] is three times the boost topology. However, the voltage gain does not have a high increase. Ref. [44] employed nine diodes, five inductors, three capacitors, and one switch. However, the provided voltage is almost three times the boost converter at a low duty cycle percentage. Moreover, some semiconductors face a voltage stress higher than the output voltage. Such disadvantages are repeated in [45]. Refs. [46,47] provides the same voltage gain with the same number of components. These converters employ two switches in the power circuit. However, the provided voltage gain is not as high as desired. Ref. [48] is an improved buck-boost topology. Its voltage gain is more than the classic buck-boost one. However, the main drawbacks of the buck-boost topology are present in this converter. Additionally, the magnet-based components are many, which decreases the power density of this topology. Moreover, the increase in voltage gain is not sensible compared with the increase in components. Ref. [49] is an improved form of the SEPIC topology. It uses one inductor, four capacitors, and diodes more than the classic SEPIC topology. However, the voltage gain increase is not bold. Refs. [50,53] combine boost and super lift luo converters. Their voltage gain is more than the cascaded boost topology. Moreover, the voltage stress problem of the cascaded boost topology is solved. However, the extracted voltage gain cannot provide a ten-times voltage gain with low duty cycle percentages. The proposed topologies in [51,52,53,54,55,56,57,58,59,60] are the improved form of the cascaded boost converters. Their voltage gain can be achieved ten times with a low percentage of duty cycles. Moreover, the voltage stress of the semiconductors is less than the output voltage. These features are acceptable for renewable energy applications. However, a high-voltage DC test equipment, which is used in dielectric tests, is not suitable. Moreover, in such applications, low voltage stresses are required to be applied to the components. Consequently, the voltage stresses must be less than the output voltage with a large difference. All these converters are based on the use of the classic converters without using any coupled inductors and transformers. The voltage lift, which is explained at the beginning of this paper, is explained in more detail in [61] for various topologies. One of this technique’s prominent disadvantages is the increase in the number of components. In other words, the voltage gain can be increased by using more inductor–diode cells or more diode–capacitor structures. The first method increases the mass and volume of the converter and decreases the power density. However, using diode–capacitor structures increases the voltage gain without increasing mass and volume. Notably, the capacitors have a lower mass, volume, cost, and loss compared with inductors. The MKT and MKP types of capacitors have a negligible equivalent series resistance (ESR), high capacitance, and high voltage range. Consequently, they can be used for DC links. Unfortunately, the topologies presented in [61] used more inductors, which increased the loss. The application of the converter has an essential effect on converter design. For example, the topologies presented in [62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85] are recommended to be used in renewable energy sites such as photovoltaic farms, fuel cells, and hydrogen electrolysis. In these studies, their features in control and employing MMPT methods are prominent, and providing ultra-high gain values is not expected. It is good to mention that renewable energy resources provide a voltage gain of 15 V to 60 V. Consequently, a converter with a ten-times voltage gain can be easily used in such an application. However, the equipment used in dielectric tests is not suitable. Other types of converters are based on the use of a couple of inductors in the power circuit. As with the isolated converters, the turn ratio of the coils appears as a coefficient in the voltage gain and makes the converter independent on using a high percentage of the duty cycle. Moreover, employing the couple inductors can solve the non-minimum phase behavior of the converter. All the topologies presented in [86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142] are the newly proposed converters of this type. Unfortunately, using the coupled inductors and their leakage inductances increases the losses and forces high voltage stresses on the converters’ switch. Hence, snubber circuits and extra circuits or procedures are required to solve the mentioned problems and maintain efficiency at higher values. However, employing the mentioned circuits increases the number of components and the complexity of the converter control. Furthermore, a decrease in reliability, according to this happening, is significant. Consequently, employing a couple of inductors in the power circuit causes the same problems as the isolated converters. The topologies in [143,144,145,146,147,148,149,150,151,152,153,154] are topologies based on boost topology that have been presented for renewable applications. According to the mentioned application, ultra-high voltage gain values are not accessible in this group of converters.

This paper proposes an improved cascaded boost topology. The topology of the cascaded boost topology is improved by diode–inductor–capacitor and diode–capacitor voltage multiplier cells. This improvement creates a high-voltage-lift value suitable for high-voltage test applications. There is only one switch in the power circuit. Moreover, as with the boost topology, the continuity of the input current and common ground of the load and input source are present. Notably, besides the high voltage gain value, the voltage stress of the semiconductors is less than the output voltage. In other words, the highest value of the voltage stress is one-third of the output voltage. Consequently, the voltage stress challenge of the conventional boost and cascaded boost is solved in this topology.

2. Proposed Topology in the Ideal Mode

The proposed topology is presented in Figure 3. According to this figure, two kinds of voltage multiplier cells improve the cascaded boost topology. The beginning part of the boost topologies is modified by an inductor–diode–capacitor voltage multiplier cell. This voltage multiplier cell increases the voltage gain of the boost converter two-fold. The end part of the boost converters is modified by a diode–capacitor voltage multiplier cell. This diode–capacitor voltage multiplier cell increases the boost topology voltage gain three-fold. This topology is a one-switch converter. There are two operational modes for the proposed topology in the ideal mode and the steady state. The equivalent circuit of the first operating mode is shown in Figure 3. According to this figure, the first, second, fourth, sixth, eighth, ninth, tenth, twelfth, and fourteenth diodes beside the switch are activated. According to the equivalent circuit of the converter in this mode, the first capacitor with the input source, the second capacitor with the third one, the sixth capacitor with the seventh one, and the eighth capacitor with the ninth one become parallel with each other. Therefore, their voltages become the same. Additionally, the series connection of the third to fifth capacitors is parallel with the sixth capacitor, and the series connection of the ninth to eleventh capacitors is parallel with the output capacitor. All the applied voltages to the inductors are positive, and all of them become magnetized. The equivalent circuit of the second operating mode is shown in Figure 3c. According to this figure, the third, fifth, seventh, eleventh, thirteenth, and fourteenth diodes are activated. In this circuit, the fourth capacitor with the fifth and the tenth capacitors with the eleventh ones are parallel. Moreover, the series connection of the second to fourth capacitors is parallel with the sixth capacitor and the series connection of the eighth to tenth capacitors with output one. According to the expressed concepts, the voltage equation of the inductors is as follows:

$$\left\{\begin{array}{c}{V}_{L1}=D\left(V_{in}\right)+(1-D)(V_{in}+V_{C1}-V^{\prime })\hfill \\ V_{L2}=D\left(V_{in}\right)+(1-D)(V^{\prime }-V_{C2})\hfill \\ V_{L3}=D\left(V_{C6}\right)+(1-D)(V_{C6}+V_{C7}-V^{″})\hfill \\ V_{L4}=D\left(V_{C6}\right)+(1-D)(V^{″}-V_{C8})\hfill \end{array}\right.$$

(1)

In this equation, V′ stands for the common node voltage of the first diode, first capacitor, and second inductor. Additionally, V″ is the common node voltage of the eighth diode, seventh capacitor, and fourth capacitor.

The current equation of the capacitors according to the equivalent circuits and the expressed concepts are as follows:

$$\left\{\begin{array}{c}{i}_{C1}=D\left(i_1\right)+(1-D)(-i_{L1})\hfill \\ i_{C2}=D(-i_2)+(1-D)(i_{L1}-i_3)\hfill \\ i_{C3}=D(i_2+i_6)+(1-D)(-i_3)\hfill \\ i_{C4}=D\left(i_6\right)+(1-D)(-i_4)\hfill \\ i_{C5}=D\left(i_6\right)+(1-D)(-i_3+i_4)\hfill \\ i_{C6}=D(-i_6-i_7-i_{L3}-i_{L4})+(1-D)(i_3-i_{L3})\hfill \\ i_{C7}=D\left(i_7\right)+(1-D)(-i_{L3})\hfill \\ i_{C8}=D(-i_8)+(1-D)(i_{L3}-i_9)\hfill \\ i_{C9}=D(i_8+i_{12})+(1-D)(-i_9)\hfill \\ i_{C10}=D\left(i_{12}\right)+(1-D)(-i_{10})\hfill \\ i_{C11}=D\left(i_{12}\right)+(1-D)(-i_9+i_{10})\hfill \\ i_{Co}=D(-i_{12}-I_o)+(1-D)(i_{C9}-I_o)\hfill \end{array}\right.$$

(2)

In this equation, $i_1$ stands for the inrush current of the first capacitor when it becomes parallel to the input source. $i_2$ stands for the inrush current of the second capacitor while it is parallel to the third capacitor. Notably, $i_6$ is the inrush current of the sixth capacitor as it becomes parallel to the series connection of the third to fifth capacitors. $i_7$ is the inrush current of the seventh capacitor, which becomes parallel to the sixth capacitor. $i_8$ is the inrush current of the eighth capacitor when it is paralleled to the ninth capacitor. $i_{12}$ is the inrush current of the output capacitor as it becomes parallel to the series connection of the ninth to eleventh capacitors. $i_3$ is the inrush current of the third capacitor while its series connection with the second and fifth capacitors is parallel to the sixth capacitor. $i_4$ is the inrush current of the fourth capacitor, which becomes parallel to the fifth capacitor. $i_9$ is the inrush current of the series connection of the eighth, ninth, and eleventh capacitors when it becomes parallel to the output capacitor. $i_{10}$ is the created inrush current by the parallel connection of the tenth and eleventh capacitors.

It is good to note that the average voltage of the inductors is zero according to the voltage’s second balance. Consequently, all the Equations in (1) are equal to zero. Based on this fact, the average voltage of the capacitors becomes accessible as follows:

$$\left\{\begin{array}{c}{V}_{C1}=V_{in},V_{C2}=V_{C3}={\displaystyle \frac{2}{1-D}}{V}_{in},V_{C3}=V_{C4}=V_{C5}={\displaystyle \frac{2}{1-D}}{V}_{in}\hfill \\ V_{C6}=V_{C7}={\displaystyle \frac{6}{1-D}}{V}_{in},V_{C8}=V_{C9}=V_{C10}=V_{C11}={\displaystyle \frac{12}{{(1-D)}^2}}{V}_{in},V_o={\left({\displaystyle \frac{6}{1-D}}\right)}^2{V}_{in}\hfill \end{array}\right.$$

(3)

According to the current’s second balance, the average current of the capacitors is zero. Solving the capacitors’ current equation according to the mentioned concept leads to the inductors’ and inrush currents’ average values as follows:

$$\left\{\begin{array}{c}{I}_{L1}=I_{L2}={\displaystyle \frac{18}{{(1-D)}^2}}{I}_o,I_{L3}=I_{L4}={\displaystyle \frac{3}{1-D}}{I}_o,i_1={\displaystyle \frac{18}{D(1-D)}}{I}_o,i_2={\displaystyle \frac{6}{D(1-D)}}{I}_o\hfill \\ i_3={\displaystyle \frac{12}{{(1-D)}^2}}{I}_o,i_4={\displaystyle \frac{6}{{(1-D)}^2}}{I}_o,i_6={\displaystyle \frac{6}{D(1-D)}}{I}_o,i_7={\displaystyle \frac{3}{D}}{I}_o\hfill \\ i_8={\displaystyle \frac{I_o}{D}},i_9={\displaystyle \frac{2}{1-D}}{I}_o,i_{10}={\displaystyle \frac{I_o}{1-D}},i_{12}={\displaystyle \frac{I_o}{D}}\hfill \end{array}\right.$$

(4)

According to the extracted relation of the voltage gain, it can be understood that the provided voltage gain by this topology is 36 times more than the conventional cascaded boost topology. Figure 4 presents the voltage gain comparing the boost and cascaded boost topologies with the proposed converter. It can be understood that the voltage gain values provided by the proposed topology at the low-duty cycles are not accessible for the boost and cascaded boost topologies at higher-duty cycles.

According to the extracted values for the capacitors’ voltage, inductors’ current, and capacitors’ inrush currents, the semiconductors’ voltage and current stress are as follows. Notably, the semiconductors’ current stress is the average crossing current from the semiconductors during their activation, and the voltage stress is the peak value of the applied voltage during their inactivation mode.

$$\left\{\begin{array}{c}{I}_S={\displaystyle \frac{35+2D-D^2}{{(1-D)}^2}}{I}_o,I_{D1}=I_{D2}={\displaystyle \frac{18}{{(1-D)}^2}}{I}_o\hfill \\ I_{D3}=I_{D4}=I_{D5}=I_{D6}=I_{D7}={\displaystyle \frac{6}{1-D}}{I}_o\hfill \\ I_{D8}=I_{D9}={\displaystyle \frac{3}{1-D}}{I}_o,I_{D10}={\displaystyle \frac{5+D}{1-D}}{I}_o\hfill \\ I_{D11}=I_{D12}=I_{D13}=I_{D14}=I_{D15}=I_o\hfill \end{array}\right.$$

(5)

$$\left\{\begin{array}{c}{V}_{D1}=V_{D2}={\displaystyle \frac{V_{in}}{1-D}},V_{D3}=V_{D4}=V_{D5}=V_{D6}=V_{D7}={\displaystyle \frac{2}{1-D}}{V}_{in}\hfill \\ V_{D8}=V_{D9}={\displaystyle \frac{6}{{(1-D)}^2}}{V}_{in},V_S=V_{D11}=V_{D12}=V_{D13}=V_{D14}=V_{D15}={\displaystyle \frac{12}{{(1-D)}^2}}{V}_{in}\hfill \end{array}\right.$$

(6)

Figure 5 presents the normalized voltage/current stress of the semiconductors. Notably, the output voltage is the base voltage of voltage stresses. Additionally, the input current is considered as the base current of the current stresses. According to this figure, all the normalized voltage/current stresses are less than unity. Notably, the current stress of the eleventh to fifteenth diodes is the same as the output current, which is the lowest current in this topology. The highest current stress of the diodes belongs to the first and second diodes, which is half of the input current. Furthermore, the highest current stress is for the switch, whose current stress is less than the input current at the maximum duty cycle.

Among the voltage stresses, the tenth to fifteenth diodes and the switch have the highest voltage stress, which is one-third of the output voltage. It can be understood that all the semiconductors have an acceptable condition in this topology.

The simplified form of the inductors’ current ripple and capacitors’ voltage ripple are as follows:

$$\left\{\begin{array}{c}\Delta i_{L1}={\displaystyle \frac{1}{L_1}}{\int }_0^{D{T}_s}{V}_{L1}\left(t\right)dt={\displaystyle \frac{1}{L_1}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{V}_{L1}\left(t\right)dt={\displaystyle \frac{D{V}_{in}}{L_1{f}_s}}\hfill \\ \Delta i_{L2}={\displaystyle \frac{1}{L_2}}{\int }_0^{D{T}_s}{V}_{L2}\left(t\right)dt={\displaystyle \frac{1}{L_2}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{V}_{L2}\left(t\right)dt={\displaystyle \frac{D{V}_{in}}{L_2{f}_s}}\hfill \\ \Delta i_{L3}={\displaystyle \frac{1}{L_3}}{\int }_0^{D{T}_s}{V}_{L3}\left(t\right)dt={\displaystyle \frac{1}{L_3}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{V}_{L3}\left(t\right)dt={\displaystyle \frac{6D{V}_{in}}{(1-D)L_3{f}_s}}\hfill \\ \Delta i_{L4}={\displaystyle \frac{1}{L_4}}{\int }_0^{D{T}_s}{V}_{L4}\left(t\right)dt={\displaystyle \frac{1}{L_4}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{V}_{L4}\left(t\right)dt={\displaystyle \frac{6D{V}_{in}}{(1-D)L_4{f}_s}}\hfill \end{array}\right.$$

(7)

$$\left\{\begin{array}{c}\Delta V_{C1}={\displaystyle \frac{1}{C_1}}{\int }_0^{D{T}_s}{i}_{C1}\left(t\right)dt={\displaystyle \frac{1}{C_1}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C1}\left(t\right)dt={\displaystyle \frac{18I_o}{(1-D)C_1{f}_s}}\hfill \\ \Delta V_{C2}={\displaystyle \frac{1}{C_2}}{\int }_0^{D{T}_s}{i}_{C2}\left(t\right)dt={\displaystyle \frac{1}{C_2}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C2}\left(t\right)dt={\displaystyle \frac{6I_o}{(1-D)C_2{f}_s}}\hfill \\ \Delta V_{C3}={\displaystyle \frac{1}{C_3}}{\int }_0^{D{T}_s}{i}_{C3}\left(t\right)dt={\displaystyle \frac{1}{C_3}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C3}\left(t\right)dt={\displaystyle \frac{12I_o}{(1-D)C_3{f}_s}}\hfill \\ \Delta V_{C4}={\displaystyle \frac{1}{C_4}}{\int }_0^{D{T}_s}{i}_{C4}\left(t\right)dt={\displaystyle \frac{1}{C_4}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C4}\left(t\right)dt={\displaystyle \frac{6I_o}{(1-D)C_4{f}_s}}\hfill \\ \Delta V_{C5}={\displaystyle \frac{1}{C_5}}{\int }_0^{D{T}_s}{i}_{C5}\left(t\right)dt={\displaystyle \frac{1}{C_5}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C5}\left(t\right)dt={\displaystyle \frac{6I_o}{(1-D)C_5{f}_s}}\hfill \\ \Delta V_{C6}={\displaystyle \frac{1}{C_6}}{\int }_0^{D{T}_s}{i}_{C6}\left(t\right)dt={\displaystyle \frac{1}{C_6}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C6}\left(t\right)dt={\displaystyle \frac{3(3+D)I_o}{(1-D)C_6{f}_s}}\hfill \\ \Delta V_{C7}={\displaystyle \frac{1}{C_7}}{\int }_0^{D{T}_s}{i}_{C7}\left(t\right)dt={\displaystyle \frac{1}{C_7}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C7}\left(t\right)dt={\displaystyle \frac{3I_o}{C_7{f}_s}}\hfill \\ \Delta V_{C8}={\displaystyle \frac{1}{C_8}}{\int }_0^{D{T}_s}{i}_{C8}\left(t\right)dt={\displaystyle \frac{1}{C_8}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C8}\left(t\right)dt={\displaystyle \frac{I_o}{C_8{f}_s}}\hfill \\ \Delta V_{C9}={\displaystyle \frac{1}{C_9}}{\int }_0^{D{T}_s}{i}_{C9}\left(t\right)dt={\displaystyle \frac{1}{C_9}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C9}\left(t\right)dt={\displaystyle \frac{2I_o}{C_9{f}_s}}\hfill \\ \Delta V_{C10}={\displaystyle \frac{1}{C_{10}}}{\int }_0^{D{T}_s}{i}_{C10}\left(t\right)dt={\displaystyle \frac{1}{C_{10}}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C10}\left(t\right)dt={\displaystyle \frac{I_o}{C_{10}{f}_s}}\hfill \\ \Delta V_{C11}={\displaystyle \frac{1}{C_{11}}}{\int }_0^{D{T}_s}{i}_{C11}\left(t\right)dt={\displaystyle \frac{1}{C_{11}}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{C11}\left(t\right)dt={\displaystyle \frac{I_o}{C_{11}{f}_s}}\hfill \\ \Delta V_o={\displaystyle \frac{1}{C_o}}{\int }_0^{D{T}_s}{i}_{Co}\left(t\right)dt={\displaystyle \frac{1}{C_o}}{\int }_0^{{\displaystyle \frac{D}{f_s}}}{i}_{Co}\left(t\right)dt={\displaystyle \frac{(1+D)I_o}{C_o{f}_s}}\hfill \end{array}\right.$$

(8)

The converter’s operation in the continuous conduction mode (CCM) stands for the inductors’ current ripple and inductors’ average current. The inductors’ current ripple has a reversed relation with inductance. Notably, the inductors’ current ripple must be more than twice the corresponding inductor average current to provide the CCM. According to this concept, the inductors’ minimum value is as follows:

$$L_1\ge {\displaystyle \frac{D{(1-D)}^{4}R}{1296f_S}},L_2\ge {\displaystyle \frac{D{(1-D)}^{4}R}{1296f_S}},L_3\ge {\displaystyle \frac{D{(1-D)}^{2}R}{36f_S}},L_4\ge {\displaystyle \frac{D{(1-D)}^{2}R}{36f_S}}$$

(9)

The inductors’ average current is the second factor of the converters operating in CCM.The inductors’ average current must be more than half of the corresponding inductor’s current ripple. The inductors’ average current depends on the output average current and duty cycle. Figure 6 presents the operational region of the converter among CCM, DCM, and boundary conditions according to the output average current and duty cycle for a constant output voltage and a constant input voltage. The employed relations for the mentioned figure are as follows:

$$\left\{\begin{array}{c}{I}_{OB}={\displaystyle \frac{V_O}{36L_4{f}_s}}D{(1-D)}^2\hfill \\ I_{OB}={\displaystyle \frac{V_{in}}{L_4{f}_s}}D\hfill \end{array}\right.$$

(10)

Any point up the mentioned curves in Figure 6 belongs to CCM. Additionally, any point under the mentioned curves is for DCM. Finally, any point on the curve is the boundary condition.

3. Non-Ideal Voltage Gain and Efficiency

The extracted relation of the voltage gain in the second section is for the ideal mode, where the equivalent series resistance of the inductor ($r_L$), switch ($r_S$), diode ($r_D$), and load (R) are absent. Considering the mentioned parameters, the voltage gain of the boost converter is as follows in the non-ideal mode.

$${\displaystyle \frac{v_o}{V_{in}}}={\displaystyle \frac{1}{(1-D)}}\left(1-{\displaystyle \frac{r_L}{R}}\left({\displaystyle \frac{1}{{(1-D)}^2}}\right)-{\displaystyle \frac{r_S}{R}}\left({\displaystyle \frac{D}{{(1-D)}^2}}\right)-{\displaystyle \frac{r_D}{R}}\left({\displaystyle \frac{1}{(1-D)}}\right)\right)$$

(11)

For the cascaded boost topology, we have

$${\displaystyle \frac{v_o}{V_{in}}}={\displaystyle \frac{1}{{(1-D)}^2}}\left(1-{\displaystyle \frac{r_L}{R}}\left({\displaystyle \frac{1}{{(1-D)}^4}}\right)-{\displaystyle \frac{r_S}{R}}\left({\displaystyle \frac{D}{{(1-D)}^4}}\right)-{\displaystyle \frac{r_D}{R}}\left({\displaystyle \frac{1}{{(1-D)}^3}}\right)\right)$$

(12)

Applying the effect of the voltage multiplier cells to the relation, the non-ideal voltage gain relation of the proposed topology becomes as follows:

$${\displaystyle \frac{v_o}{V_{in}}}={\displaystyle \frac{36}{{(1-D)}^2}}\left(1-{\displaystyle \frac{r_L}{R}}\left({\displaystyle \frac{36}{{(1-D)}^4}}\right)-{\displaystyle \frac{r_S}{R}}\left({\displaystyle \frac{36D}{{(1-D)}^4}}\right)-{\displaystyle \frac{r_D}{R}}\left({\displaystyle \frac{36}{{(1-D)}^3}}\right)\right)$$

(13)

According to the extracted relation, the voltage gain depends on the duty cycle, load, and component quality, which stands for $r_L$, $r_S$, and $r_D$. Figure 7 compares the ideal voltage gain (expressed in the second section) with the non-ideal voltage gain (expressed in this section). It can be understood that the non-ideal voltage gain is not compatible with the ideal voltage gain in all duty cycle values. The interval of their compatibility depends on the output power and component quality. Figure 8 presents the non-ideal voltage gain behavior according to the output power and component quality changes. Changing the output power has the highest impact, and changing the diode quality has the lowest impact.

The converter’s input power and output power are equal in the ideal mode. However, this equality is not valid in the non-ideal mode. Considering the components’ conduction loss, the efficiency becomes accessible.

$$\left\{\begin{array}{c}{P}_L=\sum _{n=1}^4{r}_{Li}{i}_{Li}^2\hfill \\ P_{SC}=r_S{i}_S^2\hfill \\ P_D=\sum _{n=1}^{15}{V}_{DFi}{i}_{Di}^2\hfill \\ \eta ={\displaystyle \frac{P_o}{P_o+P_L+P_{SC}+P_D}}\hfill \end{array}\right.$$

(14)

Notably, the frequency loss of the semiconductors is ignored. In other words, they have negligible values. For example, for IRF450, which is used in the prototype, the frequency loss is approximately 0.01 W. Notably, the switch of the converter has the highest voltage and current stresses among the employed semiconductors of this topology. The loss of capacitors is ignored due to the use of MKT capacitors. This kind of capacitor has a negligible equivalent series resistor (0.001 Ω).

According to this equation, the efficiency depends on the duty cycle, output power, and component quality. Figure 9 presents the efficiency behavior of the topology according to the output power and component quality changes. According to the illustrated figure, the output power strongly influences efficiency behavior. After this, the switch type has the highest influence on the efficiency of component quality.

It is good to note that such high-gain proposed topologies with an ultra-high voltage gain can be discussed from various aspects, like in [155,156], to determine the various features with detailed simulations. Our research team will consider this for future research purposes.

4. Voltage Gain and Voltage Gain Density Comparison of the Proposed Topology with Other High-Gain Topologies

One of the prominent points of the proposed topology is its voltage gain. Figure 10 compares the voltage gains. According to this figure, the proposed topology’s provided voltage gain is higher than that of [10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60]. Notably, the proposed topology’s provided voltage gain at low-duty cycles is higher than that of [10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60]. At higher-duty cycles. In comparing different components, let us consider the number of inductors, capacitors, switches, diodes, and overall components.

Table 1. Components numbers.

Topology	L	C	S	D	All
[10]	2	3	2	2	8
[11]	2	2	2	2	8
[12]	3	3	1	3	10
[13]	2	2	1	3	8
[14]	3	4	1	2	10
[15]	2	2	2	2	8
[16]	2	2	2	2	8
[17]	2	2	1	3	8
[18]	3	4	2	3	12
[19]	2	2	2	2	8
[20]	2	2	2	2	8
[21]	3	3	2	2	10
[22]	2	3	2	3	10
[23]	2	2	2	2	8
[24]	2	3	2	3	10
[25]	2	2	2	2	8
[26]	3	3	1	5	12
[27]	3	3	1	3	10
[28]	3	3	2	2	10
[29]	3	3	2	2	10
[30]	2	2	2	2	8
[31]	2	2	2	2	8
[32]	2	2	2	2	8
[33]	3	3	2	2	10
[34]	2	2	2	2	8
[35]	3	3	2	2	10
[36]	2	2	2	2	8
[37]	3	3	2	2	10
[38]	2	2	2	2	8
[39]	3	3	2	2	10
Proposed	4	12	1	15	32

and

Table 2. Components number.

	L	C	S	D	All
[41]	2	4	1	5	12
[42]	3	4	1	4	12
[43]	1	3	1	3	8
[44]	5	3	1	9	18
[45]	5	5	1	7	18
[46]	2	3	2	3	10
[47]	2	3	2	3	10
[48]	3	4	2	3	12
[49]	3	6	1	3	13
[40]	3	4	1	2	10
[50]	2	3	1	4	10
[51]	3	4	1	6	14
[52]	3	5	1	6	15
[53]	2	3	2	3	10
[54]	3	4	1	5	13
[55]	3	3	1	5	12
[56]	3	4	1	6	14
[57]	3	3	1	5	12
[58]	3	3	1	5	12
[59]	2	4	1	3	10
[60]	3	3	1	5	12
proposed	4	12	1	15	32

showcase these numbers. The proposed topology has more capacitors, diodes, and overall components than the other topologies. In terms of switch number, the proposed and most other converters have the same number of switches. However, the lower component count results in a lower voltage gain, which is consistent with references [10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39]. The design of the proposed topology is further analyzed by discussing the voltage gain density over the number of components. Figure 11 illustrates the voltage gain density over the components at all duty cycles. It shows that the proposed topology has a higher gain density. Additionally, Figure 12, Figure 13, Figure 14 and Figure 15 present the voltage gain density over each type of component. According to these figures, the proposed topology has the highest voltage gain density in terms of inductors, capacitors, switches, and diodes. These results highlight that the superior voltage gain is not solely due to the number of components but also signifies a better design compared to other topologies. To better understand the superiority of the proposed topology in terms of voltage gain density, the value of this parameter is extracted per type of component number. The voltage gain of converters is calculated at a 50% duty cycle, where the energy-storing and -releasing times are the same.

Table 3. Voltage gain density over the inductors number.

Topology	${\displaystyle \frac{\mathit{G}}{\mathit{L}}}$	${\displaystyle \frac{\mathit{G}}{\mathit{C}}}$	${\displaystyle \frac{\mathit{G}}{\mathit{S}}}$	${\displaystyle \frac{\mathit{G}}{\mathit{D}}}$	${\displaystyle \frac{\mathit{G}}{\mathit{A}}}$
[10]	0.5	0.5	0.5	0.5	0.125
[11]	1.5	1.5	1.5	1.5	0.375
[12]	0.66	0.66	2	0.66	0.2
[13]	2	2	4	1.33	0.5
[14]	0.66	0.5	2	1	0.2
[15]	1	1	1	1	0.25
[16]	2	2	2	2	0.5
[17]	1.5	1.5	1.5	1.5	0.375
[18]	1	0.75	1.5	1	0.25
[19]	0.5	0.5	0.5	0.5	0.125
[20]	0.5	0.5	0.5	0.5	0.125
[21]	0.33	0.33	0.5	0.5	0.1
[22]	2	1.3	2	1.3	0.4
[23]	0.5	0.5	0.5	0.5	0.125
[24]	3	2	3	2	0.5
[25]	2	2	2	2	0.5
[26]	0.33	2	2	2	0.5
[27]	0.66	0.66	1	1	0.2
[28]	0.33	2	2	2	0.5
[29]	0.33	0.33	0.5	0.5	0.1
[30]	2	2	2	2	0.5
[31]	2	2	2	2	0.5
[32]	2	2	2	2	0.5
[33]	1	1	1.5	1.5	0.3
[34]	1.5	1.5	1.5	1.5	0.375
[35]	0.67	0.67	1	1	0.2
[36]	2	2	2	2	0.5
[37]	0.66	0.66	1	1	0.2
[38]	2	2	2	2	0.5
[39]	0.33	0.33	0.5	0.5	0.1
[41]	4	2	8	1.6	0.75
[42]	1.66	1.25	5	1.25	0.42
[43]	4	1.3	4	1.3	0.5
[44]	0.9	1.5	4.5	0.5	0.25
[45]	1.6	1.6	8	1.14	0.44
[46]	3.5	2.33	3.5	2.33	0.7
[47]	3.5	2.33	3.5	2.33	0.7
[48]	1.66	1.25	2.5	1.66	0.42
[49]	1	0.5	3	1	0.23
[40]	0.66	0.5	2	1	0.2
[50]	3	2	6	1.5	0.6
[51]	4	3	12	2	0.85
[52]	3.33	2	10	1.66	0.66
[53]	3	2	3	2	0.6
[54]	3	2.25	9	1.8	0.69
[55]	2.66	2.66	8	1.6	0.75
[56]	3.33	2.5	10	1.66	0.69
[5]	1.33	1.33	4	0.8	0.33
[58]	2.33	2.33	7	1	0.5
[59]	2	1	4	1.33	0.4
[60]	3.33	3.33	10	2	0.83
Proposed	36	12	144	9.6	4.5

displays the voltage gain density over the number of inductors, capacitors, switches, diodes, and overall components. It becomes evident that the proposed topology has the highest voltage gain density, justifying the number of components employed in it.

5. Application of the Proposed Topology

High-step-up DC–DC converters are used in various applications, as shown in Figure 16. A number of dielectric test procedures require a high DC voltage. Using a non-isolated high-gain DC–DC converter to supply this voltage reduces the size and weight of the testing equipment. One common application of this setup is measuring the dielectric resistance of equipment, which necessitates both a high DC voltage and a pico ammeter. Additionally, when the output voltage ripple is low enough, measuring a dielectric’s polarization and depolarization currents (PDC) becomes possible. This capability is valuable for monitoring the condition of high-voltage equipment. Another application of these converters is the electrolysis of water to produce hydrogen as a clean energy resource. The low DC voltage provided by renewable energy sources can be used as the input source of a high-gain DC–DC converter. The high voltage offered at the output of the DC–DC converter can be applied to a pulse power converter for the electrolysis of water to produce hydrogen.

6. Experimental Results

The experimental results are discussed in this section to validate the extracted theoretical relations. The prototype of the converter is accessible by defining the voltage/current characteristics of the circuit components. In other words, the inductors’ average current, capacitors’ average voltage, and semiconductors’ voltage/current stresses must be determined. All these voltage variables are a function of the duty cycle, and input voltage and current variables are a function of the output current and duty cycle. Considering the safety considerations and measurement equipment limits, the input voltage, output current, and duty cycle are as follows:

$$\left\{\begin{array}{c}{V}_{in}=10\mathrm{V}\hfill \\ I_o=55\mathrm{mA}\hfill \\ D=50\%\hfill \end{array}\right.$$

(15)

The input voltage and output current have been considered according to safety considerations, components, and measurement equipment limits. The mentioned duty cycle leads to equal energy storage and release times. According to the expressed values and reported relations in the second section, the inductors’ average current, capacitors’ average voltage, and semiconductors’ voltage/current stresses are as follows:

$$\left\{\begin{array}{c}{I}_{L1}=I_{L2}={\displaystyle \frac{18}{{(1-D)}^2}}{I}_o=4\mathrm{A}\hfill \\ I_{L3}=I_{L4}={\displaystyle \frac{3}{1-D}}{I}_o=0.33\mathrm{A}\hfill \end{array}\right.$$

(16)

$$\left\{\begin{array}{c}{V}_{C1}=V_{in}=10\mathrm{V}\hfill \\ V_{C2}=V_{C3}={\displaystyle \frac{2}{1-D}}{V}_{in}=40\mathrm{V}\hfill \\ V_{C4}=V_{C5}={\displaystyle \frac{2}{1-D}}{V}_{in}=40\mathrm{V}\hfill \\ V_{C6}=V_{C7}={\displaystyle \frac{6}{1-D}}{V}_{in}=120\mathrm{V}\hfill \\ V_{C8}=V_{C9}={\displaystyle \frac{12}{{(1-D)}^2}}{V}_{in}=480\mathrm{V}\hfill \\ V_{C10}=V_{C11}={\displaystyle \frac{12}{{(1-D)}^2}}{V}_{in}=480\mathrm{V}\hfill \\ V_o={\left({\displaystyle \frac{6}{1-D}}\right)}^2{V}_{in}=1440\mathrm{V}\hfill \end{array}\right.$$

(17)

$$\left\{\begin{array}{c}{I}_S={\displaystyle \frac{35+2D-D^2}{{(1-D)}^2}}{I}_o=7.9\mathrm{A}\hfill \\ I_{D1}=I_{D2}={\displaystyle \frac{18}{{(1-D)}^2}}{I}_o=4\mathrm{A}\hfill \\ I_{D3}=I_{D4}={\displaystyle \frac{6}{1-D}}{I}_o=0.66\mathrm{A}\hfill \\ I_{D5}=I_{D6}=I_{D7}={\displaystyle \frac{6}{1-D}}{I}_o=0.66\mathrm{A}\hfill \\ I_{D8}=I_{D9}={\displaystyle \frac{3}{1-D}}{I}_o=0.33\mathrm{A}\hfill \\ I_{D10}={\displaystyle \frac{5+D}{1-D}}{I}_o=0.61\mathrm{A}\hfill \\ I_{D11}=I_{D12}=I_{D13}=I_o=0.055\mathrm{A}\hfill \\ I_{D14}=I_{D15}=I_o=0.055\mathrm{A}\hfill \end{array}\right.$$

(18)

$$\left\{\begin{array}{c}{V}_{D1}=V_{D2}={\displaystyle \frac{V_{in}}{1-D}}=20\mathrm{V}\hfill \\ V_{D3}=V_{D4}={\displaystyle \frac{2}{1-D}}{V}_{in}=40\mathrm{V}\hfill \\ V_{D5}=V_{D6}=V_{D7}={\displaystyle \frac{2}{1-D}}{V}_{in}=40\mathrm{V}\hfill \\ V_{D8}=V_{D9}={\displaystyle \frac{6}{{(1-D)}^2}}{V}_{in}=240\mathrm{V}\hfill \\ V_S=V_{D11}={\displaystyle \frac{12}{{(1-D)}^2}}{V}_{in}=480\mathrm{V}\hfill \\ V_{D12}=V_{D13}={\displaystyle \frac{12}{{(1-D)}^2}}{V}_{in}=480\mathrm{V}\hfill \\ V_{D14}=V_{D15}={\displaystyle \frac{12}{{(1-D)}^2}}{V}_{in}=480\mathrm{V}\hfill \end{array}\right.$$

(19)

To determine the inductors’ and capacitors’ values, the inductors’ current ripple, capacitors’ voltage ripple, and switching frequency are as follows:

$$\left\{\begin{array}{c}\Delta i_L=30\%\hfill \\ \Delta v_c=5\%\hfill \\ f_s=50\mathrm{kHz}\hfill \end{array}\right.$$

(20)

According to the power quality standards, the voltage ripple must be between 1% and 10%, and the current ripple must be between 20% and 40%. In this study, the average value of the lower and upper margins was used. According to the mentioned values, the inductors’ and capacitors’ values are as follows:

$$\left\{\begin{array}{c}\Delta i_{L1}={\displaystyle \frac{D{V}_{in}}{L_1{f}_s}}\Rightarrow 83\mathsf{\mu }\mathrm{H}\hfill \\ \Delta i_{L2}={\displaystyle \frac{D{V}_{in}}{L_2{f}_s}}\Rightarrow 83\mathsf{\mu }\mathrm{H}\hfill \\ \Delta i_{L3}={\displaystyle \frac{6D{V}_{in}}{(1-D)L_3{f}_s}}\Rightarrow 12\mathrm{mH}\hfill \\ \Delta i_{L4}={\displaystyle \frac{6D{V}_{in}}{(1-D)L_4{f}_s}}\Rightarrow 12\mathrm{mH}\hfill \end{array}\right.$$

(21)

$$\left\{\begin{array}{c}\Delta V_{C1}={\displaystyle \frac{18I_o}{(1-D)C_1{f}_s}}\Rightarrow 80\mathsf{\mu }\mathrm{F}\hfill \\ \Delta V_{C2}={\displaystyle \frac{6I_o}{(1-D)C_2{f}_s}}\Rightarrow 6.6\mathsf{\mu }\mathrm{F}\hfill \\ \Delta V_{C3}={\displaystyle \frac{12I_o}{(1-D)C_3{f}_s}}\Rightarrow 13\mathsf{\mu }\mathrm{F}\hfill \\ \Delta V_{C4}={\displaystyle \frac{6I_o}{(1-D)C_4{f}_s}}\Rightarrow 6.6\mathsf{\mu }\mathrm{F}\hfill \\ \Delta V_{C5}={\displaystyle \frac{6I_o}{(1-D)C_5{f}_s}}\Rightarrow 6.6\mathsf{\mu }\mathrm{F}\hfill \\ \Delta V_{C6}={\displaystyle \frac{3(3+D)I_o}{(1-D)C_6{f}_s}}\Rightarrow 3.8\mathsf{\mu }\mathrm{F}\hfill \\ \Delta V_{C7}={\displaystyle \frac{3I_o}{C_7{f}_s}}\Rightarrow 550\mathrm{nF}\hfill \\ \Delta V_{C8}={\displaystyle \frac{I_o}{C_8{f}_s}}\Rightarrow 46\mathrm{nF}\hfill \\ \Delta V_{C9}={\displaystyle \frac{2I_o}{C_9{f}_s}}\Rightarrow 96\mathrm{nF}\hfill \\ \Delta V_{C10}={\displaystyle \frac{I_o}{C_{10}{f}_s}}\Rightarrow 46\mathrm{nF}\hfill \\ \Delta V_{C11}={\displaystyle \frac{I_o}{C_{11}{f}_s}}\Rightarrow 96\mathrm{nF}\hfill \\ \Delta V_o={\displaystyle \frac{(1+D)I_o}{C_o{f}_s}}\Rightarrow 69\mathrm{nF}\hfill \end{array}\right.$$

(22)

The calculated values are minimum values, and higher values for capacitors can be used spatially. According to the expressed values, the component types are reported in

Table 4. Components type.

Inductor	Capacitor	Diode	Switch
EC type	MKT	DTV56F	IRF450

. According to the mentioned types, the prototype is presented in Figure 17. Additionally, the experimental results are presented in Figure 18. In this figure, the current waveforms of the inductors, the voltage waveforms of the capacitors, and voltage/current waveforms of the semiconductors are the extracted experimental results.

According to the experimental results in Figure 18, the inductors’ average current, capacitors’ average voltage, semiconductors’ average current, and semiconductors’ peak voltage are as follows:

$$\left\{\begin{array}{c}{I}_{L1}=3.7\mathrm{A}\hfill \\ I_{L2}=3.7\mathrm{A}\hfill \\ I_{L3}=0.31\mathrm{A}\hfill \\ I_{L4}=0.31\mathrm{A}\hfill \end{array}\right.$$

(23)

$$\left\{\begin{array}{c}{V}_{C1}=9.7\mathrm{V}\hfill \\ V_{C2}=39.5\mathrm{V}\hfill \\ V_{C3}=38.7\mathrm{V}\hfill \\ V_{C4}=36.5\mathrm{V}\hfill \\ V_{C5}=36.5\mathrm{V}\hfill \\ V_{C6}=112.2\mathrm{V}\hfill \\ V_{C7}=112\mathrm{V}\hfill \\ V_{C8}=450\mathrm{V}\hfill \\ V_{C9}=450\mathrm{V}\hfill \\ V_{C10}=448.5\mathrm{V}\hfill \\ V_{C11}=448.4\mathrm{V}\hfill \\ V_o=1360\mathrm{V}\hfill \end{array}\right.$$

(24)

$$\left\{\begin{array}{c}{I}_S=7.1\mathrm{A}\hfill \\ I_{D1}=I_{D2}=3.7\mathrm{A}\hfill \\ I_{D3}=I_{D4}=0.62\mathrm{A}\hfill \\ I_{D5}=I_{D6}=I_{D7}=0.62\mathrm{A}\hfill \\ I_{D8}=I_{D9}=0.3\mathrm{A}\hfill \\ I_{D10}=0.59\mathrm{A}\hfill \\ I_{D11}=I_{D12}=I_{D13}=0.051\mathrm{A}\hfill \\ I_{D14}=I_{D15}=0.051\mathrm{A}\hfill \end{array}\right.$$

(25)

$$\left\{\begin{array}{c}{V}_{D1}=V_{D2}=19\mathrm{V}\hfill \\ V_{D3}=V_{D4}=38\mathrm{V}\hfill \\ V_{D5}=V_{D6}=38\mathrm{V}\hfill \\ V_{D8}=V_{D9}=225\mathrm{V}\hfill \\ V_S=V_{D11}=450\mathrm{V}\hfill \\ V_{D12}=V_{D13}=450\mathrm{V}\hfill \\ V_{D14}=V_{D15}=450\mathrm{V}\hfill \end{array}\right.$$

(26)

It can be understood that the extracted values are compatible with the design considerations, and the differences are in the parasitic components of the circuit elements. The efficiency of the converter according to the extracted data is illustrated in Figure 19 as a pie chart. It is worth noting that the mentioned application for the proposed topology does not need high-efficiency values. Additionally, the current values are less than the considered value in the experimental results. Consequently, the conduction losses are not a dramatic issue in this study. Notably, the efficiency of the proposed converter is extracted for a varying output voltage and constant output power besides a constant output voltage and varying output power. Both conditions show an acceptable value of efficiency in Figure 20. To provide higher output voltages, two proposed topologies can be used in a stacked form, as in Figure 21. In this condition, the input sources must be isolated from each other, and the switch of the second converter must be derived as a high-sided switch. The extracted output voltages are presented in Figure 22. According to this figure, a 2680 V is provided with such a structure. Consequently, a much higher value than this, which is used in very-high-voltage DC tests of dielectrics, can be achieved by increasing the number of stacked levels.

7. Conclusions

An ultra-high step-up DC–DC converter is proposed. A high voltage gain was provided without a high-frequency transformer and a high-duty cycle. Moreover, the semiconductors’ voltage stress was less than the output voltage. A high voltage gain density was also extracted from the proposed topology, which justified the number of components and the voltage gain value. Such a high voltage density was extracted according to all types of components. The current stress of the semiconductors was low and acceptable, making the design of such a converter easier. Furthermore, the provided voltage gain by the proposed topology is high enough that the stacked connection of two converters from this type can easily achieve a 2.6 kV without using transformers. All these points make the proposed topology suitable for dielectric test applications.