A Novel Single-Stage Boost Single-Phase Inverter and Its Composite Control Strategy to Suppress Low-Frequency Input Ripples

Abstract

Low-frequency pulsating ripples exist on the input side of a single-phase inverter, which bring some adverse effects and harm to the inverter and photovoltaic power generation system. In order to suppress the low-frequency pulsating ripple and reduce the filter circuit parameters, a novel single-stage boost single-phase inverter is proposed, which can suppress low-frequency ripple. And a three-closed-loop compound control strategy that can suppress input low-frequency ripples under the limitation of an energy storage inductor current and buffer capacitor voltage is proposed. The circuit topology, control strategy, key circuit parameters design, system modeling, and simulation of the inverters are deeply analyzed and studied. Simulation and experimental results show that the inverter has a good ability to suppress input low-frequency ripples.

1. Introduction

With the development of the global economy, the problem of energy crisis and environmental deterioration has become increasingly serious, and the new energy power generation system represented by fuel cells and photovoltaics has attracted more and more attention [1,2,3,4]. The output of photovoltaic cells and fuel cells are DC, and the voltage is low, the fluctuation range is large, and it is difficult to directly use; the booster inverter needs to convert DC power into AC power and transmit it to the grid or for loading. The single-phase inverter produces input current low-frequency ripples on the DC input side during normal operation, which affect the performance of the converter and cause some adverse harm and influence [5,6,7]. For example, in the application of fuel cell inverters, the input current low-frequency ripple increases the loss of the battery and reduces the efficiency and performance of the system [8]. When the photovoltaic is inverted, the low-frequency current ripple on the input side affects the MPPT of the photovoltaic cell and decreases the efficiency and energy utilization of the photovoltaic generation system [9,10,11,12,13,14]. The low-frequency ripple also has a certain impact on the power battery of electric vehicles [15]. The method of filtering out the low-frequency ripple on the input side is usually to use a larger filter on the DC side of the inverter, but this leads to the large volume, weight, and cost of the system, and the large electrolytic capacitor life is short, which affects the long-term reliable operation of the system. In addition, the electrified railway, which has developed rapidly in recent years as a single-phase rectifier or inverter load electric locomotive, injects large and fluctuating low-frequency current ripples and negative-sequence currents into the power system through the traction power supply system, which affects the power quality of the system. Therefore, it is also necessary to consider ripple suppression and the elimination of negative-sequence components to solve power quality problems [16,17,18]. In order to adapt to the application of low input voltage, such as new energy power generation, it is necessary to seek a single-stage boost single-phase inverter that can suppress the low-frequency ripple on the DC side.

In order to better suppress the secondary current ripple at the input side of the single-phase inverter, researchers have put forward many solutions. Generally, they can be divided into two categories: the first is the two-stage inverter circuit topology and its optimal control strategy; the second category is the single-stage inverter circuit topology and its control strategy. Based on the traditional two-stage inverter circuit topology, Refs. [19] and [20] proposed an inductor current feedback control strategy that could introduce low-frequency pulsating power into the DC bus capacitor, which realized the suppression of the input current secondary ripple, though the DC bus capacitor was large. In [21], an active LC decoupling circuit was connected to the AC side of the traditional two-stage inverter, and the low-frequency pulsating power was transferred to the decoupling circuit to suppress the secondary ripple of input current. However, more power switches were introduced, and the decoupling circuit was slightly complicated. A single-phase current source boost inverter with active filter was proposed in [22] and adds some effective circuit modes. By flexibly controlling these circuit modes, the low-frequency pulsating power can be transferred to the active filter to suppress the secondary ripple of the input current. A single-phase Buck-Boost inverter with source decoupling circuit was proposed in [23], where the low-frequency ripple of the input current was suppressed by the thin-film decoupling capacitor to absorb the low-frequency pulsation power. However, limited by the working principle of the circuit, the duty cycle adjustment range was narrow. A single-stage battery integrated inverter was proposed in [24], and a thin film capacitor was used to replace the electrolytic capacitor for the mismatch between input and output power, but the inverter used a large number of energy storage components. Ref. [25] proposed a single-phase current source inverter, which used a switching cell (SC) structure to reduce the overlap time. At the same time, when the main circuit switches were all disconnected, the SC provided the current path for the input inductor and compensated the ripple power through the decoupling circuit. Ref. [26] proposed a multi-proportional resonant closed-loop decoupling method to suppress the voltage ripple of the DC bus and analyzed the ripple component of the capacitor voltage by solving differential equations. Ref. [27] introduced single-phase converter topologies with secondary ripple suppression and classified and compared different power-decoupling topologies.

Based on the research of the above-related papers, this paper proposes a novel single-stage boost single-phase inverter that can suppress low-frequency ripple and analyzes the circuit topology, circuit mode, and working mode of the inverter, putting forward the suppression strategy of the inverter input low-frequency ripple, and conducting the physical modeling of the circuit. And through simulation and prototype experiments, the proposed inverter and control strategy are verified.

2. Circuit Topology and Circuit Mode

2.1. Circuit Topology

The single-stage boost single-phase inverter that can suppress low-frequency ripple proposed in this paper is shown in Figure 1.

The boost inverter and low-frequency ripple suppression function of the circuit are mainly realized by the energy storage inductor, the active buffer circuit, and the single-phase current inverter bridge. The active buffer circuit controls the charge and discharge state of the buffer capacitor C_b through the switches S₆ and S₅, which can realize the transfer of the low-frequency pulsating power on the load side with the purpose of suppressing the low-frequency ripple of the input current. The buffer circuit also provides a current path for the energy storage inductor when the drive is missing, which realizes the compatibility of the current source inverter with the unexpected overlap and dead zone of the inverter bridge and improves the reliability of the converter. In addition, in order to reliably realize the boost inverter, make the inverter adapt to capacitive and inductive loads, and meet the control of the charge and discharge of the buffer capacitor in the energy feedback stage, the inverter’s energy storage inductor current and buffer capacitor voltage must meet certain conditions.

2.2. Circuit Mode

The proposed inverter has four circuit modes in one power frequency cycle, respectively: (1) The magnetizing mode: S₁, S₃ (or S₂, S₄) conduct, U_i magnetizes L works through the left bridge arm (or the right bridge arm), and, at the same time, the output filter C_f supplies power to the load Z_L. (2) The energy-feeding mode: S₁, S₄ (or S₂, S₃) conduct, and U_i outputs a positive (or negative) modulation current i_m through L and S₁, S₄ (or S₂, S₃) to supply power to C_f and Z_L, respectively. (3) The buffer capacitor charging mode: S₁-S₆ cut off, D₅, D₆ represent natural conduction, and L works through D₅, D₆ to C_b charging while C_f supplies power to Z_L. (4) Buffer capacitor discharging mode: S₅, S₆ are connected, C_b magnetizes L through S₅, S₆, and C_f supplies power to Z_L.

3. Control Strategy

3.1. Output Voltage Feedback SPWM Control Strategy and Its Working Mode Design

According to the different circuit mode combinations of each switching cycle T_s, the proposed inverter can be designed into three working modes: the magnetizing working mode composed of the (1 – d)T_s magnetizing mode and dT_s energy-feeding mode. The charging working mode is composed of the (1 – d)T_s buffer capacitor charging mode and dT_s energy-feeding mode. The discharge working mode is composed of the (1 – d)T_s buffer capacitor discharge mode and dT_s energy feed mode. Taking the resistive load as an example, when the inverter works in the magnetizing mode of three working modes, the power flow flows from the input source to the inductor and load. In the charging mode, the power flow flows from the input source and the inductor to the buffer capacitor and the load. In the discharge mode, the power flow flows from the input source and the buffer capacitor to the inductor and the load.

Based on these three working modes, the proposed inverter can adopt the output voltage feedback SPWM control strategy with a t energy storage inductor current limit and buffer capacitor voltage limit, and the driving logic is shown in

Table 1. Output voltage feedback drive logic signal under SPWM control.

Circuit Status	High-Frequency-Switching Interval	S1	S2	S3	S4	S5	S6
uo > 0, iL < IL*, ucb < Ucb*	(1 – d)TS	1	0	1	0	0	0
	dTS	1	0	0	1	0	0
uo > 0, iL < IL*, ucb > Ucb*	(1 – d)TS	0	0	0	0	1	1
	dTS	1	0	0	1	0	0
uo > 0, iL > IL*	(1 – d)TS	0	0	0	0	0	0
	dTS	1	0	0	1	0	0
uo < 0, iL < IL*, ucb < Ucb*	(1 – d)TS	1	0	1	0	0	0
	dTS	0	1	1	0	0	0
uo < 0, iL < IL*, ucb > Ucb*	(1 – d)TS	0	0	0	0	1	1
	dTS	0	1	1	0	0	0
uo < 0, iL > IL*	(1 – d)TS	0	0	0	0	0	0
	dTS	0	1	1	0	0	0

. Let I_L* be the current limit value of the energy storage inductor and U_cb* be the voltage limit value of the buffer capacitor. When u_cb < U_cb* and i_L < I_L*, the inverter works in the magnetizing working mode. When u_cb > U_cb* and i_L < I_L*, the inverter works in discharging working mode. When i_L > I_L*, the inverter works in the charging working mode. Under the premise of ensuring that the inverter bridge outputs the appropriate modulation current, the control strategy preferentially limits i_L near I_L* in order to ensure the continuity of the inductor current i_L. At the same time, by limiting the buffer capacitor voltage near U_cb*, the energy buffer of the buck stage and the load energy feedback stage of the converter is realized.

3.2. Ideas for Suppressing Low-Frequency Ripple of Input Current

The output voltage, current, and power of the single-phase inverter are as follows:

$$u_{\mathrm{o}}(t)=\sqrt{2}{U}_{\mathrm{o}}\sin (\omega t)$$

(1)

$$i_{\mathrm{o}}(t)=\sqrt{2}{I}_{\mathrm{o}}\sin (\omega t-\phi )$$

(2)

$$p_{\mathrm{o}}(t)=u_{\mathrm{o}}(t)i_{\mathrm{o}}(t)=U_{\mathrm{o}}{I}_{\mathrm{o}}\cos \phi -U_{\mathrm{o}}{I}_{\mathrm{o}}\cos (2\omega t-\phi )$$

(3)

Ignore the power loss of the inverter, which, according to the principle of power conservation, can be obtained as follows:

$$p_{\mathrm{in}}(t)=p_{\mathrm{o}}(t)=U_{\mathrm{o}}{I}_{\mathrm{o}}\cos \phi -U_{\mathrm{o}}{I}_{\mathrm{o}}\cos (2\omega t-\phi )$$

(4)

As can be seen from (4), the input power consists of a DC component and a low-frequency AC component with double-frequency pulsation. Since the input voltage is constant, the low-frequency AC component is reflected as the input current pulsation component. The corresponding input current is as follows:

$$i_{\mathrm{in}}(t)={\displaystyle \frac{U_{\mathrm{o}}{I}_{\mathrm{o}}\cos \phi }{U_{\mathrm{in}}}}-{\displaystyle \frac{U_{\mathrm{o}}{I}_{\mathrm{o}}}{U_{\mathrm{in}}}}\cos (2\omega t-\phi )$$

(5)

If this part of energy can be transferred to the buffer capacitor through appropriate circuit control, the AC and DC power decoupling of the inverter can be achieved as follows:

$$p_{\mathrm{o}}(t)=p_{\mathrm{in}}(t)+p_{\mathrm{c}}(t)=U_{\mathrm{o}}{I}_{\mathrm{o}}\cos \phi -U_{\mathrm{o}}{I}_{\mathrm{o}}\cos (2\omega t-\phi )$$

(6)

$$p_{\mathrm{in}}(t)=U_{\mathrm{in}}{I}_{\mathrm{in}}=U_{\mathrm{o}}{I}_{\mathrm{o}}\cos \phi$$

(7)

$$p_{\mathrm{c}}(t)=u_{\mathrm{c}}(t)i_{\mathrm{c}}(t)=u_{\mathrm{c}}(t)C_{\mathrm{b}}{\displaystyle \frac{d{u}_{\mathrm{c}}(t)}{dt}}=U_{\mathrm{o}}{I}_{\mathrm{o}}\cos (2\omega t-\phi )$$

(8)

When p_o is ensured as (3), it can be seen from (6) that if p_in satisfies (7), then p_c satisfies (8). Similarly, if p_c satisfies (8), then p_in satisfies (7). Therefore, the low-frequency ripple of the input current can be suppressed by controlling p_in or p_c. Considering that the control target of the input current only contains DC and high-frequency switching components, according to the principle of impulse equivalence, it is easier to control the input current directly using PWM, so the scheme of direct control p_in can be considered. The voltage feedback SPWM control based on three working modes is limited by the modulation mode, which cannot take into account the transfer of low-frequency pulsating power on the load side by the active buffer circuit, and it is difficult to suppress the low-frequency ripple of the input current. Therefore, in order to stabilize the output AC voltage and input DC pulse current of the inverter, a two-objective, three-closed-loop composite control strategy is proposed in this paper.

3.3. Two-Objective Three-Closed-Loop Composite Control Strategy and Its Working Mode Design

The input current I_i of the proposed inverter is the pulse current. In order to ensure that the average value of I_i in each T_s is constant, each T_s needs to contain an energy-feeding circuit mode, magnetizing the circuit mode of L (I_i = i_L), and charging or discharging the circuit mode of C_b (I_i = 0). Set d₁ as the magnetizing duty cycle, d₂ as the energy-feeding duty cycle, and 1 – d₁ – d₂ as the capacitor charge/discharge duty cycle, according to the different circuit mode combinations of each switching cycle T_s, and the proposed inverter can be designed into two working modes: the magnetizing charging working mode and magnetizing discharge working mode. The magnetizing charging working mode consists of the d₁T_s magnetizing mode, d₂T_s energy feeding mode, and (1 – d₁ – d₂)T_s buffer capacitor charging mode; the magnetizing discharge working mode consists of the d₁T_s magnetizing mode, d₂T_s energy feed mode, and (1 – d₁ – d₂)T_s buffer capacitor discharge mode. Taking the resistive load as an example, when the inverter works in the magnetizing charging mode, the power flow flows from the input source and the inductor to the buffer capacitor and the load. In the magnetizing discharge mode, the power flow flows from the input source and the buffer capacitor to the inductor and the load. By controlling the duty cycles d₁ and d₂, this two-mode modulation strategy can ensure that the inverter bridge outputs the appropriate modulation current and limit the current of the energy storage inductor and the voltage of buffer capacitor, controlling the average value of the input DC pulse current, which is equal, and thereby suppressing the low-frequency ripple of the input current.

Based on these two working modes, the proposed inverter can adopt the two-objective, three-closed-loop composite control strategy with the energy storage inductor current limit and buffer capacitor average voltage limit. The block diagram and principle waveform are shown in Figure 2. In Figure 2a, the cascaded double loop control composed of the buffer capacitor voltage average outer loop and the input current inner loop realizes the low-frequency ripple suppression of the input current, and the output voltage feedback control loop realizes the stability of the output voltage. In cascade double-loop control, the error of the buffer capacitor voltage average outer loop is amplified by the P regulator to obtain the signal I_iavg*, which is used as the reference value of the input current inner loop and the sum d_i of the magnetizing mode duty cycle d₁ and the energy feed-mode duty cycle d₂ in a switching cycle, which is directly obtained by the inner loop of the input current through the single-cycle control. The output voltage loop provides the feed-energy duty cycle d₂ through the PI regulator to realize the errorless tracking of the output voltage reference. Both i_sy0 and i_sy1 in the control circuit are the output voltage polarity judgment signal and the energy storage inductance current limit signal, respectively.

The combined logic circuit mainly selects the working mode of the inverter and generates the corresponding drive signal according to the control signal i_sy0, i_sy1, i_sy2, i_sy3. The regulation of the control signal i_sy2 is used to ensure that the average input current in each switching cycle can track the DC given and stabilize the buffer capacitor voltage; the feed-energy duty cycle d₂ is used to adjust the output voltage, and current signal i_sy1 of the energy storage inductor is used to determine the two working modes of the system to achieve the purpose of limiting the inductor current. Therefore, the driving logic signal of the switch S₁~S₆ of the inverter is shown in

Table 2. Drive logic signal under two target three-closed-loop compound controls.

isy0	isy1	isy2	isy3	S1	S2	S3	S4	S5	S6
1	x	1	1	1	0	1	0	0	0
1	x	1	0	1	0	0	1	0	0
1	1	0	x	0	0	0	0	0	0
1	0	0	x	0	0	0	0	1	1
0	x	1	1	0	1	0	1	0	0
0	x	1	0	0	1	1	0	0	0
0	1	0	x	0	0	0	0	0	0
0	0	0	x	0	0	0	0	1	1

.

4. Design Key Circuit Parameters

4.1. Buffer Capacitor

4.1.1. Buffer Capacitor Voltage Average Limit Value U_cavg*

The buffer capacitor voltage can be obtained from (6) as follows:

$$u_{\mathrm{c}}\left(t\right)=\sqrt{{({U_{\mathrm{cavg}}}^{*})}^2+{\displaystyle \frac{U_{\mathrm{o}}{I}_{\mathrm{o}}}{\omega C_{\mathrm{b}}}}\sin (2\omega t+\phi )}$$

(9)

In (9), U_cavg* is the one buffer capacitor voltage average limit value.

According to the switching equivalent circuit of the inverter energy feed mode, the diodes D₅ and D₆ must be in the cut-off state in this mode, and the body diodes of the switches S₅ and S₆ must be in the cut-off state.

In order to ensure that D₅ and D₆ are cut off when energy is fed, the capacitor voltage must meet the following:

$$u_{\mathrm{c}}\left(t\right)>\left|\left|u_{\mathrm{o}}\left(t\right)\right|-U_{\mathrm{in}}\right|$$

(10)

Both (1) and (9) can be combined into (10) to obtain the following:

$$\sqrt{{({U_{\mathrm{cavg}}}^{*})}^2+{\displaystyle \frac{U_{\mathrm{o}}{I}_{\mathrm{o}}}{\omega C_{\mathrm{b}}}}\sin (2\omega t+\phi )}>\left|\sqrt{2}{U}_{\mathrm{o}}|\sin (\omega t)|-U_{\mathrm{in}}\right|$$

(11)

Then, the case of limit can be considered alongside the following:

$$\sqrt{{({U_{\mathrm{cavg}}}^{*})}^2-{\displaystyle \frac{U_{\mathrm{o}}{I}_{\mathrm{o}}}{\omega C_{\mathrm{b}}}}}>\sqrt{2}{U}_{\mathrm{o}}-U_{\mathrm{in}}$$

(12)

4.1.2. Buffer Capacitor Value C_b

In addition, the value of the buffer capacitor depends on the pulsation of the buffer capacitor voltage and the low-frequency pulsation of the buffer capacitor voltage is selected not to exceed K_c% of the limited value U_cavg*, as shown below:

$$\sqrt{{({U_{\mathrm{cavg}}}^{*})}^2+{\displaystyle \frac{U_{\mathrm{o}}{I}_{\mathrm{o}}}{\omega C_{\mathrm{b}}}}}-{U_{\mathrm{cavg}}}^{*}\le K_{\mathrm{c}}\%{U_{\mathrm{cavg}}}^{*}$$

(13)

From the above formula,

$$C_{\mathrm{b}}\ge {\displaystyle \frac{U_{\mathrm{o}}{I}_{\mathrm{o}}}{\left[2K_{\mathrm{c}}\%+{(K_{\mathrm{c}}\%)}^2\right]\omega {({U_{\mathrm{cavg}}}^{*})}^2}}$$

(14)

4.2. Energy Storage Inductor

4.2.1. Energy Storage Inductor Current Limit Value I_L*

In order to ensure the normal operation of the inverter and completely transfer the low-frequency ripple to the buffer capacitor, it is necessary to effectively limit the current of the energy storage inductor. This requires that the charging mode of the inverter ensures that the current of energy storage inductor drops, while the discharge mode can ensure that the energy storage inductor current rises. It can be seen from (15) that when i_o and u_o reach the peak at the same time, d₂ is the largest. If the buffer capacitor discharges, i_L rises, and buffer capacitor discharges can make i_L rise in any case; then, the inverter must meet the following requirements:

$${\displaystyle \frac{U_{\mathrm{in}}{d}_{1\min }{T}_{\mathrm{s}}}{L}}+{\displaystyle \frac{{U_{\mathrm{cavg}}}^{*}(1-d_{1\min }-d_{2\max })T_{\mathrm{s}}}{L}}\ge {\displaystyle \frac{(u_{\mathrm{o}\max }-U_{\mathrm{in}})d_{2\max }{T}_{\mathrm{s}}}{L}}$$

(15)

Combined with the system control strategy, we can obtain the following:

$$\left\{\begin{array}{cc}{d}_{2\max }& ={\displaystyle \frac{i_{\mathrm{o}\max }}{i_{\mathrm{L}\min }}}\approx {\displaystyle \frac{\sqrt{2}{P}_{\mathrm{o}}}{(1-K_{\mathrm{L}}\%)U_{\mathrm{o}}{I_{\mathrm{L}}}^{*}}}\hfill \\ d_{1\min }& ={\displaystyle \frac{i_i}{i_{\mathrm{L}\min }}}-d_{2\max }\hfill \\ & ={\displaystyle \frac{P_{\mathrm{o}}}{(1-K_{\mathrm{L}}\%)U_{\mathrm{in}}{I_{\mathrm{L}}}^{*}}}-{\displaystyle \frac{\sqrt{2}{P}_{\mathrm{o}}}{(1-K_{\mathrm{L}}\%)U_{\mathrm{o}}{I_{\mathrm{L}}}^{*}}}\hfill \end{array}\right.$$

(16)

where K_L% is the pulsation of the inductor current.

Both (7) and (16) can be combined into (15) to obtain the following:

$${I_{\mathrm{L}}}^{*}\ge {\displaystyle \frac{P_{\mathrm{o}}}{(1-K_{\mathrm{L}}\%)}}({\displaystyle \frac{1}{U_{\mathrm{in}}}}+{\displaystyle \frac{1}{{U_{\mathrm{cavg}}}^{*}}})$$

(17)

In view of the lowest possible line loss, i_L needs to be as small as possible, so (17) is equal.

4.2.2. Energy Storage Inductor Value L

According to the switching equivalent circuits of four circuit modes, the variation in i_L under each circuit mode is as follows:

$$\Delta i_{\mathrm{L}\mathrm{mag}}={\displaystyle \frac{U_{\mathrm{i}}}{L}}{d}_1{T}_{\mathrm{s}}$$

(18)

$$\Delta i_{\mathrm{L}\mathrm{rec}}=-{\displaystyle \frac{u_{\mathrm{cb}}}{L}}(1-d_1-d_2)T_{\mathrm{s}}$$

(19)

$$\Delta i_{\mathrm{L}\mathrm{disc}}={\displaystyle \frac{u_{\mathrm{cb}}}{L}}(1-d_1-d_2)T_{\mathrm{s}}$$

(20)

$$\Delta i_{\mathrm{L}\mathrm{fed}}={\displaystyle \frac{\left(U_{\mathrm{i}}\mp u_{\mathrm{o}}\right)}{L}}{d}_2{T}_{\mathrm{s}}$$

(21)

When the output voltage is near the zero-crossing point, d₂ approaches zero, and d₁ is the largest. In this interval, the inverter is mainly switched to the charging and discharging modes of the buffer capacitor, so the pulsation of energy storage inductor current is the largest:

$$\Delta i_{\mathrm{L}\max }={\displaystyle \frac{U_{\mathrm{in}}{d}_{1\max }{T}_{\mathrm{s}}}{L}}+{\displaystyle \frac{{U_{\mathrm{cavg}}}^{*}(1-d_{1\max })T_{\mathrm{s}}}{L}}$$

(22)

Combined with the proposed system control strategy, we can obtain the following:

$$d_{1\max }={\displaystyle \frac{I_{\mathrm{i}}}{i_{\mathrm{L}\min }}}={\displaystyle \frac{P_{\mathrm{o}}}{(1-k_{\mathrm{iL}}\%)U_{\mathrm{in}}{I_{\mathrm{L}}}^{*}}}$$

(23)

According to the state limit condition, it is known that the continuous occurrence of the discharge circuit mode lasts for up to two switching cycles. Therefore, the maximum relative pulsation of inductor current is as follows:

$${\displaystyle \frac{\left|\Delta i_{\mathrm{L}\max }\right|}{{I_{\mathrm{L}}}^{*}}}={\displaystyle \frac{U_{\mathrm{in}}{d}_{1\max }{T}_{\mathrm{s}}}{L{I_{\mathrm{L}}}^{*}}}+{\displaystyle \frac{{U_{\mathrm{cavg}}}^{*}(1-d_{1\max })T_{\mathrm{s}}}{L{I_{\mathrm{L}}}^{*}}}$$

(24)

If the ripple of the energy storage inductor current is no greater than k_iL%, then

$$L\ge {\displaystyle \frac{U_{\mathrm{in}}{T}_{\mathrm{s}}}{{I_{\mathrm{L}}}^{*}{k}_{\mathrm{i}\mathrm{L}}\%}}{\displaystyle \frac{P_{\mathrm{o}}}{(1-k_{\mathrm{i}\mathrm{L}}\%)U_{\mathrm{in}}{I_{\mathrm{L}}}^{*}}} +{\displaystyle \frac{{U_{\mathrm{cavg}}}^{*}{T}_{\mathrm{s}}}{{I_{\mathrm{L}}}^{*}{k}_{\mathrm{i}\mathrm{L}}\%}}\left(1-{\displaystyle \frac{P_{\mathrm{o}}}{(1-k_{\mathrm{i}\mathrm{L}}\%)U_{\mathrm{in}}{I_{\mathrm{L}}}^{*}}}\right)$$

(25)

4.3. Filter Capacitor

4.3.1. Input Filter Capacitance Value C_i

Assuming that the DC source has an internal resistor r_i, in order to make the harmonics in the input current i_i with a frequency greater than f_i be filtered by C_i, and attenuated below K%, then the following is performed:

$${\displaystyle \frac{1}{\sqrt{1+{\left(2\pi f_{\mathrm{i}}{r}_{\mathrm{i}}{C}_{\mathrm{i}}\right)}^2}}}\le K\%$$

(26)

Therefore, the input filter capacitor C_i is as follows:

$$C_{\mathrm{i}}\ge {\displaystyle \frac{\sqrt{{\left(1/\mathrm{K}\%\right)}^2-1}}{2\pi r_{\mathrm{i}}{f}_{\mathrm{i}}}}$$

(27)

4.3.2. Output Filter Capacitance Value C_f

Combined with the four circuit modes of the proposed inverter, it can be seen that in the non-energy-feeding stage, C_f supplies power to the load, and the voltage variation caused by it is the output voltage ripple Δu_o, which can be expressed as follows:

$$\Delta u_{\mathrm{o}}={\displaystyle \frac{\Delta Q}{C_{\mathrm{f}}}}={\displaystyle \frac{i_{\mathrm{o}}\Delta t}{C_{\mathrm{f}}}}={\displaystyle \frac{i_{\mathrm{o}}(d_1+d_3)T_{\mathrm{s}}}{C_{\mathrm{f}}}}={\displaystyle \frac{i_{\mathrm{o}}(1-d_2)T_{\mathrm{s}}}{C_{\mathrm{f}}}}$$

(28)

The ripple of the output voltage is obtained as follows:

$${\displaystyle \frac{\Delta u_{\mathrm{o}}}{u_{\mathrm{o}}}}={\displaystyle \frac{i_{\mathrm{o}}(1-d_2)T_{\mathrm{s}}}{u_{\mathrm{o}}{C}_{\mathrm{f}}}}={\displaystyle \frac{(1-d_2)T_{\mathrm{s}}}{Z_{\mathrm{L}}{C}_{\mathrm{f}}}}$$

(29)

If the ripple is less than K_o%, then the expression of C_f can be obtained from (29) as follows:

$$C_{\mathrm{f}}\ge {\displaystyle \frac{(1-d_{2\min })T_{\mathrm{s}}}{{\mathrm{K}}_{\mathrm{o}}\%Z_{\mathrm{Lmin}}}}={\displaystyle \frac{T_{\mathrm{s}}}{{\mathrm{K}}_{\mathrm{o}}\%Z_{\mathrm{Lmin}}}}={\displaystyle \frac{P_{\mathrm{o}\max }{T}_{\mathrm{s}}}{{\mathrm{K}}_{\mathrm{o}}\%{U_{\mathrm{o}}}^2}}$$

(30)

5. System Modeling and Controller Parameter Design

According to the system power conservation, when the input power and output power are not equal, excess energy is transferred to the buffer capacitor, causing the voltage rise of the buffer capacitor, according to the power relationship:

$$P_{\mathrm{i}}-P_{\mathrm{o}}=\Delta P$$

(31)

In (31), ΔP is the power difference. According to the relation of power and energy,

$$\Delta W={\displaystyle {\int }_0^t\Delta Pdt}={\displaystyle \frac{1}{2}}{C}_{\mathrm{b}}({U_{\mathrm{cavg}}}^2-{({U_{\mathrm{cavg}}}^{*})}^2) ={\displaystyle \frac{1}{2}}{C}_{\mathrm{b}}(U_{\mathrm{cavg}}+{U_{\mathrm{cavg}}}^{*})(U_{\mathrm{cavg}}-{U_{\mathrm{cavg}}}^{*})$$

(32)

Since U_cavg fluctuates slightly near U_cavg*, U_cavg can be approximately replaced by U_cavg*, then the following can be calculated:

$$\Delta W\approx C_{\mathrm{b}}{U_{\mathrm{cavg}}}^{*}(U_{\mathrm{cavg}}-{U_{\mathrm{cavg}}}^{*})$$

(33)

According to the power conservation, the bus capacitor voltage outer loop output I_iavg* is used as the reference for the input current single cycle control inner loop. Single-cycle control is used mainly to realize that the average value of the input pulse current in each switching cycle is equal to the average value of the input current, and the single-cycle control can be equivalent to a proportional link K_oc here. The control block diagram on DC side is shown in Figure 3.

Since the current loop on the DC side before correction is a type I system, the P regulator is used here, and the open-loop transfer function from the output power to the input current is as follows:

$$G_{P_{\mathrm{o}}-i_{\mathrm{i}}}(s)={\displaystyle \frac{U_{\mathrm{i}}{K}_{\mathrm{o}\mathrm{c}}{K}_{\mathrm{p}}}{C_{\mathrm{b}}{U_{\mathrm{cavg}}}^{*}s}}$$

(34)

In Figure 3, the reference of the average value of the bus capacitor voltage is U_cavg*, and the error is ΔU_cavg. Controlling the average value of the buffer capacitor voltage to retain U_cavg*, which is essential to control the input power and the load power balance, the given loop is equivalent to the load power P_o, the output feedback of the loop is the input power U_iI_i, and the input current inner loop can be regarded as the control object of the outer loop.

According to (34), taking into account the stability and fast following of the system, it is assumed that the crossing frequency of the open-loop transfer function is f_c1 = 10 Hz, and the phase margin is 90 degrees, the system can track the low-frequency DC signal well, and the system stability is good.

$${\left|{\displaystyle \frac{U_{\mathrm{i}}{K}_{\mathrm{o}\mathrm{c}}{K}_{\mathrm{p}}}{C_{\mathrm{b}}{U_{\mathrm{cavg}}}^{*}s}}\right|}_{s=j2\pi \times f_{c1}}=1$$

(35)

The inverter bridge adopts unipolar the SPWM modulation scheme, and the circuit carrier frequency is much higher than the modulation wave frequency, ignoring the impact of the switching action on the system; then, the inverter bridge can be approximated as a gain link K_PWM

$$K_{\mathrm{PWM}}={\displaystyle \frac{I_{\mathrm{m}}(s)}{I_{\mathrm{r}}(s)}}$$

(36)

In (36), I_m(s) is the modulated current, and I_r(s) is the modulated current reference.

When the capacitor filtering is adopted, the transfer function of output voltage U_o(s) and inverter bridge modulation current I_m(s) is as follows:

$$G_{\mathrm{C}}(s)={\displaystyle \frac{U_{\mathrm{o}}(s)}{I_{\mathrm{m}}(s)}}={\displaystyle \frac{Z_{\mathrm{L}}(s)}{Z_{\mathrm{L}}(s)C_{\mathrm{f}}s+1}}$$

(37)

In (37), Z_L(s) is the load impedance.

Figure 4 shows the inverter output voltage loop control block diagram, where G_PI(s) is the transfer function of PI controller, and H_u(s) is the output voltage feedback coefficient.

The open-loop transfer function can be obtained from Figure 4:

$$G_{\mathrm{u}\mathrm{o}\_\mathrm{open}}(s)=K_{\mathrm{PWM}}{G}_{\mathrm{PI}}(s)G_{\mathrm{C}}(s)H_{\mathrm{u}}(s)$$

(38)

Taking into account the stability and fast following of the system, the crossing frequency is set to f_c2 = f_s/10 in order to make the amplitude–frequency response decay faster at a higher frequency, which is set to the zero point of the PI controller at s = −1; then,

$$\left\{\begin{array}{l}{\displaystyle \frac{K_{\mathrm{I}}}{K_{\mathrm{P}}}}=1\\ {\left|{\displaystyle \frac{K_{\mathrm{P}}s+K_{\mathrm{I}}}{s}}\cdot {\displaystyle \frac{K_{\mathrm{PWM}}R}{R{C}_{\mathrm{f}}s+1}}\right|}_{s=j2\pi \times f_{c2}}=1\end{array}\right.$$

(39)

6. Simulation and Experiment

6.1. Simulation Analysis

Under the parameters shown in

Table 3. Key parameters of circuit.

Circuit Parameters	Numerical Values
Rated capacity S/VA	1000
Rated output voltage RMS Uo/V	220
Input voltage Ui/V	90
Energy storage inductor L/mH	1.5
Buffer capacitor Cb/uF	120
Input filter capacitor Ci/uF	200
Output filter capacitor Cf/uF	16.8
Switching frequency f/kHz	50

, the proposed inverter adopts the output voltage feedback SPWM control strategy and the dual-objective three-closed-loop composite control strategy, respectively, and the simulation results are shown in Figure 5. In the output voltage feedback SPWM control strategy, the limited value of buffer capacitor voltage is U_cavg* = 260 V, and the limited value of the energy storage inductor current is I_L* = 30 A. In the double objective three-closed-loop composite control strategy, the buffer capacitor voltage limit value is U_cavg* = 360 V, and the energy storage inductor current limit value is I_L* = 18 A. The current ripple of the two control strategies is no more than 20%, and the voltage ripple of the buffer capacitor is not more than 20%.

Figure 5a–d depict the simulation waveforms of the proposed inverter using output voltage feedback SPWM control, and Figure 5e–h show the simulation waveform of the proposed inverter using three-closed-loop composite control, which can suppress the low-frequency ripple of the input current. (1) It can be seen from Figure 5b,f that both control strategies can realize single-stage boost inverter, and the quality of output voltage and current waveforms are high. The output voltage THD of the output voltage feedback SPWM control strategy is 3.2%, and the output voltage THD of the dual-objective three-closed-loop composite control strategy is 1.5%. (2) From Figure 5a,e, it can be seen that the three-closed-loop control strategy can realize power decoupling to suppress the low-frequency ripple of the input current, so that the input current is approximately DC. (3) In Figure 5d,h, at full load, the second harmonic content of the input current of the inverter system controlled by output voltage feedback SPWM is 10.6%, and the second harmonic content of the input current of the inverter system controlled by the three-closed-loop composite control is 1%. Clearly, the three-closed-loop composite control strategy with the limit of energy storage inductor current and the buffer capacitor voltage brings about a better low-frequency ripple suppression effect. (4) As can be seen from Figure 5c,g, when the three-closed-loop composite control is adopted, the voltage of the buffer capacitor double-frequency pulsation, which achieves the purpose of transferring the low-frequency pulsation power on the load side to the buffer capacitor, the voltage ripple component of the buffer capacitor is 11%, which meets the design requirements.

The steady-state full-load simulation waveform of the inverter under the three-closed-loop composite control with the energy storage inductor current limit and the buffer capacitor voltage limit is shown in Figure 6. As can be seen from Figure 6, (1) The output voltage and current THD are 1.5%, and the waveform quality is high. (2) The proposed state limit modulation strategy can smoothly switch between two working modes and four circuit modes and realize the limitation of two state quantities. (3) This can drive resistive, resistive-inductive, and resistive-capacitive loads.

The simulation waveforms of the load mutation on the output side of the inverter are shown in Figure 7. The resistive load power changes from 1000 W to 500 W, and the changes from 500 W to 1000 W. It is clear from Figure 7 that the inverter has good dynamic performance and can realize the fast-tracking and stability of output voltage when the load changes.

6.2. Experimental Results

A 1000 VA 100 VDC/220 V50 HzAC single-stage boost single-phase inverter experimental device was designed and built using the parameters in Table 3, as shown in Figure 8. The power switches S₁~S₆ are IPW60R099C6 (Infineon, München, Germany), and the diodes D₁~D₆ are DSEI60-06A (Littelfuse, Chicago, IL, USA).

The experimental waveforms of the inverter under the two strategies are shown in Figure 9. Among them, Figure 9a–d represent the experiment waveforms of the proposed inverter using output voltage feedback SPWM control, and Figure 9e–h show the experiment waveforms of the inverter using three-closed-loop composite control that can suppress the low-frequency ripple of the input current. It can be seen from Figure 9 that the proposed inverter under the two control strategies can realize single-stage booster inverters. The three-closed-loop control strategy can realize power decoupling and transfer low-frequency pulsating power on the load side to the buffer capacitor u_c, while u_c pulsates at twice the frequency near the limit value so as to suppress the low-frequency ripple component of input current and make the input current approximate the DC. It can be seen from Figure 9d,h that the secondary ripple content of the input current before decoupling is 10.13%, and the secondary ripple content of the input current after decoupling is 1.2%.

The steady-state waveforms of the inverter with resistive full load, inductive full load (PF = 0.75), and capacitive full load (PF = 0.75) are shown in Figure 10. The experimental waveforms show that the following: (1) when the inverter is working normally, the buffer capacitor voltage is stable at 360 V and pulsates at double frequency, and the inductor current of the energy storage is stable around 18 A, which is consistent with theoretical analysis and simulation. Due to the actual inductance value, the capacitance value, and the error of the duty cycle generated by DSP, the capacitor voltage and inductor current pulsation are slightly larger than the design value. (2) The proposed inverter is suitable for resistive, resistive–inductive, and resistive–capacitive loads, and the output voltage and current waveforms are of good quality. (3) Figure 10h,I give the high-frequency switching waveforms of the positive and negative half-cycle operating modes of the output voltage and four circuit modes, respectively, where T_a and T_b correspond to the discharge working mode and charging working mode, respectively.

The experimental waveforms of the single-stage, single-phase current source inverter with a source buffer when the load on the output side changes abruptly are shown in Figure 11. The resistive load power changes from 1000 W to 500 W and changes from 500 W to 1000 W, respectively.

It can be seen from the experimental waveforms in Figure 11 that the proposed inverter adopts three-closed-loop composite control with an energy storage inductor current limit and buffer capacitor voltage limit, which has good steady-state and dynamic performance. When the load changes, the inverter state fluctuates slightly, and the output voltage and current can transition quickly and smoothly. The experimental results are basically consistent with theoretical analysis and simulation, which verify the correctness and feasibility of the proposed research scheme.

The losses of the proposed converter are mainly inductor loss (copper loss P_Cu and iron loss P_Fe) and power device loss (switching loss P_Sw and on-state loss P_S-on). Due to the inductor loss, because the inductor current is dominated by the DC component and the value is large, P_Cu is much larger than P_Fe, and the inductor loss is approximately equal to P_Cu, while P_Cu basically does not change with the output power P_o. In power device loss, P_Sw depends on the number of switches of the switch action, frequency, voltage stress, and current stress when the circuit mode is switched. P_S-on depends on the number of switch conductions, the conduction time, the on-state current, and internal resistance in each circuit mode. Under different P_o, the operating modes that switch by each high-frequency switching cycle are roughly the same (i.e., the number of switches working is the same), and the switching frequency and input/output voltage are basically unchanged (i.e., the voltage stress is unchanged). Considering that the inductor current is approximately DC, the influence of other factors is basically unchanged except when the output current causes P_S-on increases with P_o. Figure 12 shows the efficiency of the system before and after power decoupling under resistive load and the efficiency of the input voltage U_i change under full load. In Figure 12a, the efficiency increases with the increase in output power in both cases. This is because when P_o is low, the inherent loss P_Cu is dominant. As P_o increases, the proportion of P_Cu decreases. Meanwhile, P_o increases, and the duty cycle of the magnetization mode and the energy-feeding mode increases, resulting in a significant increase in P_S-on, so the rate of increase in efficiency decreases. In addition, because the inverter bridge uses four blocking diodes, which bring a certain proportion of system loss, with the development of the reverse–resistance device, these blocking diodes can be omitted so that the system efficiency can be greatly improved.

In Figure 12b, the efficiency increases with the increase in input voltage U_i. From (17), it can be seen that as U_i increases, the inductor current limit value decreases, resulting in a decrease in P_Cu. At the same time, the duty cycle of the inductance magnetization mode decreases, and the duty cycle of the energy-feeding mode increases slightly. Therefore, P_S-on decreases, while P_Sw does not change significantly, so the efficiency increases.

Table 4. Performance comparison among the converters.

Parameters	[21]	[23]	[24]	[28]	Proposed
No. of levels	2	1	1	1	1
No. of switches	12	6	7	5	6
No. of diodes	1	0	0	1	6
Capacitance	20 µF/10 µF	100 µF/10 µF	170 µF/220 µF/220 µF	22 µF	120 µF/200 µF/16.8 µF
Inductance	70 µH/10 mH	300 µH/0.8 mH	2.5 mH/1.8 mH	30 µH/1.5 mH	1.5 mH
Control complexity	Complex	Complex	Medium	Medium	Simple
Boost level	Small	Medium	Larger	Larger	Larger
Rated power	500 W	400 W	1000 W	320 W	1000 W
Secondary ripple content	1.73%	-	-	3.67%	1.2%
Efficiency	-	-	96.3%	95.8%	85%
Output voltage THD		-	-	5.62%	1.5%
Output dynamic response time	-	-	40 ms	25 ms	3 ms

“-” Denotes that the metric was not provided in the reference.

shows the comparison of several research schemes. In [21], the proposed scheme uses a thin film capacitor to replace the electrolytic capacitor, which greatly reduces the capacitance value of the buffer capacitor; the inductance parameter is small and has good secondary ripple suppression ability. However, the control strategy is complex, the boost ratio is low, and experimental data such as efficiency, output voltage THD, and dynamic response time are not given. The scheme proposed in [23] suppresses the low-frequency ripple of the input current to a certain extent, but the control method is complex, and the relevant data of the experimental results are not given. The control method used in [24] is relatively simple, the system efficiency is high, and the output dynamic response time is fast when the load changes abruptly. However, the number of energy storage elements is the largest, and the value is the largest, and the experimental data, such as the second harmonic content and the output voltage THD, are not given. In [28], the proposed scheme has fewer components, higher system efficiency, and faster dynamic response time, but the secondary ripple content of the input current and the output voltage THD are relatively high. The control method proposed in this paper is simple: the output voltage THD and input current second harmonic content are low, and the dynamic performance is good, but the system efficiency is low. With the development of the reverse resistance device, the reverse resistance device can be used to replace the MOS tube of the inverter bridge of the proposed circuit in the future, and four blocking diodes can be removed, which significantly reduces the loss of the power device and makes the system’s obtain better overall efficiency.

7. Conclusions

• The circuit topology of the single-stage boost source single-phase inverter is proposed, which is mainly composed of the energy storage inductor, active buffer circuit, and single-phase current source inverter bridge and filter. The active buffer circuit provides the hardware conditions for the inverter energy feedback and input and output power decoupling, so the circuit has the ability of a single-stage boost inverter and can undertake the low-frequency ripple suppression of the input current.
• A three-closed-loop composite control strategy is proposed under the limitation of the inductor current and buffer capacitor voltage, and the limit values of the inductor current and buffer capacitor voltage are derived, respectively, according to the circuit boost transformation mechanism and working mode characteristics.
• The proposed inverter has four circuit modes in the boost stage, where the energy storage inductor can be demagnetized through the energy feed mode, and the circuit mainly works in the magnetizing mode and the energy feed mode. In the buck stage of the inverter, the energy storage inductor can only be demagnetized by the buffer capacitor, and the circuit mainly works in the buffer capacitor charging and discharging modes.
• The circuit parameters of the proposed inverter are analyzed and designed. The mathematical model of the inverter is established from the perspective of energy conservation, combined with the state space average method, and the controller parameters of the system are designed. The simulation and experiments show that the proposed inverter is equipped with good input current low-frequency ripple suppression and single-stage boost conversion capability. It has a simple circuit and control, the output voltage THD is low, and can adapt to various types of loads, such as resistive, resistive-inductive, and resistive-capacitive load, and has a good steady state and dynamic performance.