Advanced Single-Phase PLL-Based Transfer Delay Operators: A Comprehensive Review and Optimal Loop Filter Design

Abstract

In recent years, several research works have addressed and developed the phase-locked loop (PLL) in single-phase grid-connected converters with different structures and properties. Each has merits and demerits, such as a complex structure, high computational burden, and slow transient response. This paper aims to comprehensively review advanced single-phase PLLs based on transport delay operators to realize signal orthogonality. A deep insight into the PLLs’ small-signal modeling, main characteristics, stability analysis, and loop filter design are provided in this paper. The main advantages and drawbacks are explained for each type of PLL in terms of different performance indexes, such as settling time, estimation error, and ripples in the estimated grid information. This paper also aims to provide optimal tuning and design of the loop filter gains from the large-signal model point of view, including all the nonlinearities, adopting the stochastic optimization method. All simulations are implemented using the MATLAB/Simulink 2018b environment to validate all theoretical analyses of this paper. The sampling and nominal frequencies are set to be 100 kHz and 50 Hz throughout all the simulation studies.

1. Introduction

The phase-locked loop (PLL) is one of the synchronization techniques proposed in the literature and has received attention in recent years because of the large number of renewable energy systems connected to the grid. In simple words, the PLL is a negative feedback control system that locks its output with its input with zero phase error. Therefore, it is an essential key player in grid-connected power converters to ensure the stability, reliability, and high power quality of power conversion [1,2].

Grid synchronization is essential in grid-connected applications, including active power filters, pulse width modulation (PWM), uninterruptible power supply (UPS), dynamic voltage restorer (DVR), flexible AC transmission (FACT), high voltage direct current (HVDC) transmission, controllable rectifier, and distributed generation (DG) [3,4,5,6,7]. Power quality issues include voltage sag/swell, harmonic distortion, DC offset, and phase and frequency variations. All these issues affect the performance of the SRF-PLL. This required designing a PLL to improve the performance of the grid-connected system and mitigate power quality issues, which could accurately and quickly detect the grid’s amplitude, phase, and frequency under different distortions [8,9,10].

The DC offset in the grid voltage can result from different sources, such as grid faults, geomagnetic phenomena, A/D conversion, the offset of voltage sensors, sampling, measurement errors, the DC injection by the distributed system, and implementation of control algorithms in microcontrollers [11,12,13,14,15,16,17]. The presence of the DC offset resulted in a fundamental frequency oscillation in the estimated grid parameters, affecting the closed-loop stability, power quality, and operation of the grid-connected converter. Different international standards such as IEC61727 [18] and IEEE 1547–2003 [19] impose a strict limit on the amount of DC injection, where it is less than 0.5% and 1% of the rated current, respectively. Therefore, the PLL must effectively suppress the influence of the DC offset from the grid in practical applications. Besides that, the extensive integration of the power electronics into the grid increases the nonlinearity, causing increased harmonic distortion. Different sources cause harmonics and inter-harmonics in the grid voltage, such as power electronics converters in adjustable speed drives, switched-mode computer power supplies, energy-saving lamps, and interference converters between renewable energy generation and the power grid [20,21]. Total harmonics distortion (THD) is one of the essential measurements to evaluate the quality of the power systems. Several standards such as the American standard IEEE519 and European standard EN50160 impose a strict limit on the harmonic injection to the grid. In the IEEE519 standard, the THD is 8% for low voltage networks and 5% for single harmonics [22], while in the EN50160 standard, 8% considers up 40th harmonics [23].

Another issue that appears mainly in weak grids is an unbalanced grid voltage. Imbalances can result from nonlinear loads, single-phase loads, unequal line impedance, or grid faults, adversely affecting electrical loads and power-distributed generators. The imbalance of grid voltage appears in stability margin reduction and transient performance deterioration [24,25]. Also, vibration and noise may result when high-frequency transformers are integrated with the converter, especially under non-sinusoidal voltage excitation [26].

Several types of research study the effect of the PLL in grid synchronization on stability, especially under weak grid conditions [27,28,29,30]. The symmetrical PLL is introduced in [27] to address the frequency-coupling oscillations that resulted from the asymmetrical dynamics of the PLLs by implementing single-input, single-output (SISO) impedance shaping to enhance stability under weak grid conditions. In [28], by adding a grid current feedforward, a robust delay-based PLL is designed to work with a high grid impedance with a short-circuit ratio (SCR) equal to 3. The stability is studied based on the inverter output impedance model to ensure stable operation in case of large impedance. Near the fundamental frequency, the work in [29] shows that the PLL introduces a negative resistance. Two reshaping methods are designed to improve the stability margin within the PLL bandwidth. These methods are developed based on current and direct power controls. At low-order frequencies, more serious harmonics and instabilities can result from the interaction between the inverters and the grid impedance. The stability and harmonics of single-phase systems are comprehensively reviewed in the weak grid. Also, the impact of TD-PLL and SOGI-PLL on the low-order harmonics and stability in weak grids is studied in [30]. This work concludes that the high attenuation of the PLL is required to achieve high rejections of low-order grid current harmonics [30].

Much research in the literature has dealt with the performance improvements of single phase (1-ϕ) PLLs under abnormal grid conditions such as harmonics and DC offset, which must be addressed to avoid any synchronization problems [31]. The general PLL structure contains mainly three parts: the phase detector (PD), which generates the phase error information; loop filtering (LF), which regulates the error signal to zero; and the voltage-controlled oscillator (VCO), which produces the synchronized vectors in its output [32].

Figure 1 shows the general structure of a 1-ϕ synchronous reference frame (SRF)-based PLL. The PD is the element that distinguishes one PLL from another [33]. Quadrature signal generator (QSG)-PLLs are more popular than power-based PLLs (pPLLs) in applications involving power electronics and power systems due to their simple implementation and robust performance against existing disturbances [34,35,36,37].

The performance of available enhanced PLLs (EPLLs) [38,39,40,41,42] and second-order generalized integrator-based PLLs (SOGI-PLLs) [43,44,45,46] are affected by different disturbances, such as subharmonics and inter-harmonics. The work in [47] introduces solving this issue by modifying the structure using the adaptive filter. The modified structure increased the disturbance rejection ability and minimized the computational burden by accurately detecting grid parameters.

Using frequency adaptive with SOGI-PLLs increases the design and implementation complexity, makes tuning sensitive, and reduces the stability margin [44,46]. To solve these issues, a fixed frequency SOGI-PLL (FFSOGI-PLL) is introduced in [48], where both amplitude and phase compensations are used. However, the nonzero phase error appears in the frequency jump case. The work in [49] considers the dynamics of the phase error compensator to be more accurate. All structures introduced in [48,49] cannot reject the DC offset, so the work in [32] presents the arbitrary DSC (ADSC) with FFSOGI-PLL, which can achieve a fast dynamic performance and effective rejection of the DC offset. However, in this structure, the memory requirement is increased. Two improved FFSOGI-PLLs are introduced in [50] with an accurate phase angle estimation. The first structure is with DC offset compensation, and the second with positive sequence component separation. Accurate estimating of the phase angle improves the dynamic performance. However, specialized floating-point microcontrollers and DSP control platforms must be used to ensure fast implementation.

An enhanced frequency-fed SOGI-PLL is proposed in [51]. The frequency is estimated using a Teager energy operator (TEO) using three consecutive samples, while the phase is calculated using the third-order polynomial approximation and phase unwrapping. A DSC with a 1/2-time delay removes the DC offset from the grid. These modifications enable the new structure to estimate fast grid parameters with less computational burden. However, the harmonics rejection ability depends on controlling the SOGI’s gain by fine-tuning. Another method is introduced in [52] to effectively eliminate the DC offset, combining a third-order generalized integrator (TOGI) and FLL. Compared with other SOGI-PLLs, the low-frequency noise of the PLL can be filtered easily. This structure was implemented in DSP to reduce the implementation complexity. Another modification to the SOGI-PLL using state space implementation is introduced in [53] to improve the stability and reduce the response time when the grid is distorted by using adaptation or a fixed pre-filtering stage with bandpass or low pass characteristics. However, the memory requirement is increased compared with conventional SOGI-PLLs. The authors in [53] suggest considering frequency feedback path (FFP) implementation with PLL or FLL in applications concerned with stability.

The work in [54] utilizes new filtering techniques based on multiple delayed signal cancellation (MDSC) operators, which are simple and have less memory requirement compared with the filtering based on cascaded delayed signal cancellation (CDSC) available in the literature [55,56,57,58,59]. In addition, MDSC operators can be implemented in direct form, which is considered a stable adaptive operator, and recursive form, which is regarded as a non-stable and non-adaptive operator. In addition, MDSC operators are applied to the EPLL as a pre-filtering stage to provide an accurate and fast dynamic response under adverse grid conditions, configuring the undesired harmonics by selecting the proper delay factor.

The all-pass filter PLL (APF-PLL) is a simple and stable performance method widely used in grid synchronization. However, APF-PLL performance degrades under distorted grid conditions, resulting in low-frequency oscillations appearing in the estimated phase and frequency [60,61,62,63,64]. To solve this problem, the work in [3] modified APF-PLLs to suppress harmonics and the DC offset effectively by using the band-pass filter (BPF) as a pre-filter of APF-PLL in the first structure, and the APF-PLL is integrated with the harmonic decoupling network (HDN) and multiple pre-filters. However, the second structure has a higher computational burden and lower stability margin, and the two structures do not perform effectively when the grid contains inter-harmonics.

Since the conventional SOGI-PLL cannot reject the influence of the DC offset, a new structure based on enhanced SOGI (ESOGI) with an APF-based fixed-frequency locked loop (FLL) is proposed in [12]. Compared with other based SOGI-PLLs, the ESOGI-FLL has a simple structure and is easily implemented in low-cost microcontrollers, in addition to having an adequate performance when the grid is polluted with a high DC offset value and a high rate of low-order harmonics. However, the total harmonics distortion in case of harmonics rejection is equal to 10%, higher than the maximum limit for grid-connected systems. Also, in [65], a single-phase type-1 FLL is utilized where the FLL is used in decoupling the OSG block. The double frequency oscillation is rejected by using a modified low-pass filter (LPF) with notch characteristic, and a phase combination is used to remove the phase offset error. Also, to ensure an accurate grid parameter estimation when the grid is polluted with harmonics, some selected low-order harmonics are filtered from the input signal. In this method, the following can be achieved: increased stability margin and response speed, and the tuning method is simplified. However, the linearized method is used to reject the phase offset error. This means that non-linearity is not taken into consideration. In addition, the LPF, NF blocks, and phase compensation increases the complexity of the design implementation.

The influence of the SOGI bandwidth is assumed to be an essential key in oscillation suppression [66], which is analyzed using the harmonics linearization method to derive the impedance mode of the SOGI-PLL. As a result, the system becomes unstable when the SOGI bandwidth is increased. And then, only decreasing the SOGI bandwidth improves the system stability in weak grid conditions.

The simplest and fastest method used to generate OSG in a single-phase system is a derivative function-based PLL. However, it suffers from high-frequency noise amplification under non-ideal grid conditions, as in [67,68]. The work in [69] proposes solving the derivative-based PLL issue by using a sliding mode-based arbitrary order exact differentiator. It utilizes a second-order generalized differentiator to generate a noise-free, fast, and exact OSG under any non-ideal condition, such as any variation in grid parameters, harmonics, noise, or DC offset.

In the literature, the simplest PLL is the type-1 PLL, where one integrator is used in the PLL’s control loop [70]. Therefore, a high stability margin can be achieved. However, in the case of the frequency variation, the average steady-state phase error is not zero, so it cannot be used in practice [71]. Several works used the same type-1 PLL structure while modifying the PLL’s control loop in the type-2 control system. On that basis it is referred to as a quasi-type-1 PLL (QT1-PLL), as in [72,73,74,75,76,77,78]. The MAF-QT1-PLL’s structure in [72] is a type-1 PLL, while the LF is a lag filter which is an LPF with proportional gain. The MAF is used in this structure as an LPF at a specific condition for high filtering capacity because it is assumed to be a linear phase filter. The amplitude normalization scheme (ANS) removes the dependency of the PLL’s phase error in input voltage and the PLL’s dynamic and stability sensitivity to the amplitude variations. In addition, a phase compensator is used to achieve a zero phase error. A fast transient response, a good stability margin, and a good disturbance rejection under distorted and unbalanced grid conditions can be achieved using this structure. However, the ability of the disturbance rejection for this structure is decreased when the grid frequency deviation from its nominal value is increased. This means the ability of disturbance rejection of this structure is affected by the value of frequency deviation. To remove the frequency-dependent characteristics under distorted grid conditions in [72], a frequency-adaptive improved MAF-QT1-PLL (FAMAF-QT1-PLL) is proposed in [73]. The modifications use a correction link, frequency-adaptive realization, and a regulator parameter setting method. The correction link and QT1-PLL are used for response speed improvement, while the adaptation with weighted mean value (WMV) is used for harmonics rejection improvement. The zero phase error and good transient performance can accurately be tracked using FAMAF-QT1-PLL during the frequency variation, phase jump, and distorted and unbalanced grid voltage. However, the type of harmonics that can be blocked is only non-triple harmonics. A third-order MAF-QT1-PLL (TQT1-PLL) is proposed in [74] where two filter types are used; in-loop third-order MAF and a pre-filtering based second-order fast DSC (FDSC) operator, to enhance the performance under the distorted and unbalanced condition with frequency variation which is the worst case scenario. This structure can reject the non-triple odd harmonics and the fundamental frequency negative sequence (FFNS) and reduce the ripple in the estimated grid parameters. However, this results in the cost of high sensitivity to the sub- and inter-harmonics.

In the previous structures, stability and transient response reductions appeared when MAF was used to eliminate the FFNS. Because of that, an improved version of QT1-PLL is introduced in [75] with the in-loop filtering stage integrated into the QT1-PLL, containing a second-order lead compensator (SOLC), notch filter (NF), first-order lead compensator (FOLC), and MAF. The adaptive SOLC is used to filter the input signal from FFNS, the MAF is used to reject the odd harmonics and FFNS, while the non-adaptive NF is used to filter the interference at the resonance frequency of the lead compensator. The MAF and NF caused a lagging phase in the inner loop, resulting in phase margin reduction. Because of that, the work in [75] suggests using FOLC to offset the phase lag. This structure accurately works under distorted and unbalanced grid conditions. However, adding more components increased the complexity of the overall system.

In [76], an enhanced QT1-PLL is introduced where the frequency-fixed DSC and two APF are used as a pre-filtering stage. A DSC with a half-cycle time delay is used for DC offset rejection, while two half cycles for MAF are used as APF for odd harmonics rejection. A super-twisting sliding mode controller is used to improve the transient response speed. This structure has excellent DC offset and harmonics rejection, but the computational complexity and memory requirement increase. In addition, the phase and amplitude compensators are required in this structure due to the use of the fixed frequency APF. The work in [77] is extended to the three-phase system where a parallel DSC and MAF are integrated into the QT1-PLL to enhance the dynamic performance. A fast transient response can be achieved without affecting phase estimation accuracy. However, using the filtering stage in the inner loop increased the design complexity.

The work in [79] suggests using a complex NF (CNF) in cascade with MAFs named CNF-QT1-PLL to improve the dynamic performance without effects on the stability and disturbance rejection capability. In this work, the CNF is used for FFNS elimination, while the MAF is used for rejecting other harmonics. A fast transient response and high stability margin can be achieved. However, the implementation complexity still increased.

Compared with type-1 PLLs, type-2 PLLs have a lower stability margin and finite steady-state error in the case of frequency variation. To deal with the type-2 PLL issues, the work in [80] introduces a phase angle error out-loop compensation for type-2 PLL, which removes the phase steady-state error during the frequency changes. The compensation structure contains an adaptive DSC4 operator, acting as an open-loop compensator. This structure increases the stability margin and the dynamic response without affecting the order of the system, in addition to the ease of the LF design. This work is tested in case of frequency variation with voltage dip occurring during the grid fault. So, the adaptive DSC is highly effective in extracting positive sequence components (PSC) and canceling the double-frequency oscillation, and it must be considered. Also, the adaptive DSC4 required both phase and amplitude compensators, increasing the design implementation complexity.

As before, the type-2 PLL fails to track the frequency ramp rate [80]. The type-3 control system was designed in [81] to overcome this issue by utilizing type-2 FLL. To achieve all performances of type-2 and type-3 simultaneously, the phase estimation loop has the dynamics of type-3 control, where the feedback control loop is inherently type-2 control. The dynamic performance of the proposed FLL is good, especially in the case of ramp or sinusoidal frequency variations. However, it suffers from high-frequency noise immunity. A deep comparison between type-2 and type-3 PLLs during ramp-frequency variation is introduced and summarized in [82]. The conventional type-3 PLLs suffer from a slow dynamic response and instability during voltage dips and non-zero steady-state phase error during frequency ramps [83,84,85,86]. In [83], only the phase error during the ramp-frequency variation is considered without enhancing the stability or dynamic performance. However, the work in [87] is extended to address instability and slow dynamics performance utilizing a SOGI-based type-3 PLL with both gain and phase-lead compensations to enhance gain and phase margins, respectively. In [88], a modified notch filter-based type-3 SOGI-PLL (MNF-SOGI-PLL) is introduced where the adaptive frequency removes the phase error without affecting the dynamic performance. The MNF-SOGI-PLL has faster dynamic performance and better grid parameter estimation than a standard type-3 PLL. This structure can effectively suppress the DC offset and subharmonics. However, in the case of voltage sag, the loop gain is reduced, making the system unstable. This required finding the optimal selection of the MNF-SOGI’s gain to ensure a fast dynamics response and stability.

The advantages and issues of using type-3 PLLs are introduced in [89]. It can be concluded that a type-2 PLL has a better dynamic performance than a type-3 PLL during phase and frequency jumps. The opposite is achieved during the frequency ramp or sinusoidal frequency variations. Type-3 has a more oscillatory transient response than type-2 PLLs during grid-faulted, distorted, and unbalanced grid conditions.

Among the QSG-based PLLs, this paper concentrates on the PLLs based on transport delay (TD) in terms of small-signal models (SSMs), control design, and performance. This paper aims to provide a comprehensive review of recent advances in TD-PLLs. All advantages and drawbacks are described for each PLL, and the ability of each PLL to eliminate the DC offset and harmonics is discussed. The tuning method and the SSM used for each PLL structure are reviewed deeply. Although all reviewed PLLs utilize a proportional-integral (PI) as a loop filter, the PI gains are usually designed based on the SSM. Hence, this paper also investigates the large-signal model (LSM)-based design by adopting stochastic optimization. The responses of the optimal gains are compared with the dynamic responses based on the SSM model design in settling time (ST) and percent maximum overshoot (OS). Finally, conclusions and future research directions are given.

2. Transfer Delay PLLs

The transfer delay-PLL (TD-PLL) is the simplest method used in a 1-ϕ system to generate quadrature signals. However, the TD-PLL suffers from a significant problem of its inability to create orthogonal signals when there is a frequency variation. Different works based on TD-PLLs are available in the literature to avoid this issue. Each type of TD-PLL is investigated under different grid disturbances, with particular attention to DC offset mitigation.

2.1. Standard TD-PLL

The work in [90] generates the orthogonal signals in four different combinations (phase differences between them are ∓T/4 or ∓3T/4). All possible combinations are analyzed under different grid disturbances in terms of performance indexes such as settling time, phase, and frequency estimation. The work concluded that the orthogonal signal generated by delaying the original signal by one quarter of the fundamental grid period (T/4) has better immunity against different grid disturbances, faster dynamics, and shorter settling time than 3T/4.

According to the standard TD-PLL block [91] shown in Figure 2a, the TD-PLL input voltage is:

$$v_i\left(t\right)=V\cos \theta ,$$

(1)

where $\theta ={\omega }_{g}t+\phi$ is the grid voltage phase, $V$ is the input voltage amplitude, ${\omega }_g$ is the grid frequency, and $\phi$ is the initial phase.

From Figure 2a, the orthogonal components $v_{\alpha }\left(t\right)$ and $v_{\beta }\left(t\right)$ are defined as follows:

$$v_{\alpha }\left(t\right)=v_i\left(t\right)=V\cos \left(\theta \right)$$

(2)

$$\begin{gathered} v_{\beta }\left(t\right)=v_i\left(t-\frac{T}{4}\right)=V\cos \left(\theta -\frac{{\omega }_{g}T}{4}\right) \\ =V\cos \left(\theta -\frac{\pi }{2}-\frac{∆{\omega }_{g}T}{4}\right)=V\sin \left(\theta -\frac{∆{\omega }_{g}T}{4}\right), \end{gathered}$$

(3)

where ${\omega }_g={\omega }_n+∆{\omega }_g$, ${\omega }_n=2\pi /T$ is the nominal value of grid angular frequency, $T$ is the grid fundamental period, and $∆{\omega }_g$ is the deviation of the grid frequency from its nominal value.

Using Figure 2a and Equations (2) and (3), $v_q\left(t\right)$ is found as follows:

$$\begin{array}{l}{v}_q\left(t\right)=-v_{\alpha }\left(t\right)\sin \left(\widehat{\theta }\right)+v_{\beta }\left(t\right)\cos \left(\widehat{\theta }\right)\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}=\frac{V}{2}\sin \left(\theta -\widehat{\theta }\right)+\frac{V}{2}\sin \left(\theta -\frac{∆{\omega }_{g}T}{4}-\widehat{\theta }\right)-D\left(t\right),\end{array}$$

(4)

where $D\left(t\right)=V\left(\frac{1}{2}\sin \left(\theta +\widehat{\theta }\right)-\frac{1}{2}\sin \left(\theta -\frac{∆{\omega }_{g}T}{4}+\widehat{\theta }\right)\right)$ is the lumped disturbance term and $\widehat{\theta }$ is the estimated phase by the TD-PLL, which is equal to $\widehat{\theta }={\omega }_{n}t+∆\widehat{\theta }$. $D\left(t\right)$ is equal to zero at the lock state.

Substituting the values of $\theta$ and $\widehat{\theta }$ in Equation (4) yields:

$$v_q\left(t\right)=\frac{V}{2}\sin \left(∆\theta -∆\widehat{\theta }\right)+\frac{V}{2}\sin \left(∆\theta -\frac{∆{\omega }_{g}T}{4}-∆\widehat{\theta }\right) -VD\left(t\right)$$

(5)

Under the quasi-locked state, $\sin \left(∆\theta -∆\widehat{\theta }\right)\approx ∆\theta -∆\widehat{\theta }$, $\sin \left(∆\theta -\frac{∆{\omega }_{g}T}{4}-∆\widehat{\theta }\right)\approx \left(∆\theta -\frac{∆{\omega }_{g}T}{4}-∆\widehat{\theta }\right)$. Hence, $v_q\left(t\right)$ can be approximated as follows:

$$v_q\left(t\right)\approx \frac{V}{2}\left(∆\theta -∆\widehat{\theta }\right)+\frac{V}{2}\left(∆\theta -\frac{∆{\omega }_{g}T}{4}-∆\widehat{\theta }\right) -VD\left(t\right)$$

(6)

Taking the Laplace transform of Equation (6) yields:

$$v_q\left(s\right)\approx V\left[\left(\frac{1+e^{-sT/4}}{2}\right)∆\theta -∆\widehat{\theta }-D\left(s\right)\right]$$

(7)

The TD-PLL block diagram is modified, as shown in Figure 3, including phase compensation [91].

Figure 4 shows the phase error for both TD-PLL and compensated TD-PLL under a frequency jump of 10 Hz. As can be seen from the result, the major drawbacks of the TD-PLL are the non-zero phase error and ripple due to frequency variations. The phase mismatch and oscillation are due to the transfer delay not exactly equaling 90°. Although the average phase error is approximately equal to zero using the compensated TD-PLL, the double frequency oscillations still appeared.

2.2. Non-Frequency Dependent TD-PLL (NTD-PLL)

The conventional non-frequency dependent TD-PLL (CNTD-PLL) adopts a second delay, making the TD-PLL immune to grid frequency variations, as shown in Figure 5a. However, much recent research is related to improving the dynamic performance of the NTD-PLL under the presence of a DC offset and harmonic distortion in the grid voltage, as shown in Figure 5b–d and summarized in references [35,91,92,93,94].

The work in [91] proposes the NTD-PLL, as shown in Figure 5a, where fixed time delay operators are used. The SSM of the NTD-PLL is derived using the block diagram in Figure 5a in addition to Equations (2) and (3). The input signal of the PI controller is the $v_q\left(t\right)$, which is found as follows:

$$v_q\left(t\right)=-v_{\alpha }\left(t\right)\sin \left(\widehat{\theta }\right)+v_{\beta }\left(t\right)\sin \left(\widehat{\theta }-\frac{{\widehat{\omega }}_{g}T}{4}\right)$$

(8)

This can be simplified to:

$$\begin{array}{l}{v}_q\left(t\right)=\frac{ V}{2}\sin \left(\theta -\widehat{\theta }\right)+\frac{V}{2}\sin \left(\left(\theta -\frac{{\omega }_{g}T}{4}\right)-\left(\widehat{\theta }-\frac{{\widehat{\omega }}_{g}T}{4} \right)\right)-\frac{V}{2}\underset{D\left(t\right)}{\underbrace{\sin \left(\theta +\widehat{\theta }\right)}}-\frac{V}{2} \\ \underset{D\left(t-\frac{T}{4}\right)}{\underbrace{\sin \left(\theta -\frac{{\omega }_{g}T}{4}+\widehat{\theta }-\frac{{\widehat{\omega }}_{g}T}{4}\right)}}\end{array}$$

(9)

Equation (9) is approximated under a quasi-locked state as:

$$v_q\left(t\right)\approx \frac{ V}{2}\left[\left(\theta -\widehat{\theta }\right)+\left(\theta -\frac{{\omega }_{g}T}{4}\right)-\left(\widehat{\theta }-\frac{{\widehat{\omega }}_{g}T}{4} \right)-D\left(t\right)-D\left(t-\frac{T}{4}\right)\right]$$

(10)

Taking the Laplace transform to Equation (10) yields:

$$v_q\left(s\right)\approx V\left(\frac{1+e^{-sT/4}}{2}\right)\left[∆\theta -∆\widehat{\theta }-D\left(s\right)\right]$$

(11)

Hence, the SSM of NTD-PLL is obtained using Equation (11) as in Figure 5a. The open-loop transfer function of the NTD-PLL is found assuming $D\left(s\right)=0$ as:

$$G_{ol}\left(s\right)=\frac{∆\widehat{\theta }}{∆\widehat{\theta }-∆\theta } =V\left(\frac{1+e^{-sT/4}}{2}\right)\left(\frac{k_{p}s+ki}{s^2} \right)$$

(12)

By replacing the delay in Equation (12) with the first order Padѐ approximation yields:

$$G_{ol}\left(s\right)=V\left(\frac{k_{p}s+k_i}{s^2} \right)\left(\frac{1}{\left(T/8\right)s+1}\right)$$

(13)

Using the symmetrical optimum method (SOM) with the desired phase margin (PM), which is equal to 45$°$, $k_p$ and $k_i$ can be obtained as $k_p$ = 166, and $k_i$ = 11,371 [91]. The CNTD-PLL has a limitation under frequency variation, yielding phase error and double-frequency oscillations.

The work in [92] modifies the NTD-PLL by utilizing dual independent control loops to enhance the NTD-PLL speed and accuracy capability and improve the dynamic response of NTD-PLL by considering the optimal delay length selection for both delay operators.

Based on Figure 5b, the dq-transformation matrix is found as follows:

$$\left[\begin{array}{c}{v}_d\left(t\right)\\ v_q\left(t\right)\end{array}\right]=\left[\begin{array}{cc}\mathrm{c}\mathrm{o}\mathrm{s} \left({\widehat{\omega }}_g\left(t-T_d\right)\right)& -\mathrm{c}\mathrm{o}\mathrm{s} \left({\widehat{\omega }}_{g}t\right)\\ -\mathrm{s}\mathrm{i}\mathrm{n} \left({\widehat{\omega }}_g\left(t-T_d\right)\right)& \mathrm{s}\mathrm{i}\mathrm{n} \left({\widehat{\omega }}_{g}t\right)\end{array}\right]\left[\begin{array}{c}{v}_{\alpha }\left(t\right)\\ v_{\beta }\left(t\right)\end{array}\right],$$

(14)

where $\left[\begin{array}{c}{v}_{\alpha }\left(t\right)\\ v_{\beta }\left(t\right)\end{array}\right]=\left[\begin{array}{c}V\sin \left({\omega }_{g}t\right)\\ V\sin \left({\omega }_g\left(t-T_d\right)\right)\end{array}\right]$. Using Equation (14), the input signal of the modified NTD-PLL (MTD-PLL) PI controller is the $v_q\left(t\right)$, which is found as follows:

$$\begin{gathered} v_q\left(t\right)=\frac{V}{2}\left[-\cos \left(\left(∆\widehat{\theta }-∆{\widehat{\omega }}_g{T}_d\right)-∆\theta -{\omega }_n{T}_d\right)+\cos \left(\left(∆\theta -∆{\omega }_g{T}_d\right)-∆\widehat{\theta } \\ -{\omega }_n{T}_d\right)\right]+\frac{V}{2}D\left(t\right), \end{gathered}$$

(15)

where $D\left(t\right)$ is the double frequency term and it is equal to $(∆{\widehat{\omega }}_g-∆{\omega }_g)T_d\mathrm{s}\mathrm{i}\mathrm{n} (\theta +\widehat{\theta }-{\omega }_n{T}_d)$.

By defining $\mathrm{\varnothing }={\omega }_n{T}_d$ and applying trigonometric identities, Equation (15) is simplified to:

$$v_q\left(t\right)=\frac{V{k}_s}{2}\left({\theta }_2-{\theta }_1\right)+d_{hf}\left(t\right),$$

(16)

where $k_s=\mathrm{s}\mathrm{i}\mathrm{n} \left(\mathrm{\varnothing }\right)$, ${\theta }_1=\left(∆\widehat{\theta }-∆{\widehat{\omega }}_g{T}_d\right)-∆\theta$, ${\theta }_2=\left(∆\theta -∆{\omega }_g{T}_d\right)-∆\widehat{\theta }$, and $d_{hf}\left(t\right)=\frac{V}{2}D\left(t\right)$.

Taking the Laplace transform to Equation (16) yields:

$$v_q\left(s\right)=V{k}_s\left(\frac{1+e^{-s{T}_d}}{2}\right)\left[∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)\right]+d_{hf}\left(s\right)$$

(17)

Hence, the SSM of the MNTD-PLL is obtained using Equation (17) as in Figure 5b. Based on Figure 5b, the open-loop transfer function $G_{ol}\left(s\right)$ founds as follows:

$$G_{ol}\left(s\right)=\frac{V{k}_s(k_{p}s+k_i)}{s^2}\left(\frac{1+e^{-s{T}_d}}{2}\right)$$

(18)

Equation (18) can be simplified, approximating the delay term using first-order Padѐ approximation as follows:

$$G_{ol}\left(s\right)\cong \frac{k_{is}\left(T_{i}s+1\right)}{s^2\left({\acute{T}}_{d}s+1\right)},$$

(19)

where $k_{is}=k_s{k}_i$, $k_{ps}=k_s{k}_p$, $T_i=k_p/k_i$, ${\acute{T}}_d=T_d/2$, and $V=1$ pu.

Since the closed-loop transfer function is third order, the SOM is used to find the PI controller values as in [35,91,96]:

$$\left\{\begin{array}{c}{\omega }_c=\frac{1}{T_i\sqrt{{\acute{T}}_d}}\\ T_i=b^2{\acute{T}}_d\\ k_{is}=\frac{1}{b^3{ {\acute{T}}_d}^2}\\ k_{ps}=\frac{1}{b{\acute{T}}_d}\end{array}\right\},$$

(20)

where $T_i$ is the time constant of the controller, ${\acute{T}}_d$ is half of the selected time delay, and $b$ specifies the phase margin (PM), ${\mathrm{\varnothing }}_{PM}={\mathrm{t}\mathrm{a}\mathrm{n}}^{-1}\left(\frac{b^2-1}{2b}\right)$, the recommended value of ${\mathrm{\varnothing }}_{PM}=45°$.

The MNTD-PLL utilizes two-loop PLLs with different structures to extract phase and frequency information from each. The delay with the best dynamic performance response at each sample period is used to find a single time delay, providing an optimum solution to minimize overshoot and reduce settling time. Although this method is one of the simplest and fastest solutions to the oscillation error in estimated grid information under frequency variation, it is susceptible to grid voltage disturbances, such as DC offsets and harmonics.

Another modification for the conventional NTD-PLL structure is proposed in [93], as shown in Figure 5c, to mitigate the effect of DC offsets and harmonics with a fast dynamic response and accurate grid information. These modifications are conducted by adopting an in-loop moving average filter (MAF) cascaded with the digital phase lead compensator (PLC) integrated into the NTD-PLL (MPNP). Also, it is referred to as the modified version of a digital comb filter. The comb filter is designed to be adaptive to stand for any variation in grid frequency. The combination of MAF and PLC provides unity gain at low frequency and a near-zero phase shift. The window length is selected to be one grid cycle to remove all types of disturbance.

In Figure 5c, the CNTD-PLL was modified to achieve operational robustness against abnormal grid conditions by adding the moving average filter (MAF) in a loop. When the window period ${(T}_w)$ is selected equal to the nominal fundamental grid period ${(T}_N)$ all disturbances can be eliminated. The transfer function of MAF in the s-domain can be written as:

$$G_{\mathrm{M}\mathrm{A}\mathrm{F}}=\frac{1-e^{-T_{w}s}}{T_{w}s}$$

(21)

MAF can be approximated using first-order Padѐ approximation. The approximation is equivalent to the low pass filter as in Equation (22):

$$G_{\mathrm{M}\mathrm{A}\mathrm{F}}=\frac{1}{1+s(T_w/2)}$$

(22)

The filtering stage using MAF inside the PLL control loop introduces a large phase delay that reduces the PLL control bandwidth and makes the PLL dynamic response slow. The digital PLC is added in cascade with the MAF inside the PLL control loop to improve the transient response while maintaining the filtering capacity. This method introduces zero poles closer to zero locations of the MAF at the same frequency. The digital implementations for the transfer functions for the PLC and MAF are given in Equation (23). It can be noted that the PLC’s transfer function is the inverse of the MAF’s transfer function, where $r$ and $N$ are the attenuation factor of MAF and the number of samples in one MAF window period, respectively:

$$\left\{\begin{array}{c}{G}_{\mathrm{M}\mathrm{A}\mathrm{F}}\left(z\right)=\frac{1}{N}\frac{1-z^{-N}}{1-z^{-1}}\\ G_{\mathrm{P}\mathrm{L}\mathrm{C}}\left(z\right)=\frac{1-r^N}{1-r}\frac{1-{r.z}^{-1}}{1-{(r.z^{-1})}^N}\end{array}\right.$$

(23)

Based on Equation (14) and assuming $T_d=T/4$, the input signal of the RNTD-PLL PI controller is the $v_q\left(t\right)$, which is found as follows:

$$v_q\left(t\right)=-V\sin \left(\widehat{\theta }-{\widehat{\omega }}_g\frac{T}{4}\right)\sin \left(\theta \right)+V\sin \left(\widehat{\theta }\right)\sin \left(\theta -{\omega }_g\frac{T}{4}\right)$$

(24)

The sin terms in Equation (24) are replaced by its small angle approximation as follows:

$$v_q\left(t\right)=\frac{V}{2}\left[\sin \left(∆\theta -(∆\widehat{\theta }-∆{\widehat{\omega }}_g\frac{T}{4}\right)\right)-\mathrm{s}\mathrm{i}\mathrm{n} \left(∆\widehat{\theta }-\left(∆\theta -∆{\omega }_g\frac{T}{4}\right)\right)]+\frac{V}{2}{D}_h(t)$$

(25)

Taking Laplace transform to the Equation (25);

$$v_q\left(s\right)=V\left(\frac{1+e^{-s(T/4) }}{2}\right)\left[∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)\right]+D_h\left(s\right)$$

(26)

The linearized model of MAF-NTD-PLL ignoring the effect of PLC is shown in Figure 5c. The PI controller gains are found based on the open-loop transfer function for NTD-PLL cascaded with MAF and PLC as follows:

$${\acute{G}}_{ol}\left(s\right)=G_{\mathrm{M}\mathrm{A}\mathrm{F}}\left(s\right)G_{\mathrm{P}\mathrm{L}\mathrm{C}}\left(s\right)G_{ol}\left(s\right)$$

(27)

The open-loop transfer function can be rewritten as follows where $T_i=k_p/k_i:$

$${\acute{G}}_{ol}\left(s\right)=\frac{k_i(T_{i}s+1)}{s^2(\left(T/8\right)s+1)}$$

(28)

The PI controller parameters are designed using the symmetrical optimum method depending on the values of b, which is related to the PM [35,91,94] as mentioned in Equation (20). A tradeoff between the selection of crossover frequency and the phase margin (PM) is proposed in [93], which gives the following recommendations: PM = 43$°$, b = 2.3, and $T_d=T/4$. This selection gives $k_p=138$ and $k_i=6600$.

The modification of the CNTD-PLL in [95] aims to solve the double-frequency oscillatory errors during the frequency variations by modifying the Park transformation matrix (TM) without increasing complexity in the design. The accuracy of the derived model is improved using the linear time-periodic (LTP) framework. The modification to the CNTD-PLL and its linear time-invariant (LTI) model are shown in Figure 5d. The TM used in Equation (14) is modified by directly generating the $\cos \left(\widehat{\theta }\right)$ and indirectly generating the $\sin \left(\widehat{\theta }\right)$ by delaying the $\cos \left(\widehat{\theta }\right)$ by $T_d=T/4$. The modified Park TM $R_{mPT}\left(\widehat{\theta }\right)$ is given as shown in Equation (29).

$$R_{mPT}\left(\widehat{\theta }\right)=\left[\begin{array}{cc}\cos \left(\widehat{\theta }\right)& \sin (\widehat{\theta }-∆{\widehat{\omega }}_g(T/4\left)\right) \\ -\sin (\widehat{\theta }-∆{\widehat{\omega }}_g(T/4\left)\right) & \cos \left(\widehat{\theta }\right)\end{array}\right]$$

(29)

The voltage in $dq$ reference frame is found as in Equation (30):

$${\left[\begin{array}{cc}{v}_d\left(t\right)& v_q\left(t\right)\end{array}\right]}^T=R_{mPT}\left(\widehat{\theta }\right) {\left[\begin{array}{cc}{v}_{\alpha }\left(t\right)& v_{\beta }\left(t\right)\end{array}\right]}^T$$

(30)

By modifying the Park TM, it is noted that the double-frequency oscillatory errors $d_{hf}\left(s\right)$ in Equation (17) disappear. The input signal of the modified NTD-PLL PI controller in the s-domain is the $v_q\left(s\right)$, which is found as follows:

$$v_q\left(s\right)=V\left(\frac{1+e^{-s(T/4) }}{2}\right)\left[∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)\right],$$

(31)

By using the same design procedures in Equations (18)–(20), $k_p$ and $k_i$ are selected to be 166 and 11,371, respectively. Also, ref. [95] suggests using the LTP model rather than the LTI model. The LTP model accurately detects the estimated values of phase, frequency, and amplitude under different grid disturbances and solves the double frequency error under a frequency variation without imposing any computational burden on the system. However, the LTP model does not predict the oscillatory response when the DC offset and harmonic disturbances are presented in the grid.

In Figure 6, the CNTD-PLL, MNTD-PLL, and MPNP are tested under a frequency jump of 10Hz that occurs at 0.1 s. The phase error under grid frequency variation is solved in MNTD-PLL and MPNP. The phase error of the MPNP is higher than in CNTD- and MNTD-based PLLs. However, the frequency settling time of the MPNP is less, with zero peak frequency. Comparing these three types, the MPNP performs best under frequency variations. Furthermore, the improvements in the mNTD-PLL can be seen in Figure 6, where the double frequency oscillations in the estimated phase and frequency are obliterated compared with the CNTD-PLL. However, the double-frequency oscillation rejection in the estimated grid voltage ($\widehat{V}$) is poor, as shown in Figure 7.

The work in [97] is introduced to alleviate the offset and double-frequency oscillation errors that appeared in the estimated amplitude in the mNTD-PLL during the frequency variation. A truly NTD-PLL structure (tNTD-PLL) is proposed by modifying the CNTD-PLL by adding another fixed T/4 TD operator in the Park TM of the CNTD-PLL, as shown in Figure 8. Compared with NTD-PLL, these modifications perfectly remove the double frequency oscillation errors from all estimation parameters of the grid and make them not dependent on the frequency variation, especially from the amplitude point of view, as shown in Figure 9.

In [98], a comparative study of standard and digital phase lead compensators (PLCs) was conducted. The general block diagram is shown in Figure 10. These PLCs minimize the phase delay of in-loop filters and boost the PLL’s bandwidth to maintain an acceptable phase margin for the PLL’s stability. The comparisons are evaluated from their dynamic performances, steady state accuracy, frequency adaptive, and computational burden. The results of comparing the modified digital PLC NTD-PLL (MDNPLL) and modified standard PLC NTD-PLL (MSNPLL) are summarized as follows: MDNPLL’s transient response is slightly faster than MSNPLL, and both have similar steady-state accuracy. Both PLLs accurately track the grid information parameters under different disturbances, especially the DC offset and harmonics distortion. However, comparing the digital PLC with the standard PLC, the digital PLC requires a higher processing time and computational burden.

The work in [99] concerns a systematic design approach for the loop filter tuning of standard TD-PLL and CNTD-PLL. The optimal control effort is presented in this work based on the modern optimal control theory, which is the linear quadratic regulator (LQR). The optimal controller setting is found based on the specific weighting matrix selections of LQR. The LQR tuning method is compared with well-known tuning methods such as time-domain and IAE/ISE based on standard TD-PLL and with a symmetrical optimum method (SO) for CNTD-PLL. The comparisons indicated that the LQR-based tuning method achieved a faster dynamic response without overshoot and phase offset. Also, the disturbance rejection capability is improved compared to other available tuning methods, with minimal control effort requirements during grid synchronization. The method in [100] modified the standard TD-PLL by using two delay blocks rather than one delay block, as shown in Figure 11, to improve the dynamic performance when harmonics or sag/swell disturbances pollute the grid voltage. Compared with standard TD-PLL, this work has less computational complexity.

From Figure 11, the filter input ${\stackrel{ˎ}{v}}_q(t)$ is given as follows:

$${\stackrel{ˎ}{v}}_q\left(t\right)=2V_{im}\left(t-\tau \right)+V_{im}\left(t\right)+V_{im}\left(t-2\tau \right),$$

(32)

where $V_{im}\left(t\right)=-\frac{v_i\left(t\right)}{2}\sin \left(\widehat{\theta }\right)$ and $v_i\left(t\right)=\cos \left(\theta \right)$.

The approximated closed-loop transfer function can be represented as in (33), where the $D\left(s\right)$ represent the second-order function:

$$\frac{\stackrel{ˎ}{\widehat{\omega }}(s)}{\omega \left(s\right)}=\frac{\left(1/16\right)D\left(s\right)(k_{p}s+k_i){\omega }_f}{s^3+{\omega }_f{s}^2+\left(1/16\right)\left({\omega }_f{k}_{p}s+{\omega }_f{k}_i\right)D\left(s\right)}$$

(33)

From Equation (33), it is easy to see that the PLL poles can be selected by tuning the parameter of the PI controller ($k_p,k_i)$ and the cutoff frequency of the lowpass filter ${\omega }_f$. The ${\omega }_f$ value is selected based on the expected noise and harmonics in the system. In Figure 12, the effectiveness of this modification is tested under a +10 Hz frequency jump at 0.02 s and compared with the standard TD-PLL. The results show that this modification improves the dynamic response and removes the phase offset and the double frequency oscillation errors. Besides this, the frequency settling time of this modification is faster than in the standard TD-PLL. However, its peak phase error is larger than the standard TD-PLL.

2.3. Enhanced Time Delay PLL (ETD-PLL)

The standard TD-PLL is modified utilizing αβ-frame delayed signal cancellation operator with a delay factor equal $T/4$. This operator is called αβDSC₄, as in Figure 13a. The double frequency problem is solved using two cascade αβDSC₄ operators. Also, the phase correction and harmonic filtering capacity are improved using additional αβDSC operators. This PLL is called enhanced TD-PLL (ETD-PLL). The phase error compensator gain $k_{\mathrm{\varnothing }}$ is equal to $\frac{11T}{32}$ is used to correct the estimated phase error as calculated in (34) [91].

$$k_{\varnothing }=\angle \left\{{\left[\alpha \beta DS{C}_4\left(j{\omega }_g\right)\right]}^2\alpha \beta DS{C}_8\left(j{\omega }_g\right)\alpha \beta DS{C}_{16}\left(j{\omega }_g\right)\right\}=-\frac{11T}{32} ∆{\omega }_g,$$

(34)

The SSM of the ETD-PLL is shown in Figure 13b. The open-loop and the closed-loop transfer functions are found as:

$$G_{ol}\left(s\right)=\frac{∆{\widehat{\theta }}_c}{∆\theta -∆{\widehat{\theta }}_c}=\frac{V[\left(k_p+k_i{k}_{\varnothing }\right)s+k_i]}{s(s-V{k}_i{k}_{\varnothing })},$$

(35)

$$G_{cl}\left(s\right)=\frac{∆{\widehat{\theta }}_c}{∆\theta }=G_1\left(s\right)G_2\left(s\right),$$

(36)

where $G_1\left(s\right)=\frac{1}{16}{\left(1+e^{-\left(\frac{T}{4}\right)s}\right)}^2\left(1+e^{-\left(\frac{T}{8}\right)s}\right)\left(1+e^{-\left(\frac{T}{16}\right)s}\right)$ and $G_2\left(s\right)=\frac{V[\left(k_p+k_i{k}_{\mathrm{\varnothing }}\right)s+k_i]}{s^2+V{k}_{p}s+V{k}_i}$.

The ETD-PLL’s dynamic performance is checked under a +20° jump in phase magnitude and 10 Hz jump in the frequency, as in Figure 14. Although the double frequency oscillation is reduced using the ETD-PLL, oscillations are still under grid frequency variation, as shown in Figure 14.

2.4. Adaptive Time Delay PLL (ATD-PLL)

The adaptive TD-PLL (ATD-PLL), introduced in [101], is the modified version of the TD-PLL using a fixed-length quarter cycle delay to generate the quadrature signal and frequency feedback to handle gird frequency variation. The ATD-PLL is shown in Figure 15a. The computational burden is reduced, approximating the trigonometric terms $\mathrm{s}\mathrm{i}\mathrm{n} \left(\vartheta \right)$ and $\mathrm{c}\mathrm{o}\mathrm{s} \left(\vartheta \right)$ by the first two terms of their Taylor series expansions as in [101]. From Figure 15a, it is easy to define $v_{\alpha }\left(t\right)$ and $v_{\beta }\left(t\right)$ as follows:

$$v_{\alpha }\left(t\right)=v_i\left(t\right)=V\cos \left(\theta \right),$$

(37)

$$v_{\beta }\left(t\right)=v_i\left(t-\frac{T}{4}\right)=Vsin\left(\theta -\frac{∆{\omega }_{g}T}{4}\right)$$

(38)

Applying trigonometric identities to (38) yields:

$$v_{\beta }\left(t\right)=V\sin \left(\theta \right)\cos \left(\frac{∆{\omega }_{g}T}{4}\right)-V\cos \left(\theta \right)\sin \left(\frac{∆{\omega }_{g}T}{4}\right)$$

(39)

Let $\stackrel{ˎ}{v_{\beta }}\left(t\right)=V\sin \left(\theta \right),$ then:

$$v_{\beta }\left(t\right)=\stackrel{ˎ}{v_{\beta } }(t)\cos \left(\frac{∆{\omega }_{g}T}{4}\right)-v_{\alpha }(t)\sin \left(\frac{∆{\omega }_{g}T}{4}\right)$$

(40)

From Equation (41), $\stackrel{ˎ}{v_{\beta }}\left(t\right)$ can be expressed in terms of $v_{\beta }\left(t\right)$ and $v_{\alpha }\left(t\right)$ as follows:

$$\stackrel{ˎ}{v_{\beta } }\left(t\right)=\frac{v_{\beta }\left(t\right)+v_{\alpha }(t)\sin \left(\frac{∆{\omega }_{g}T}{4}\right)}{\cos \left(\frac{∆{\omega }_{g}T}{4}\right)}$$

(41)

The generation of $\stackrel{ˎ}{v_{\beta }}(t)$ needs the knowledge of grid frequency variation ${∆\omega }_g$. Therefore, the output signal from the integrator of the PI controller $∆{\widehat{\omega }}_g$ gives a good estimation of ${∆\omega }_g$. Therefore, Equation (41) can be rewritten in terms of $∆{\widehat{\omega }}_g$ by substituting Equations (37) and (38) into Equation (41), which yields:

$$\stackrel{ˎ}{v_{\beta } }\left(t\right)=\frac{V\sin \left(\theta -\frac{∆{\omega }_{g}T}{4}\right)+V\cos \left(\theta \right)\sin \left(\frac{∆{\widehat{\omega }}_{g}T}{4}\right)}{\cos \left(\frac{∆{\widehat{\omega }}_{g}T}{4}\right)}$$

(42)

From Figure 15b, the PI controller input signal $v_q\left(t\right)$ is:

$$\begin{gathered} v_q\left(t\right)=-v_{\alpha }\left(t\right)\sin \left(\widehat{\theta }\right)+\stackrel{ˎ}{v_{\beta } }\left(t\right)\mathit{cos} \left(\widehat{\theta }\right), \\ {v}_q\left(t\right)=\frac{V}{2}\left[\mathit{sin} \left(\theta -\widehat{\theta }\right)+\mathit{tan} \left(\frac{∆{\widehat{\omega }}_{g}T}{4}\right)\mathit{cos} \left(\theta -\widehat{\theta }\right)+\frac{\mathit{sin} \left(\theta -\widehat{\theta }-\frac{∆{\omega }_{g}T}{4}\right)}{\mathit{cos} \left(\frac{∆{\widehat{\omega }}_{g}T}{4}\right)}\right]+D\left(t\right), \end{gathered}$$

(43)

$$D\left(t\right)=\frac{V}{2}\left[-\sin \left(\theta -\widehat{\theta }\right)+\tan \left(\frac{∆{\widehat{\omega }}_{g}T}{4}\right)\cos \left(\theta -\widehat{\theta }\right)+\frac{\sin \left(\theta -\widehat{\theta }-\frac{∆{\omega }_{g}T}{4}\right)}{\cos \left(\frac{∆{\widehat{\omega }}_{g}T}{4}\right)}\right],$$

(44)

where $D\left(t\right)$ is the lumped disturbance term, and it is equal to zero when the estimated grid frequency equals the actual grid frequency (frequency-locked state).

To derive the SSM of ATD-PLL, the following approximations are considered. $\sin \left(\theta -\widehat{\theta }\right)\approx \left(\theta -\widehat{\theta }\right)\approx \left(∆\theta -∆\widehat{\theta }\right),\cos \left(\theta -\widehat{\theta }\right)\approx 1,\tan \left(\frac{∆{\widehat{\omega }}_{g}T}{4}\right)\approx \frac{∆{\widehat{\omega }}_{g}T}{4}$, $\cos \left(\frac{∆{\widehat{\omega }}_{g}T}{4}\right)\approx 1,$ and $\sin \left(\theta -\widehat{\theta }-\frac{∆{\omega }_{g}T}{4}\right)\approx \theta -\widehat{\theta }-\frac{∆{\omega }_{g}T}{4}\approx ∆\theta -∆\widehat{\theta }-\frac{∆{\omega }_{g}T}{4}$. Therefore, $v_q\left(t\right)$ is simplified to:

$$v_q\left(t\right)=V\left[\frac{∆{\widehat{\omega }}_{g}T}{8}-∆\widehat{\theta }+\frac{∆\theta +\left(∆\theta -\frac{∆{\omega }_{g}T}{4}\right)}{2}\right]$$

(45)

Taking Laplace transform for Equation (45), yields:

$$v_q\left(s\right)=V\left[\frac{∆{\widehat{\omega }}_g(s)T}{8}-∆\widehat{\theta }(s)+\frac{1+e^{\frac{-T}{4}s}}{2}∆\theta (s)\right]$$

(46)

Based on Equation (46) and Figure 15a, the SSM of the ATD-PLL is shown in Figure 15b. From the SSM, the closed-loop transfer function is found as follows:

$$G_{ol}\left(s\right)=\frac{1+e^{\frac{-T}{4}s}}{2}\left[\frac{V{k}_{p}s+V{k}_i}{s^2+V\left(k_p-\frac{k_{i}T}{8}\right)s+V{k}_i}\right]$$

(47)

The PI controller gains are selected following the guidelines of [101], which yields $k_p=217$ and $k_i=\mathrm{15,791}.$ Figure 16 shows the response of the actual ATD-PLL under +${20}^{°}$ phase jump and 10 Hz frequency jump. The double frequency oscillation is entirely removed using ATD-PLL rather than using ETD-PLL or NTD-PLL when there is a grid frequency variation, as shown in Figure 16. Besides, the ATD-PLL has a simpler structure than ETD-PLL since it uses fixed transfer delay, and there is no need to use the αβ-DSC operators to remove the double frequency oscillation.

Many available linear time-invariant (LTI) models of TD-based PLLs depend on assumptions such as neglecting amplitude variation and double-frequency oscillation, which affect the system’s accuracy. To alleviate this issue, the linear time periodic (LTP) model is presented [102]. The ATD-PLL is taken as a case study. The LTP model of the ATD-PLL is derived and compared with its LTI model. From the summary of the comparison, the LTP models provide much higher accuracy through the ability to predict the transient state when there is a disturbance in the grid information parameters and damped double-frequency error oscillation. However, the LTP provides the cost of higher model complexity. In addition, the LTP model of the ATD-PLL has two limitations: the LTP’s accuracy drops with increasing the magnitude of input voltage (sag/swell), and it neglects the presence of harmonic components, which results in some ripples in the estimated phase and frequency.

2.5. Variable Length Time Delay PLL (VLTD-PLL)

The variable-length time delay (VLTD)-PLL is introduced in [103], as shown in Figure 17, using a variable-length transfer delay adjusted according to the estimated grid frequency. The length of transfer delay is selected to be variable to avoid the frequency variations problem. However, there are some double-frequency oscillations in the transient response of the VLTD-PLL, that the model cannot predict, due to the neglecting of the double-frequency terms in the modeling stage. However, the settling time is improved, and harmonic filtering capacity is enhanced by employing the VLTD-PLL.

From Figure 17a, $v_{\alpha }\left(t\right)$ and $v_{\beta }\left(t\right)$ are given by:

$$\begin{gathered} v_{\alpha }\left(t\right)=v_i\left(t\right)=Vcos\left(\theta \right), \\ {v}_{\beta }\left(t\right)=v_i\left(t-\frac{\overline{T}}{4}\right)=Vcos\left(\theta -\frac{{\omega }_g\overline{T}}{4}\right), \end{gathered}$$

(48)

where $\left(\overline{}\right)$ is the filtered version of the estimated signal, i.e., $\overline{T}$ is the filtered version of the estimated grid period. By defining ${\omega }_g={\omega }_n+∆{\omega }_g$, ${\overline{\omega }}_g={\omega }_n+∆{\overline{\omega }}_g$ and the non-linear term $\frac{{\omega }_g\overline{T}}{4}$ is simplified using Taylor series expansion as:

$$\frac{{\omega }_g\overline{T}}{4}=\frac{\pi }{2}+\frac{T}{4}∆{\omega }_g-\frac{T}{4}∆{\overline{\omega }}_g$$

(49)

Based on Figure 17a, the PI controller input signal $v_q\left(t\right)$ is:

$$v_q\left(t\right)=-v_{\alpha }\left(t\right)\mathit{sin} \left(\widehat{\theta }\right)+v_{\beta }\left(t\right)\mathit{cos} \left(\widehat{\theta }\right)$$

(50)

Substituting Equations (48) and (49) in (30) yields:

$$v_q\left(t\right)=\frac{V}{2}\left[\mathit{sin} \left(\theta -\widehat{\theta }\right)+\mathit{sin} \left(\theta -\widehat{\theta }-\frac{T}{4}\left[∆{\omega }_g-∆{\overline{\omega }}_g\right]\right)\right]+D\left(t\right),$$

(51)

where $D\left(t\right)=-\sin \left(\theta +\widehat{\theta }\right)+\sin \left(\theta +\widehat{\theta }-\frac{T}{4}\left[∆{\omega }_g-∆{\overline{\omega }}_g\right]\right)$ is equal to zero by assuming that $∆{\omega }_g\approx ∆{\overline{\omega }}_g.v_q\left(t\right)$ can be approximated as in Equation (52) since $\sin \left(\theta -\widehat{\theta }\right)\approx \left(∆\theta -∆\widehat{\theta }\right)$ and $\sin \left(\theta -\widehat{\theta }-\frac{T}{4}\left[∆{\omega }_g-∆{\overline{\omega }}_g\right]\right)\approx ∆\theta -∆\widehat{\theta }-\frac{T}{4}\left[∆{\omega }_g-∆{\overline{\omega }}_g\right]$, and

$$v_q\left(t\right)=V\left[\frac{∆\theta +∆\theta -\frac{T}{4}∆{\omega }_g}{2}-∆\widehat{\theta }+\frac{T}{8}∆{\overline{\omega }}_g\right]$$

(52)

Applying the Laplace transform to the Equation (52), yields:

$$v_q\left(s\right)\approx V\left[\frac{1+e^{\frac{-T}{4}S}}{2}∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)+\frac{T}{8}∆{\overline{\omega }}_g\left(s\right)\right]$$

(53)

From Equation (49) and Figure 17a, the SSM is plotted in Figure 17b. The lowpass filter (LPF) introduced in the feedback loop has a time constant of $T_d=k_p/k_i$ to cancel the effect of the unwanted zero. The PI controller gains are $k_p=217,k_i=15791$ as given in [103].

The work in [104] utilizes the arbitrary delay signal cancelation (ADSC) that is not restricted to a specific time delay, with a variable length time delay (VLTD)-based PLL to remove the DC offset from the 1-$\varphi$ system. This gives flexibility and advantages over other PLLs that use DSC operators at a specific time delay. Figure 18 shows the ADSC with VLTD-PLL.

The grid voltage is subtracted from the delayed version to remove the DC offset. As using the ADSC operator caused an error in the estimated phase, a phase correction of ($\frac{-{\widehat{\omega }}_g\tau }{2}$) and a scaling factor of $2\sin \left(\frac{{\widehat{\omega }}_g\tau }{2}\right)$ is introduced to overcome these issues. In small-signal modeling and near synchronization $V_q\left(t\right)$ can be obtained as:

$$v_q=2V\sin \left(\frac{{\omega }_n\tau }{2}\right)\left[\frac{∆\theta +∆\theta -∆{\omega }_g\left(\tau +\frac{T}{4}\right)}{2}-∆\widehat{\theta }+\frac{∆{\widehat{\omega }}_g\left(\tau +\frac{T}{4}\right)}{2}\right]$$

(54)

Taking Laplace transform to Equation (54):

$$v_q\left(s\right)=k_v\left[ \frac{1+e^{-\left(\tau +\frac{T}{4}\right)s}}{2}∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)+\frac{\tau }{2}∆{\widehat{\omega }}_g\left(s\right)+\frac{T}{8}∆{\widehat{\omega }}_g\left(s\right)\right],$$

(55)

where $k_v=2Vsin\left(\frac{{\omega }_n\tau }{2}\right)$ is the scaling factor.

The SSM of the ADSC with VLTD-PLL is shown in Figure 18b using Equation (54). From the SSM in Figure 18b, the closed-loop transfer function can be obtained as:

$$\frac{∆\widehat{\theta }}{∆\theta }=\frac{1+e^{-\left(\tau +\frac{T}{4}\right)s}}{2} \frac{k_v(k_{p}s+k_i)}{s^2+k_v\left(k_p-k_i\left(\frac{4\tau +T}{8}\right)\right)+k_v{k}_i},$$

(56)

which is stable if $k_i>0$ and $k_p>k_i\left(\frac{4\tau +T}{8}\right)$, knowing that $k_v>0$ by a proper selection of $\tau$.

From the closed-loop transfer function in Equation (56), the PI controller gains are designed based on the desired characteristic equation, which is found as: $k_p=\frac{2\zeta \omega }{k_v}+k_i\left(\frac{4\tau +T}{8}\right)$ and $k_i=\frac{{\omega }^2}{k_v}$. Referring to [104], the controller gains were found as $k_p=376.98$, $k_i=25551,$ and $k_v=0.618$. The actual responses of the VLTD-PLL and ADSC with VLTD-PLL due to the 20$°$ phase jump and 10 Hz frequency jump occurring at 0.02 s and 0.1 s are shown in Figure 19. The response of the VLTD is almost close to the response of ATD-PLL. However, the ATD-PLL is better than VLTD-PLL since it uses fixed transfer delay. Nevertheless, if the accuracy is of interest, the VLTD-PLL has the advantage over the ATD-PLL, especially when the system suffers from high-frequency variations. The VLTD-PLL cannot eliminate the effect of the DC offset on the grid. Moreover, the estimated phase response of ADSC with VLTD-PLL under a frequency step of 10 Hz is suppressed in two grid cycles. The ADSC with VLTD-PLL solves the VLTD-PLL’s limitation in DC offset rejection.

2.6. Enhanced PLL-Based Moving Average Filter or a Finite Impulse Response Filter

The work in [79] is based on a finite impulse response filter (FIR-EPLL) for harmonic and DC offset filtration. The FIR-EPLL was compared to different PLL approaches regarding their ability to remove the DC offset, harmonic filtration, and performance accuracy.

The MAF-EPLL, shown in Figure 20, is very popular in designing advanced synchronization systems. It completely blocks all frequency components with a frequency integer multiple of the inverse of the MAF window. Nevertheless, the MAF passes the DC component in the grid input. The FIR-EPLL shown in Figure 21 is a modified version of MAF-EPLL where the MAF block is replaced with an FIR filter. One of the important parts of this filter is the delay factor (τ).

Figure 21 shows that increasing the number of delay operators can increase the harmonic filtering capability but at the cost of increasing complexity slowing down the PLL response. Hence, the selection of the number of delay operators and their time delay must be optimized between different factors such as cost, noise immunity, dynamic response performance, and filtering capacity. One of the crucial limitations of the FIR-EPLL is a high memory requirement since each delay operator in practice implementation needs to store $N=\tau /T_s$ samples in the DSP memory, which means the number of stored samples depends on the selected τ and the sampling frequency. The SSM and the parameter control designs were not given in [79]. Figure 22 shows the performance of MAF-EPLL compared with FIR-EPLL under the case of DC offset added to the grid input at 0.02 s, where the ability of FIR-EPLL to reject the DC offset increased. However, the MAF-EPLL suffers from a large fundamental frequency oscillatory error in its estimated quantities, implying a limited DC offset rejection capability.

The work in [105] is presented to cover the gaps in the FIR-EPLL, as shown in Figure 23a. Compared with the FIR-EPLL, the work in [105] utilizes two delay operators, and each operator is selected arbitrarily to improve the performance of DC offset rejection capability. Both the SSM and loop-filter design are introduced as follows. Assuming the grid voltage $v_i\left(t\right)$ contains the DC offset, the two generated voltages $v_1\left(t\right)$ and $v_2\left(t\right)$ are obtained by delaying the grid voltage twice to remove the DC offset and generate the orthogonal signals. Hence, the $v_{\alpha \beta }\left(t\right)$ signals are obtained as

$$\left[\begin{array}{c}{v}_{\alpha }\\ v_{\beta }\end{array}\right]=H^{-1} \left[\begin{array}{c}{v}_1\left(t\right)\\ v_2\left(t\right)\end{array}\right],$$

(57)

where $H^{-1}=\frac{1}{\mathrm{d}\mathrm{e}\mathrm{t} \left(\mathit{H}\right)}\left[\begin{array}{cc}\sin \left({\widehat{\mathrm{\omega }}}_g\tau \right)-\sin \left(2{\widehat{\mathrm{\omega }}}_g\tau \right)& \sin \left({\widehat{\mathrm{\omega }}}_g\tau \right)\\ -\cos \left({\widehat{\mathrm{\omega }}}_g\tau \right)+\cos \left(2{\widehat{\mathrm{\omega }}}_g\tau \right)& 1-\cos \left({\widehat{\mathrm{\omega }}}_g\tau \right)\end{array}\right]$ and $\det \left(H\right)=2\sin \left({\widehat{\mathrm{\omega }}}_g\tau \right)[1-\cos \left({\widehat{\mathrm{\omega }}}_g\tau \right)]$

Applying Park’s transformation to the Equation (57) and using trigonometric identities, the $v_q\left(t\right)$ can be obtained as in Equation (58) under a quasi-locked state:

$$v_q\left(t\right)\approx V\sin \left(\theta -\widehat{\theta }-{\omega }_g\tau +{\widehat{\omega }}_g\tau \right)$$

(58)

In small-signal analysis, Equation (58) can be written as:

$$v_q\left(t\right)\approx V\left(∆\theta -∆\widehat{\theta }-\left(∆{\omega }_g-∆{\widehat{\omega }}_g\right)\tau \right)$$

Taking the Laplace transform to the normalized $v_q\left(t\right)$ it can be written in the following form:

$$v_q\left(s\right)=\frac{\left(1+e^{-2\tau s}\right)}{2}∆\theta (s)-∆\widehat{\theta }(s)+\tau ∆{\widehat{\omega }}_g(s)$$

(59)

The SSM of the modified FIR-EPLL is shown in Figure 23b, and from the closed-loop transfer function in Equation (60), the PI controller gains are selected as $k_p=217.2$ and $k_i=15719.3$ for the selected $\tau =0.0025$. Compared to the modified version with the FIR-EPLL under the 0.1 of DC offset, it can be concluded that the modified version improved the dynamic performance of the DC offset rejection capability, with a faster phase settling time than the FIR-EPLL, as shown in Figure 24.

2.7. Advanced 1-$\varphi$ DSC-PLLs

In [106], the advanced 1-$\varphi$ PLLs using adaptive and non-adaptive αβ-reference frame delay signal cancelation operators shown in Figure 25, Figure 26 and Figure 27 are discussed in this section.

2.7.1. Adaptive 1-$\varphi$ CDSC-PLL

The adaptive 1-$\varphi$ CDSC-PLL is shown in Figure 25a. This PLL uses frequency-adaptive “variable length” operators, which involve adjusting the length of its delays according to the grid frequency variations. Nevertheless, this will increase the complexity and the cost of implementation. The SSM is shown in Figure 25b. The closed-loop transfer function of the adaptive 1-$\varphi$ CDSC-PLL is obtained as:

$$G_{cl}\left(s\right)=\frac{∆{\widehat{\theta }}_c\left(s\right)}{∆\theta \left(s\right)}=\left(\frac{1+e^{\frac{-Ts}{2}}}{2}\right)\left(\frac{1+e^{\frac{-Ts}{4}}}{2}\right)\left(\frac{1+e^{\frac{-Ts}{8}}}{2}\right)\left(\frac{1+e^{\frac{-Ts}{16}}}{2} \right)\left(\frac{1+e^{\frac{-Ts}{32}}}{2}\right)\frac{k_{p}s+k_i}{s^2+\left(k_p-k_i{k}_{dc}\right)s+k_i},$$

(60)

where, $k_{dc}=31T/64$ and $k_d=10T/64$. The characteristic polynomial of Equation (60) is a second-order polynomial. By applying the Routh–Hurwitz criteria to Equation (60) and to ensure stability, the following must be satisfied:$k_p>k_i{k}_{dc}$ and $k_i>0$. Hence, if the damping factor $\zeta$ and natural frequency ${\omega }_n$ are selected to be 1 and 2π35 rad/s, respectively, as in [106], the PI controller gains will be: $k_p=908$ and $k_i=48361$.

2.7.2. Non-Adaptive 1-$\varphi$ CDSC-PLL₁

The second version of the adaptive αβ-DSC-PLL is shown in Figure 26a. This modification was carried out to ensure a high-performance PLL. The extra αβ-DSC operator with delay factor $n$ equals 32 to provide a 90° phase difference between both αβ-axis outputs under both nominal and off-nominal frequencies. Also, the scaling factor is used to correct the amplitude in SRF-PLL under off-nominal frequencies. Finally, a phase compensator is used to compensate for the phase offset. The SSM of the non-adaptive 1-$\varphi$ CDSC-PLL1 is given in Figure 26b. Based on the SSM, the closed-loop transfer function of the non-adaptive 1-$\varphi$ CDSC-PLL1 is found as follows:

$$G_{cl}\left(s\right)=\frac{∆{\widehat{\theta }}_c\left(s\right)}{∆\theta \left(s\right)}=\frac{1+e^{\frac{-Ts}{2}}}{2}\frac{1+e^{\frac{-Ts}{4}}}{2}\frac{1+e^{\frac{-Ts}{8}}}{2}\frac{1+e^{\frac{-Ts}{16}}}{2}{\left(\frac{1+e^{\frac{-Ts}{32}}}{2}\right)}^2 \frac{\left(k_p+k_{i}T/2\right)s+k_i}{s^2+k_{p}s+k_i}$$

(61)

If $\zeta$ and ${\omega }_n$ selected to be 1 and 2π35 rad/s, the PI controller gains are $k_p=439.8$ and $k_i=48361$.

2.7.3. Non-Adaptive 1-$\varphi$ CDSC-PLL₂

Another modification for the adaptive αβ-DSC-PLL is shown in Figure 27a to solve the double frequency by ensuring that the input and output signals of the quarter cycle delay are always orthogonal. Based on reference [106], the SSM of the non-adaptive 1-$\varphi$ CDSC-PLL2 can be obtained as in Figure 27b.

Based on Figure 27b, the closed-loop transfer function is expressed as:

$$G_{cl}\left(s\right)=\left(\frac{1+e^{\frac{-Ts}{2}}}{2}\right)\left(\frac{1+e^{\frac{-Ts}{4}}}{2}\right)\left(\frac{1+e^{\frac{-Ts}{8}}}{2}\right)\left(\frac{1+e^{\frac{-Ts}{16}}}{2}\right)\left(\frac{1+e^{\frac{-Ts}{32}}}{2}\right)\frac{\left(k_p+{23Tk}_{i}T/64\right)s+k_i}{s^2+{(k}_p-T{k}_i/8)s+k_i}$$

(62)

If $\zeta$ and ${\omega }_n$ are selected to be 1 and 2π35 rad/s, the PI controller gains are $k_p=560.7$ and $k_i=48361$. Also, it should be ensured that the design parameters satisfy the Routh–Hurwitz criteria to ensure the PLL’s stability where $k_p>T{k}_i/8$ and $k_i>0$.

From Figure 28, These PLLs have the same ability to reject the DC offset with a fast dynamic response around two grid cycles. Besides this, all of these PLLs, adaptive and non-adaptive CDSC operators, at nominal grid frequency, completely block the harmonics. However, under off-nominal frequency, only adaptive CDSC-PLL completely rejects the harmonics, and some oscillation appears in the case of the used non-adaptive CDSC-PLL1 and CDSC-PLL2.

2.8. Fast Delayed Signal Cancellation-Based PLL (FDSC-PLL)

An improvement to the DSC-based PLL is introduced in [107], and the delay length is reduced from $T/4$ to $T/20$. This reduction in time delay enhances the frequency estimation. In this structure, the input voltage is written as a summation of the positive component ($v^p{e}^{j\omega t+{\mathrm{\varnothing }}_1}$) and negative component ($v^n{e}^{-j\omega t+{\mathrm{\varnothing }}_1}$) as in Equation (63), where the phase shift angles ${\mathrm{\varnothing }}_1$ and ${\mathrm{\varnothing }}_2$ are neglected for simplicity:

$$v_i\left(t\right)=v^p{e}^{j\omega t+{\varnothing }_1}+v^n{e}^{-j\omega t+{\varnothing }_2}$$

(63)

By considering digital implementation, the new expression of $v_s\left(t\right)$ is proposed as follows $v_s\left(t\right)=v_i\left(\omega t\right)-e^{-j{\theta }_d}{v}_i\left(\omega t-{\theta }_d\right)$ where ${\theta }_d=\frac{2\pi T}{N{T}_s}$ and $N$ is an integer number.

The positive sequence component can be extracted as in Equation (64), and the negative sequence component is canceled as in Equation (65):

$${{\widehat{v}}^p}_{i\alpha \beta }=\frac{[v_i\left(\omega t\right)-e^{-j{\theta }_d}{v}_i(\omega t-{\theta }_d\left)\right](1-e^{j2{\theta }_d})}{2[1-cos (2{\theta }_d\left)\right]},$$

(64)

$${{\widehat{v}}^n}_{i\alpha \beta }=\frac{[v_i\left(\omega t\right)-e^{j{\theta }_d}{v}_i(\omega t-{\theta }_d\left)\right](1-e^{-j2{\theta }_d})}{2[1-cos (2{\theta }_d\left)\right]}$$

(65)

Using Equations (64) and (65), the FDSC-PLL structure is shown in Figure 29.

Compared with the DSC-based PLL, this structure has a fast convergence with positive and negative sequence extraction under balanced or unbalanced grid voltage fault conditions. However, the reduction in ${\theta }_d$ appeared in noise and overshoot.

2.9. Two Sample PLL (2S-PLL)

As shown in Figure 30, a two-sample PLL is proposed with high immunity to harmonic distortion [108]. An adaptive filter with minimal computational burden is used. The adaptive filter gains are tuned using the gradient descent method. To ensure the stability of the filter, the selected sampling frequency must be large enough to provide a limited variation of $N$ around the central frequency. This structure is a closed-loop control. However, despite the ability of harmonic rejection, the computational burden of this method depends on the number of observers and their adaptation methods.

Table 1. The summarized of available recent TD-PLLs.

TD-PLLs	Advantages	Drawbacks	DC Offset Rejection	Harmonic Filtering	Num. of TD Operator	Ref.
1 Standard TD-PLL
a. Without compensator	1. Simple structure 2. Maintaining faster dynamics compared with other OSGs	1. Non-orthogonal signal generation due to non-adaptive delay length in the presence of frequency variations 2. Phase offset and double frequency oscillatory error in the presence of frequency variations 3. Poor harmonics filtering	No	No, poor	1	[91]
b. With compensator	1. A zero average phase error in the presence of frequency variations	1. A double-frequency oscillatory error still appears	No	No, poor	1	[91]
2 NTD-PLL
a. Conventional NTD-PLL (CNTD-PLL)	1. Simple structure 2. Fast dynamic response 3. Immune to grid frequency variations	1. It suffers from a limited harmonic and double frequency oscillatory error in the presence of frequency variations 2. Instability when the faults occurred	No	No, poor	2	[91]
b. Modified NTD-PLL (MNTD-PLL)	1. Simple structure 2. Stable 3. Fast estimation of phase and frequency components	1. Weak DC offset rejection and harmonics filtering.	No	No, poor	2	[92]
c. MAF NTD-PLL (MNP)	1. All types of disturbances are eliminated when $(T_w=T$)	1. The filtering stage introduces a phase delay, lowers PLL control bandwidth and hampers system dynamics 2. Poor dynamic performance 3. The type of disturbance removed depends on the selected value of $T_w$	Yes	Yes	2	[93]
d. MAF PLC NTD-PLL (MPNP)	1. Fast dynamic response and operational robustness against abnormal grid conditions 2. A phase delay caused by filtering structure is reduced using PLC 3. Clean synchronization with THD less than 0.3%.	1. Additional filters used increase the implementation complexity 2. High memory requirements	Yes, perfect	Yes, perfect	2	[93]
e. mNTD-PLL	1. Simple, stable, and efficient digital implementation structure. 2. Fast phase and frequency estimations	1. The estimation amplitude suffers from DFOE under frequency draft	No	No	2	[95]
f. tNTD-PLL	1. Simple structure 2. The estimated parameters are free from all DFOEs under phase, frequency, and amplitude variations.	1. It suffers from the distorted response under DC offset and harmonics disturbances	No	No	3	[97]
3 Enhanced TD-PLL (ETD-PLL)
a. ETD-PLL	1. Fast dynamic response 2. Ease of implementation 3. Accurate phase and frequency estimation in the presence of frequency variations 4. High ability to reject double frequency errors due to large frequency variation	1. Extra cost of complex implementation	No	Yes, quite good		[91]
4 ATD-PLL
	1. A simple approach to completely remove a phase offset error and double-frequency oscillatory error during the frequency drifts 2. The approximation of the cos and sin functions in the frequency feedback loop reduced the computational effort	1. Low-cost application and viable only for small frequency variations 2. Weak DC offset rejection and harmonics filtering	No	Yes, medium	1	[101,102]
5 VLTD-PLL
a. VLTD-PLL	1. It has perfectly removed the double-frequency disturbance. 2. Fast dynamic response	1. Highly non-linear 2. Complex in practical implementation compared with ATD-PLL	No	Yes, medium	1	[103]
b. ADSC-based VLTD-PLL	1. It has perfectly removed the double-frequency disturbance 2. Fast dynamic response 3. Perfect DC offset rejection	1. Memory requirement is increased	Yes, perfect	Yes, medium	2	[104]
6
a. MAF-EPLL	1. Good harmonic filtering 2. Completely blocks all frequency components that their frequency is an integer multiple of the inverse of its window length	1. Pass DC offset component 2. Slow dynamic response 3. Memory requirement depends on the sampling frequency	No	Yes, Good	0	[79]
b. FIR-EPLL	1. Fast dynamic response 2. Perfect DC offset rejection and harmonic filtering	1. High DSP memory requirement 2. Memory requirement depends on the sampling frequency	Yes	Yes, perfect	$n$	[79]
c. Modified FIR-EPLL	1. Fast dynamic response	1. High DSP memory requirement	Yes		2	[32]
7 Advanced DSC-PLL
a. Adaptive DSC-PLL	1. Fast transient response 2. It perfectly rejects the harmonics and DC offset from the grid voltage	1. The complexity and cost of implementation increased due to the use of frequency adaptive operators	Yes	Yes, perfect	8	[106]
b. Non-adaptive DSC-PLL1	1. Fast dynamic response 2. It perfectly rejects the harmonics and DC offset from the grid voltage 3. The use of non-adaptive operators decreases the cost of implementation	1. Under off-nominal frequency, some oscillatory ripples appeared in their estimated parameters. 2. It does not block the harmonics completely	Yes	Yes, Good	10	[106]
c. Non-adaptive DSC-PLL2	1. Fast dynamic response 2. It perfectly rejects the harmonics and DC offset from the grid voltage 3. The use of non-adaptive operators decreases the cost of implementation	1. Under off-nominal frequency, some oscillatory ripples appeared in their estimated parameters. 2. It does not block the harmonics completely	Yes	Yes, Good	8	[106]
8 FDSC-PLL
FDSC-PLL	1. Fast convergence under balanced or unbalanced fault grid conditions	1. The reduction in ${\theta }_d$ used appeared in noise and overshoot in the estimated grid frequency	No	No	1	[107]
9 2S-PLL
	1. High immunity to harmonic distortion 2. Minimal computational burden is used with an adaptive filter	1. Computational burden depends on the number of observers used	No	Yes, Good	1	[108]

outlines all available TD-PLLs in terms of the DC offset rejection capability, harmonic filtering, and the major advantages and drawbacks.

3. Optimal Loop Filter (LF) Design Based on a Large-Signal Model

All LF designs reported in the literature are based on SSMs. The SSM uses a linear control method based on assumptions and simplifications, such as ignoring the non-linear terms. In this section, the PI controller gains of the LF are designed using stochastic optimization such as particle swarm optimization (PSO) and genetic algorithm (GA), as shown in the flowchart in Figure 31. Both the ADSC with VLTD-PLL and the mFIR-EPLL can reject the DC offset. Hence, they are nominated for the case study without loss of generality. By selecting the time-delay factor ($\tau =T/a$) where a is any real positive number, the optimal gains of $k_p$ and $k_i$ are found. The minimization of the integral time absolute error (ITAE) is taken as an objective function as in Equation (66), which is one of the error performance indices with a fast settling time with less overshoot. The worst-case disturbance on the system is selected as the frequency jump.

$$\mathrm{M}\mathrm{i}\mathrm{n}\mathrm{i}\mathrm{m}\mathrm{i}\mathrm{z}\mathrm{e} J={\int }_0^{t_{ss}}t\left|\theta -\widehat{\theta }\right|dt$$

(66)

Different constraints, conditions, and the $k_p$ and $k_i$ boundaries are defined as in the following:

$$\mathrm{subject} \mathrm{to} \left\{\begin{array}{c}{k}_p/k_i>0.02 \\ k_i>0\\ k_p^{min}<k_p<k_p^{max} \\ k_i^{min}<k_i<k_i^{max}\\ OS<2\%\end{array}\right.$$

(67)

The following initial parameters are considered when PSO and GA algorithms are used in designing a PI controller, as in

Table 2. Initial parameters for GA and PSO.

Algorithms
PSO	Swarm size = 10 Max. iteration = 20 [$k_p^{min},k_i^{min}$] = [20 1000] [$k_p^{max},k_i^{max}$] = [2000 100,000]
GA	Generation = 10 Max. iteration = 20 [$k_p^{min},k_i^{min}$] = [20 1000] [$k_p^{max},k_i^{max}$] = [2000 100,000]

. Figure 31 shows the flowchart for minimizing the error difference in the estimated phase. The gains are rejected if the criterion is not satisfied, and the random gains are generated for the next update.

The optimal PI controller gains are found in

Table 3. Optimal PI controller gains based on PSO and GA.

ADSC-based VLTD-PLL	PSO Algorithm
	a	${{\mathit{k}}_{\mathit{p}}\left(\mathit{a}\right)}^{\mathit{o}\mathit{p}\mathit{t}\mathit{i}\mathit{m}}$	${{\mathit{k}}_{\mathit{i}}\left(\mathit{a}\right)}^{\mathit{o}\mathit{p}\mathit{t}\mathit{i}\mathit{m}}$	OS (%)	ST (ms)	J
	4	1010.70	8566.5	0.550	27.2	0.0187
	5	820.6275	89,557.1	0.901	26.5	0.0168
	8	833.6018	99,682.6	0.930	25.6	0.0147
	10	889.6368	99,963.6	0.641	25.8	0.0151
	20	1072.60	99,949	0.374	32.0	0.0207
	GA Algorithm
	4	921.3099	91,354.1	0.70900	31.9	0.0190
	5	754.8568	72,239.3	0.31700	18.4	0.0188
	8	936.1972	86,697.3	0.00772	24.3	0.0172
	10	1011.50	94,310.3	0.00762	24.3	0.0169
	20	1031.60	93,599.4	0.37500	32.4	0.0218
The mFIR-EPLL	PSO Algorithm
	4	984.5934	93,258.5	0.1250	20.4	0.0238
	5	878.5227	95,345.3	0.2380	18.2	0.0198
	8	781.3861	99,991.6	0.1570	15.8	0.0133
	10	734.2352	93,843.1	0.0464	16.6	0.0118
	20	601.1943	99,517.2	0.3070	11.4	0.00799
	GA Algorithm
	4	589.7581	53,551.0	0.6420	30.4	0.0318
	5	611.9827	68,325.7	0.8710	27.2	0.0243
	8	954.4283	96,713.9	0.0104	25.4	0.0152
	10	591.6748	75,155.4	0.2900	15.8	0.0138
	20	437.3930	54,748.5	0.2040	16.9	0.0135

. The overshoot and settling time are found using the stepinfo instruction in the MATLAB program 2018b for the estimated frequency under a 10 Hz frequency jump.

The optimal parameters are applied to the ADSC-based VLTD-PLL and the mFIR-EPLL to test the dynamic performance and compare it with the responses based on SSMs. The parameters in

Table 4. The PI controller gains are selected in this comparison based on SSMs and optimization.

PLL Type	SSM Method	Optimization Method
ADSC-based VLTD-PLL	$a=10$ $k_p=376.98$ $k_i=25551$	$a=10$ $k_p=1011.50$ $k_i=94310.3$
mFIR-EPLL	$a=8$ $k_p=217.2$ $k_i=15719.3$	$a=20$ $k_p=601.1943$ $k_i=99517.2$

are used in this comparison. For each PLL, suppose the DC offset is added from the start to the grid voltage, then at time 0.02 s, the grid phase undergoes a 20$°$ phase jump, and the grid frequency undergoes a +10 Hz frequency change at time 0.12 s. The comparison results for ADSC-based VLTD-PLL and the mFIR-EPLL are shown in Figure 32 and Figure 33, respectively. The numerical results of this comparison are summarized in

Table 5. Numerical summary of the comparison results between the proposed PLL and other recent PLLs.

Disturbance Type	The ADSC-Based VLTD-PLL		mFIR-EPLL
	SSM Gains	Optimal Gains	SSM Gains	Optimal Gains
10 Hz frequency jump and 0.10 pu DC offset
2% frequency settling time (ms)	42.5	24.3	49.90	11.40
Frequency overshoot (%)	0.3635	0.0076	0.6876	0.2902
Peak phase error (°)	21.09	18.36	19.15	12.66
Absolute peak frequency error (Hz)	0.22	0	0.42	0.19
20° phase jump and 0.10 pu DC offset
2% phase settling time (ms)	42.2	27.7	40.7	16.20
Phase overshoot (%)	35.17	36.86	32.408	46.183
Absolute peak frequency error (Hz)	52.88	54.69	52.96	59.62

, showing the settling time, overshoot, peak phase error, and absolute peak frequency error. Figure 32 shows that for the case under a 10 Hz frequency jump, the ADSC-based VLTD-PLL’s settling time is improved and decreased to half with zero overshoot when the optimal gains are used. Also, under the 20$°$ phase jump, the ADSC-based VLTD-PLL’s settling time is improved and decreased to half. However, the overshoot and absolute peak phase error are slightly increased. The mFIR-EPLL’s settling time under 10 Hz frequency jump is enhanced and reduced to about a quarter, as shown in Figure 33. The frequency overshoot is reduced to half. Phase and absolute peak frequency errors are also improved. Also, from Figure 33, under the case of phase jump, the mFIR-EPLL’s phase settling time is found to be less than one grid cycle. However, the phase overshoot and absolute peak frequency error are slightly higher. It can be concluded that the optimal gains improved the settling times and the overshoot.

4. Discussion

Table 1 outlines all reviewed TD-based PLLs in terms of their ability to remove the DC offset, harmonic filtering, the major advantages, and drawbacks. This comprehensive review of the closed-loop synchronization-based recent TD-based PLLs includes conventional TD-PLLs, NTD-PLLs, ETD-PLLs, ATD-PLLs, VLTD-PLLs, advanced DSC-PLLs, FDSC-PLLs, and 2S-PLLs. In summary, all recent TD-based PLLs have a fast dynamic response with a phase settling time around two grid cycles.

Table A1. TD-based PLLs and Their Tuning Method.

TD-PLLs Types	$\mathbf{Signal} {\mathit{V}}_{\mathit{q}}$	PI-Controller Parameters	Tuning Method	$\widehat{\mathit{V}}$
Standard TD-PLL	$v_q\left(s\right)\approx V\left[\left(\frac{1+e^{-sT/4}}{2}\right)∆\theta -∆\widehat{\theta }-D\left(s\right)\right]$	$k_p=\left(2\zeta \omega \right)/V$ $k_i={\omega }^2/V$	Second order characteristic	= $V_d$
CNTD-PLL	$v_q\left(s\right)\approx V\left(\frac{1+e^{-sT/4}}{2}\right)\left[∆\theta -∆\widehat{\theta }-D\left(s\right)\right]$	$k_p=1/\left(Vb\right(T/8))$ $k_i=1/(V{b}^3{\left(T/8\right)}^2)$	Symmetric optimum method	= $V_d$
MNTD-PLL	$v_q\left(s\right)=V{k}_s\left(\frac{1+e^{-s{T}_d}}{2}\right)\left[∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)\right]+d_{hf}\left(s\right)$	${\omega }_c=\frac{1}{T_i\sqrt{{\acute{T}}_d}}$, $T_i=b^2{\acute{T}}_d$ $k_p=1/(Vb{\acute{T}}_d)$ $k_{is}=1/\left(V{b}^3{\left({\acute{T}}_d\right)}^2\right)$	Symmetric optimum method	= $V_d$
MPNP	$v_q\left(s\right)=V\left(\frac{1+e^{-s(T/4) }}{2}\right)\left[∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)\right]+D_h\left(s\right)$	$T_i=b^2\left(T/8\right)$ $k_p=1/\left(Vb\right(T/8))$ $k_i=1/(V{b}^3{\left(T/8\right)}^2)$	Symmetric optimum method	= $V_d$
mNTD-PLL	$v_q\left(s\right)\approx V\left(\frac{1+e^{-sT/4}}{2}\right)\left[∆\theta -∆\widehat{\theta }\right]$	----------------------------	----------------------------	= $V_d$
ETD-PLL	$v_q\left(s\right)=V{G}_1\left(s\right)\left[∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)\right]$ $G_1\left(s\right)={\left(\frac{1+e^{-s(T/4) }}{2}\right)}^2\left(\frac{1+e^{-s(T/8) }}{2}\right)\left(\frac{1+e^{-s(T/16) }}{2}\right)$	$k_p=\left(2\omega \right)/V$ $k_i={\omega }^2/V$	Second order characteristic	= $V_d$
ATD-PLL	$v_q\left(s\right)=V\left[\frac{1+e^{\frac{-T}{4}s}}{2}∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)+\frac{∆{\widehat{\omega }}_g\left(s\right)T}{8}\right]$	$k_p=\left(2\zeta \omega \right)/V+k_{i}T/8$ $k_i={\omega }^2/V$	Second order characteristic	= $V_d$
VLTD-PLL	$v_q\left(s\right)=V\left[\frac{1+e^{\frac{-T}{4}s}}{2}∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)+\frac{∆{\widehat{\omega }}_g\left(s\right)T}{8}\right]$	$k_p=\left(2\zeta \omega \right)/V+k_{i}T/8$ $k_i={\omega }^2/V$	Second order characteristic	= $V_d$
ADSC with VLTD-PLL	$v_q\left(s\right)=2V\sin \left(\frac{{\omega }_n\tau }{2}\right)\left[\frac{1+e^{-\left(\tau +\frac{T}{4}\right)s}}{2}∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)+\frac{∆{\widehat{\omega }}_g\left(s\right)T}{8}+\frac{∆{\widehat{\omega }}_g\left(s\right)\tau }{2}\right]$	$k_p=\left(2\zeta \omega \right)/k_v+k_i(\tau /2+T/8)$ $k_i={\omega }^2/k_v$ $k_v=2V\sin \left({\omega }_n\tau /2\right)$	Second order characteristic	= $V_d\times 2\sin \frac{{\widehat{\omega }}_g\tau }{2}$
mFIR-EPLL	$v_q\left(s\right)=\frac{1+e^{-2\tau s}}{2}∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)+∆{\widehat{\omega }}_g\left(s\right)\tau$	$k_p=2\zeta \omega +k_i\tau$, $k_i={\omega }^2$	Second order characteristic	= $V_d$
Adaptive CDSC-PLL		$k_p=\left(2\zeta \omega \right)/V+10k_{i}T/64$ $k_i={\omega }^2/V$	Second order characteristic	= $V_d$
Non-adaptive DSC-PLL1	$v_q\left(s\right)=V{G}_1\left(s\right)\left[∆\theta \left(s\right)-∆\widehat{\theta }\left(s\right)\right]$ $G_1\left(s\right)={\displaystyle \prod _{n=\mathrm{2,4},\mathrm{6,8},\mathrm{16,32}}}\left(\frac{1+e^{-s(T/n) }}{2}\right)$	$k_p=\left(2\zeta \omega \right)/V$ $k_i={\omega }^2/V$	Second order characteristic	= $V_d$
Non-adaptive DSC-PLL2		$k_p=\left(2\zeta \omega \right)/V+k_{i}T/8$ $k_i={\omega }^2/V$	Second order characteristic	= $V_d$

in Appendix A provides information regarding the PLLs’ small signal model and the general LF gains calculation formula with the criteria used to design them. In general, most of the PLLs are designed either using $\zeta$ and ${\omega }_N$ if the closed loop system is a second order, or using the SOM for a third order PLLs. Therefore,

Table A2. The Most Common Control Design Parameters.

Tuning Method	Parameters	Range
Second order characteristic	$\zeta$ ${\omega }_N$	(0.5–1) (2$\pi 10-2\pi 50$) [rad/s]
Symmetric optimum method	$PM$ $b$	$(30–60°)$ (1.732–3.732)

in Appendix B provides the most common control design parameters of the LF gains. Moreover, if the SSM of the PLLs is hard to find or the LF-based SSM design responses are not satisfactory, Section 2.3 provides a mechanism to design the LF gains using stochastic optimization relying on the actual PLL without approximation. The summary of this work can be covered in the following points:

• The conventional TD-PLL requires a phase compensator to achieve a zero average phase error under the frequency variation. However, the harmonics filtering is poor and cannot reject the DC offset.
• The CNTD-PLL structure has a five-modified version, including an MNTD-PLL, MNP, MPNP, mNTD-PLL, and tNTD-PLL. The double frequency oscillatory error under the frequency drafts is eliminated from all except the CNTD-PLL and mNTD-PLL, which still suffer from it in frequency and amplitude responses, respectively. The harmonics filtering and DC offset rejection are poor for all except MNP and MPNP. However, all disturbances are mitigated using MNP and MPNP depending on the selected MAF window length, resulting in a slow dynamic performance and high memory requirements.
• The ETD-PLL, ATD-PLL, VLTD-PLL, and ADSC-based VLTD-PLL perfectly removed the double frequency oscillatory error under the frequency draft. However, only ADSC-based VLTD-PLLs can reject the DC offset perfectly. The ATD-PLL has a minimum memory requirement compared with this group of PLLs.
• All of the MAF-EPLLs, FIR-EPLLs, and modified FIR-EPLLs have good harmonic filtering. However, MAF-EPLLs cannot reject DC offset unless the window length is the same as the fundamental grid period.
• Good harmonics filtering and the perfect DC offset rejection are achieved using adaptive and non-adaptive DSC-PLLs. However, the use of adaptation operators increased the design complexity.
• It is well known that the estimated amplitude is a by-product of the PLL. In the nominal frequency case, the d-axis output of the Park transformation estimates the grid voltage. However, amplitude correction must be applied to the estimated d-axis component using frequency-fixed DC offset rejection to estimate the amplitude correctly. The correction factor can be obtained from the transfer function of the PLL.

5. Conclusions

This paper provides a detailed investigation to review recent research for designing single-phase PLLs based on TD operators. The most popular types of PLLs based on TD operators were then described; their advantages, drawbacks, and limitations were explained deeply, and some guidelines to enhance their performance were presented.

Many power quality issues, such as DC offsets, harmonic filtering, phase disturbance, voltage sag/sell, and harmonic oscillations, require a PLL with fast and accurate detection to avoid synchronizing single-phase grid-connected systems. The effectiveness of these PLLs due to normal and abnormal conditions is reviewed deeply. Also, the review provides useful information about the characteristics and small-signal models of different single-phase TD-PLLs. Each characteristic can indicate the PI controller tuning method.

Many applications used a single-phase PLL as a part of the control system, such as inter-harmonics extraction, estimated electromechanical oscillations, delay compensation used in power converters, and designing frequency-adaptive resonant controllers. So, selecting the type of PLL used with grid-connected systems must be a tradeoff between the industrial application used, the kind of disturbance that occurs, and the appropriate performance it can achieve.

This review paper is expected to be a useful reference for new researchers with limited knowledge in this field, especially those who want to contribute. It can also be a guideline for engineers who wish to select an appropriate single-phase PLL for their application.

In the last section of this work, since all PLLs designed controllers based on their small-signal model, the large-signal model with all nonlinearities in the system is investigated. The optimal PI controller parameters of the PLL using the stochastic optimization algorithm are presented, considering the worst disturbance case on the grid, assuming the DC offset with the grid’s frequency variation. This paper also demonstrated in detail how to employ stochastic optimization to search the optimal PI controller parameters. The result clearly shows that the optimal PI controller can achieve better performance indexes, such as fast response with approximately zero percent overshoot compared to the PI controller parameters based on the SSM. Under the worst-case scenario, a frequency jump with a DC offset occurs on the grid. The frequency settling time of the ADSC-based VLTD-PLL using optimal gains is twice as fast as that using the SSM gains. Meanwhile, the frequency settling time of the modified FIR-EPLL using optimal gains is four times faster than the SSM gains. Also, optimal gain selection based on the large system model can be appropriate when the small signal is challenging to find mathematically, avoiding the time-consuming trial-and-error design method, or when fine-tuning is needed, taking the SSM-based gains as initial input to the stochastic optimization.