SiC MOSFET Active Gate Drive Circuit Based on Switching Transient Feedback

Abstract

Due to the influence of parasitic internal parameters and junction capacitance, the silicon carbide (SiC) power devices are frequently marred by significant overshoots in current and voltage, as well as high-frequency oscillations during the switching process. These phenomena can severely compromise the reliability of SiC-based power electronic converters during operation. This study delves into the switching transient of the SiC MOSFET with the goal of establishing a quantitative correlation between the gate driving current and the overshoot in both the drain-source voltage and the drain current. In light of these findings, the innovative active gate drive (AGD) circuit, which features an adjustable gate current, is introduced. Throughout the switching process, the AGD circuit employs a dynamic monitoring and feedback mechanism that is responsive to the gate voltage and rate of change in the drain-source voltage and drain current of the SiC MOSFET. This adjustment enables gate driving current to be actively modified, thereby effectively mitigating the occurrence of overshoots and oscillations. To empirically validate the efficacy of the proposed AGD circuit in curbing voltage and current overshoots and oscillations, a double-pulse experimental setup was meticulously constructed and tested.

1. Introduction

Silicon carbide (SiC) is a new semiconductor material with a wide bandgap and high breakdown voltage. Its bandgap width is approximately three times that of silicon (Si), and its breakdown voltage exceeds that of Si by over 10 times [1]. SiC MOSFETs are also renowned for their exceptional properties, including a high blocking voltage capacity, minimal on-state resistance, superior thermal conductivity, and rapid switching speeds [2]. Consequently, the implementation of SiC MOSFET has been recognized and adopted across a broad spectrum of industrial applications. This includes areas like the propulsion systems of electric vehicles, the technology-laden aerospace sector, and the burgeoning field of renewable energy [3,4]. However, with the escalation of the switching frequency in SiC MOSFETs, the susceptibility of these devices to internal parasitic elements and junction capacitance is amplified. According to the literature [5], the rate of voltage change (dV/dt) for 10 kV SiC MOSFETs can exceed 140 V/ns. This figure is the voltage rate immunity threshold of a majority of driver-integrated circuits (ICs). Concurrently, the high-speed transition of states leads to significant overshoots in both voltage and current, accompanied by oscillatory phenomena [6,7], leading to intensified electromagnetic interference (EMI), increased device loss, and shortened lifetimes [8,9]. Therefore, to enhance the security and dependability of SiC-based circuit systems, research on suppression methods for the overshoot and oscillation has important theoretical value.

Active gate drive (AGD) is a circuit composed of active devices based on a conventional drive circuit (CGD), which changes the structure of the gate drive circuit at specific stages of the switching procedure to optimize switching characteristics of SiC MOSFETs [10]. Therefore, AGD has been extensively studied by scholars in recent years, and three driving schemes have been proposed: variable driving resistance [11,12], variable driving voltage [13,14,15], and variable driving current [10,16,17]. A short-circuit resistance method is proposed in [11]. By controlling the gate drive resistance at different stages, the drive resistance is increased as the current ascends during the turn-on stage and decreased as the voltage ascends during the turn-off stage. Such an approach is instrumental in diminishing the peak reverse recovery current experienced by the body-diode, but the gate voltage detection is easily disturbed by gate loop oscillation, causing erroneous switching actions. A multi-stage AGD drive circuit is proposed in [15], equipped with two-level circuits, a main drive and an auxiliary drive. However, this circuit is relatively complex, and the switching of the drive circuit requires software implementation, which reduces the reliability and practicality of the system. An AGD circuit based on a mirror current source is presented in [16]. During various stages of the switching operation, the phenomena of the overshoot and oscillation of the voltage or current can be effectively mitigated through the strategic modulation of the driving current. A proposed solution involves the implementation of an AGD for SiC MOSFETs, characterized by a segmented and dynamic adjustment mechanism for the driving current. This system is capable of making real-time adjustments to the gate current based on the transient feedback received at different stages of the switching process, as referenced in [10]. However, this design is somewhat complex and involves the use of an excessive number of active switching components. An alternative AGD is crafted with a focus on the principal factors that contribute to current and voltage overshoot and oscillation, as indicated in [17]. This driver is engineered to counteract these issues by selectively increasing the gate resistance and decreasing the gate driving current at specific intervals. However, this solution will increase losses. The essence of the AGD method of variable drive resistance and variable drive voltage is adjusting the gate drive current, so the variable drive current solution is simpler and more practical. Since the switching process is very short, the generation mechanism of the drive circuit control signal is a difficult part of the AGD solution. At the same time, it is necessary to prevent incorrect operation of the AGD circuit due to switching signal jitter or oscillation of voltage and current.

Based on the characteristics analysis for the turn-on and turn-off process of the SiC MOSFET, an AGD circuit for dynamic adjustment of the drive current is proposed. With the transient detecting the gate voltage, change rate of the drain current, dynamically controlled to mitigate overshoots and the drain-source voltage of SiC MOSFET, the gate drive current is and prevent oscillations. This circuit has the advantage of a simple structure, high detection accuracy, accurate control signal generation time, and high reliability. To validate its performance, a double-pulse experimental setup was constructed to test the AGD circuit’s effectiveness in mitigating voltage and current overshoots and oscillations.

2. Analysis of SiC MOSFET Switching Characteristics

Figure 1 illustrates the double-pulse circuit model, which accounts for the parasitic parameters inherent to the SiC MOSFET, where M₁ and M₂ are the ideal models of the SiC MOSFET and diode, respectively. C_gd, C_gs, and C_ds represent the gate-drain, gate-source, and drain-source capacitances, respectively. R_g denotes the gate resistance, and L_g, L_d, L_s and L_S correspond to the parasitic inductances associated with the gate lead, drain-gate connection, Kelvin sense terminals, and power source. Meanwhile, the circuit incorporates the notions of input capacitance C_iss, output capacitance C_oss, and reverse transfer capacitance C_rss to delineate the inter-capacitance relationships at each junction.

2.1. Analysis of Turn-on Characteristics

The characteristic curves of the turn-on process, depicted as Figure 2, are primarily divided into four stages:

Stage (t₀~t₁): When the gate charging is delayed, the gate-source voltage V_gs transitions from V_EE (negative voltage) to V_CC (positive voltage), with C_iss being charged via the gate drive resistor. During this stage, V_gs is less than the threshold voltage V_th, resulting in no change to V_ds (drain-source voltage) and I_d (drain current), which remain in a static state.

Stage (t₁~t₂): At t₁, upon V_gs attaining the threshold voltage V_th, the gate current persists in charging the input capacitor C_iss, and the drain current I_d incrementally ascends towards I_L (load current). This rise can be subject to the influence of the reverse recovery current I_r from the anti-parallel diode. I_d will continue to increase and reach the current spike I_{d_peak} at t₂. I_{d_peak} can be expressed as follows:

$$I_{\mathrm{d}\_\mathrm{peak}}=I_{\mathrm{L}}+I_{\mathrm{r}}$$

(1)

I_r is positively related to the drain current change rate dI_d/dt:

$$I_{\mathrm{r}}=\sqrt{Q_{\mathrm{rr}}·\mathrm{d}{I}_{\mathrm{d}}/\mathrm{d}t}$$

(2)

where Q_rr signifies the reverse recovery charge associated with the anti-parallel diode. The change rate of I_d, denoted as dI_d/dt, can be approximated as follows:

$$\frac{\mathrm{d}{I}_{\mathrm{d}}}{\mathrm{d}t}=\frac{(V_{\mathrm{CC}}-V_{\mathrm{th}})g_{\mathrm{m}}}{C_{\mathrm{iss}}{R}_{\mathrm{g}}+g_{\mathrm{m}}{L}_{\mathrm{s}}}\approx g_{\mathrm{m}}\times \frac{I_{\mathrm{g}}}{C_{\mathrm{iss}}}$$

(3)

According to (2) and (3), the relationship between I_r and I_g can be expressed as

$$I_{\mathrm{r}}=\sqrt{\frac{g_{\mathrm{m}}{I}_{\mathrm{g}}{Q}_{\mathrm{rr}}}{C_{\mathrm{iss}}}}$$

(4)

It can be seen from Equation (4) that I_r is positively correlated with I_g. Therefore, reducing I_g can effectively reduce the drain current spike.

Stage (t₂~t₃): The reverse recovery charge is completely released, I_d returns to I_L and remains unchanged, and V_gs is clamped at the Miller voltage V_miller. The gate-drain capacitor C_gd is charged with a constant gate current I_g, and the anti-parallel diode begins to block V_ds. V_ds gradually decreases to zero. I_g can be articulated by the following expression:

$$I_{\mathrm{g}}=\frac{V_{\mathrm{cc}}-V_{\mathrm{miller}}}{R_{\mathrm{g}}}$$

(5)

The rate of change for V_ds is given by the expression:

$$\frac{\mathrm{d}{V}_{\mathrm{ds}}}{\mathrm{d}t}=-\frac{I_{\mathrm{g}}}{C_{\mathrm{gd}}}$$

(6)

Substituting Equation (6) into Equation (5), t_down, the duration of the V_ds drop process, can be obtained as

$$t_{\mathrm{down}}=\frac{C_{\mathrm{gd}}(V_{\mathrm{dc}}-V_{\mathrm{ds}})}{I_{\mathrm{g}}}$$

(7)

Stage (t₃~t₄): The gate current continues to charge C_gs until the device is saturated. V_gs rises exponentially to the reference gate voltage V_CC, V_ds drops to a value close to zero, and I_d is maintained at I_L.

2.2. Analysis of Turn-off Characteristics

The characteristic curves of the turn-off process, depicted in Figure 3, are primarily divided into four stages:

Stage (t₅~t₆): The drive voltage transitions from V_CC to V_EE, and C_iss starts to discharge through the gate resistance R_g and source resistance L_s. I_d and V_ds remain unchanged. At t₆, V_gs drops to the Miller voltage V_Miller.

Stage (t₆~t₇): V_ds gradually increases, but I_d remains unchanged.

Stage (t₇~t₈): As V_gs descends to the threshold voltage, I_d diminishes swiftly, thereby generating an induced voltage across the circuit’s parasitic inductance. This induced voltage, when combined with the DC-bus voltage, results in a voltage spike, denoted as V_{ds_peak}. The spike can be formulated as

$$V_{\mathrm{ds}\_\mathrm{peak}}=V_{\text{dc}}+L_{\text{loop}}\frac{d{I}_{\text{d}}}{dt}$$

(8)

where L_loop represents the total parasitic inductance of the whole double-pulse circuit. The change rate of I_d is

$$\frac{d{I}_{\text{d}}}{dt}=\frac{\left(V_{\text{th}}-V_{\text{EE}}\right)g_{\text{m}}}{C_{\text{iss}}{R}_{\text{g}}+L_{\text{s}}{g}_{\text{m}}}\approx g_{\text{m}}\times \frac{I_{\text{g}}}{C_{\text{iss}}}$$

(9)

According to (9), diminishing the gate current I_g serves as an effective approach to curtailing voltage overshoot during the voltage increase stage.

Stage (t₈~t₉): V_gs drops to the negative voltage V_EE. The overvoltage will oscillate, attenuated until stable.

In light of the preceding analysis, during the ascent of I_d in the turn-on stage, the surge in I_d can be mitigated by extracting I_g. Likewise, during the increase in V_ds in the turn-off stage, the excess in V_ds can be curtailed by injecting I_g. To minimize switching losses, the original I_g should be restored in other phases of the switching process. This restoration can shorten the charging and discharging duration of C_gd within the Miller plateau, thus enhancing the switching rate. This study introduces an active gate current adjustment circuit that leverages the transient feedback of the change rates of V_gs, I_d, and V_ds for dynamic regulation.

3. Hardware Implementation of the Proposed AGD Circuit

The proposed AGD circuit is shown in Figure 4. It is divided into four parts: (1) detection circuit of turn-on current rising state; (2) turn-off voltage rising state detection circuit; (3) current shunt circuit; and (4) current injection circuit. The specific implementation schemes of each circuit are as follows:

(1) The detection circuit of the turn-on current rising state comprises a dI_d/dt detection circuit and a V_gs-on voltage detection circuit. The dI_d/dt detection circuit utilizes L_sS, the parasitic inductance between the Kelvin source and the power source, which generates an induced voltage V_sS due to the change in current, so the signal of dI_d/dt is converted into a voltage signal for detection. To detect the voltage signal during the current rising stage in the turn-on process, a diode D₁ is employed to filter out spurious signals that may arise from the descent of the current during the turn-off stage. The induced voltage of L_sS is detected when the SiC MOSFET is turned on, and is compared with the reference voltage V_r3 to generate a corresponding logic signal. The value of V_r3 is defined by the following equation:

$$V_{\mathrm{r}3}=L_{\mathrm{sS}}\times \frac{(V_{\mathrm{CC}}-V_{\mathrm{th}})g_{\mathrm{m}}}{C_{\mathrm{iss}}{R}_{\mathrm{g}}+g_{\mathrm{m}}{L}_{\mathrm{s}}}\times \frac{R_9}{R_8+R_9}$$

(10)

The V_gs-on voltage detection circuit, with voltage dividing resistors (R₆ and R₇), comparators (OP₁ and OP₂) and AND gate (AND₃), eliminates the interference from the current rising stage and I_d oscillation after device turn-on. By detecting whether V_gs is within the interval [V_th, V_miller] and using the logic signal from the dI_d/dt detection circuit, the phase of current increase during the turn-on process is accurately identified. The values of comparison voltages V_r1 and V_r2 are defined by the following equations, respectively.

$$V_{\mathrm{r}1}=V_{\mathrm{miller}}\times \frac{R_7}{R_6+R_7}$$

(11)

$$V_{\mathrm{r}2}=V_{\mathrm{th}}\times \frac{R_7}{R_6+R_7}$$

(12)

(2) Voltage rising state detection circuit for turn-off stage: It consists of two parts, dV_ds/dt detection circuit and V_gs-off detection circuit. The detection circuit of the dV_ds/dt utilizes a differential circuit to calculate the voltage change rate of V_ds during the turn-off stage, then the dV_ds/dt is converted into a voltage signal. This signal is compared with the reference voltage V_r6 through a comparator. It should be noted that the diode D₂ is employed to block the interference signals generated during the turn-on stage. V_r6 is defined by the following equation:

$$V_{\mathrm{r}6}=R_{4}C\times \frac{V_{\mathrm{EE}}-V_{\mathrm{miller}}}{C_{\mathrm{gd}}\times R_{\mathrm{g}}}\times \frac{R_4}{R_4+R_3}$$

(13)

Similarly to the turn-on part, the V_gs-off voltage detection circuit, consisting of voltage dividing resistors (R₃ and R₄), comparators (OP₄ and OP₅) and an AND gate (AND₂), is designed to eliminate interference caused by V_ds oscillation after the device is turned on. By detecting whether V_gs is within the interval [V_r4, V_r5] and cooperating with the logic output signal from the dV_ds/dt detection circuit, the phase of voltage increase during the turn-off process is accurately identified. The values of the comparison voltages V_r4 and V_r5 are determined by the following equations, respectively.

$$V_{\mathrm{r}4}=V_{\mathrm{miller}}\times \frac{R_7}{R_6+R_7}$$

(14)

$$V_{\mathrm{r}5}=V_{\mathrm{gs}}(t_{7\mathrm{A}})\times \frac{R_1}{R_2+R_1}$$

(15)

$$V_{\mathrm{gs}}\left(t\right)=V_{\mathrm{EE}}+\left(V_{\mathrm{miller}}-V_{\mathrm{EE}}\right)\times \left(1-e^{-t_{\mathrm{if}}/R_{\mathrm{g}}\times C_{\mathrm{iss}}}\right)$$

(16)

$$t_{\mathrm{if}}=R_{\mathrm{g}}\left(C_{\mathrm{GS}}+C_{\mathrm{GD}}\right)\times \ln \frac{V_{\mathrm{th}}-\frac{I_{\mathrm{D}}}{g_{\mathrm{m}}}-V_{\mathrm{EE}}}{V_{\mathrm{th}}-V_{\mathrm{EE}}}$$

(17)

(3) Extraction circuit: It includes a push–pull amplifier circuit, MOS₁, diode and resistor. The detection signal, generated by the current rising state detection circuit, is amplified by the push–pull circuit and drives the MOS₁ to conduct. A portion of the gate current flows out through MOS₁ and R₁₀.

(4) Injection circuit: The structure is similar to that of the shunt circuit. The detection signal, generated by the turn-off voltage rising state detection circuit, drives the MOS₂ to conduct through the push–pull circuit. Reversed gate current is injected into the gate, reducing the discharge current during the turn-off process.

4. Active Drive Control Process

4.1. Turn-on Process Control

As the SiC MOSFET is turned on, V_gs, I_d, V_ds and other signal waveforms of each detection circuit are as shown in Figure 5. The control process is categorized into four stages.

(1) During the delay stage (t₀–t₁), the external drive signal transitions from V_EE to V_CC, and V_gs gradually rises. At this stage, V_gs does not reach the lowest set voltage V_r2, so the AND₃ outputs the low-level voltage. Both the dI_d/dt detection circuit and dV_ds/dt detection circuit have no induction signal output.

(2) During the current rising stage (t₁–t₂), when V_gs satisfies the math condition (V_r2 < V_gs < V_r1), the AND₃ outputs the high-level voltage. At the same time, the rapidly rising gate current generates an induced voltage on the auxiliary source inductor L_sS. After voltage division, when the induced voltage V_sS satisfies the following condition:

$$V_{\mathrm{sS}}>\frac{R_8+R_9}{R_9}{V}_{\mathrm{r}3}$$

(18)

OP₃ outputs the high-level voltage. Meanwhile, AND₁ receives two high-level input signals and outputs the high-level voltage. Through the push–pull amplification circuit, the MOS₁ is controlled to be turned on, the circuit of the current extraction is turned on, and partial gate current will flow to the ground through R₁₀, namely I_g1. The gate drive current is reduced to I_g−I_g1, the change rate of I_d also decreases with the decrease in I_g, and the corresponding overshoot of I_d is reduced. At this stage, the current injection circuit remains in the state of low-level voltage output.

(3) During the current oscillation stage (t₂–t₃), several cycles of oscillation will occur, causing the dI_d/dt detection circuit OP₃ to generate a high-level signal again. However, since V_gs is larger than V_miller, AND₃ outputs the low-level voltage and MOS₁ is turned off at this moment, so the circuit of the current extraction is blocked. Meanwhile, the gate drive current returns to I_g.

(4) During the stage (t₃–t₄), when the SiC MOSFET is fully turned on, the induction signal of the dI_d/dt detection circuit outputs a low-level voltage, the control circuit does not work, and MOS₁ remains in the turn-off state.

4.2. Turn-off Process Control

As the SiC MOSFET is turned off, V_gs, I_d, V_ds and other signal waveforms of each detection circuit are as shown in Figure 6. The control of the turn-off process mainly includes four stages.

(1) During the turn-off delay stage (t₅–t₆), the external drive signal transitions from V_EE to V_CC, and V_gs gradually decreases. At this stage, V_gs is greater than V_r4, the maximum reference value set for the turn-off state detection circuit, and AND₂ outputs the low-level voltage. The SiC device is in the turn-off delay stage, Both the dI_d/dt detection circuit and the dV_ds/dt detection circuit have no induction signal output.

(2) During the voltage rising stage (t₆–t₇), when the gate voltage satisfies the math condition (V_r5 < V_gs < V_r4), the AND₂ of the turn-off detection circuit outputs high-level voltage. The drain-source voltage V_ds rises rapidly, and the dV_ds/dt detection circuit generates an induced signal. The induced voltage signal is greater than the threshold voltage V_r6 after being divided by the resistor R₃ and R₄, and the comparator OP₆ outputs high-level voltage. Then, the AND₄ receives two high-level signals and outputs high-level voltage. After the push–pull amplifier circuit increases the current, the MOS₂ is controlled to be turned on, the current injection circuit is turned on, and I_g2 is injected into the gate terminal. At the moment, the gate current is −I_g + I_g2, so the corresponding turn-off voltage overshoot is reduced.

(3) During the voltage oscillation stage (t₇–t₈), after the rising stage of V_ds, V_ds tends to stabilize after oscillating. The dV_ds/dt detection circuit will output a high-level signal again during the oscillation process. However, V_gs is less than V_r5 after voltage division. The AND₄ outputs a low-level voltage, and MOS₂ is turned off in time. The current injection circuit is blocked, and the gate drive current returns to I_g.

(4) During the stage (t₈–t₉), when the device is fully turned off, V_ds and I_g tend to have a constant value, and the output of each detection circuit is low-level voltage. At this time, the control circuit does not work, and MOS₂ remains in the turn-off state.

5. Experimental Results and Analysis

To substantiate the efficacy of the AGD circuit designed and proposed in this paper, an experimental setup of the double-pulse topology was established, as shown in Figure 7a. The SiC MOSFET module model was CAS300M12BM2, with its parameters provided in

Table 1. The parameter values for the CAS300M12B2M module.

Parameter	Value
Threshold gate voltage Vth	2.3 V
Reverse recovery charge of the anti-parallel diode Qrr	1.2 μC
Drain-gate parasitic inductance Ld	4 nH
Kelvin source parasitic inductance LsS	2.4 nH
Total parasitic inductance of the power circuit Lloop	48 nH

. The oscilloscope was a Tektronix MDO3024. A DSP28335 control board was utilized to produce the double-pulse signal, and the load inductance value was 48.5 μH. The proposed active gate drive circuit, as shown in Figure 7b, includes the detection and control circuit for the turn-on and turn-off processes, and the SiC MOSFET module is soldered under the circuit board.

The models of the devices adopted in the AGD are listed in

Table 2. Models of devices used in the IC.

Device	Model
Comparator	TLV3501AI, TLV3502AI
Logical AND	SNL17SZ08DFT2G
Amplifier	2N2222A, 2N2907A
MOS1 and MOS2	BSR302N, BSS308PE

.

The experiment compared the current, voltage overshoot, oscillation and losses during the switching process for the proposed AGD and the conventional drive circuit (CGD) under different DC bus voltage levels, gate resistance and load current conditions. A total of nine groups of experimental operation conditions were established in this study, as shown in

Table 3. Experimental operation conditions.

Number	Gate Resistance (Ω)	Bus Voltage (V)	Load Current (A)
1	3	300	110
2	6.8	300	110
3	10	300	110
4	6.8	200	75
5	6.8	350	130
6	6.8	400	145
7	6.8	300	45
8	6.8	300	70
9	6.8	300	140

.

5.1. Comparative Analysis of Different Gate Resistances

To validate the effectiveness of the proposed AGD circuit under different gate resistance conditions, the experimental conditions were set as follows: bus voltage 300 V, load current 110 A, and three different gate resistances of 3 Ω, 6.8 Ω and 10 Ω, respectively. Under the same operating conditions, the experimental waveforms of I_d, V_ds and V_gs under the proposed AGD circuit and under the CGD are as shown in Figure 8.

Figure 8a~f demonstrate that the proposed AGD has a significant suppression effect on overshoot and oscillation under different gate resistances. Among them, when the gate resistance is 3 Ω, the peak of I_d decreases from 187 A to 151 A. When the SiC MOSFET is turned off, the peak of V_ds decreases from 374 V to 354 V. When R_g is set as 6.8 Ω and 10 Ω, the current overshoot decreases by 27 A (44.3%) and 24 A (53.3%), respectively. The voltage overshoot decreases by 28 V (53.8%) and 24 V (52.1%), respectively. Meanwhile, the current and voltage of AGD can be quickly restored to steady state, with a smaller oscillation amplitude and shorter oscillation time.

5.2. Comparative Analysis of Different Voltage Levels

To verify that the designed active drive circuit has superiority at different voltage levels, the gate resistance was set to 6.8 Ω, the DC-bus voltage levels were set to 200 V, 300 V, 350 V, and 400 V, and the corresponding load currents were 74 A, 110 A, 129 A, and 147 A, respectively. The experimental results for AGD and CGD are shown in Figure 9a~f.

Figure 9a~f and Figure 8c,d illustrate that under the four different voltage level conditions, in the turn-on process, compared to CGD, the current overshoot of AGD decreases by 19 A, 26 A, 26 A, and 25 A, respectively, with an average decrease of 40.4%. In the turn-off process, compared to CGD, the suppression effect on the current and voltage oscillation is obvious.

5.3. Comparative Analysis of Different Load Current

To verify that the proposed AGD circuit is effective under various load current conditions, the gate resistance and DC-bus voltage were set as 6.8 Ω and 300 V, respectively. Four different load currents of 45 A, 70 A, 110 A, and 140 A were obtained by changing the first pulse time. The results of the comparative experiment are depicted in Figure 10a~f.

Figure 10a~f and Figure 9c,d indicate that under the same gate resistance and bus voltage conditions, the current and voltage overshoot, oscillation amplitude, and oscillation time under the proposed AGD are significantly smaller than those under CGD. During the turn-on process, compared to CGD, the current overshoot of AGD decreases by 15 A, 20 A, 27 A and 26 A, respectively, with an average decrease of 39.1%. In the turn-off process, the voltage overshoot decreases by 12 V, 24 V, 28 V and 32 V, respectively, with an average decrease of 48.9%.

5.4. Comparative Analysis of Switching Loss under Different Conditions

The switching loss comparisons under different gate resistances are shown in Figure 11. Based on three group experiments under the same gate resistance condition, compared with CGD, the average switching loss of the proposed AGD only increased by 26.41%. Comparing Figure 8a with Figure 8e, it should be noted that the current suppression effect of the proposed AGD under R_g = 3 Ω, was the same as that of CGD under R_g = 10 Ω. However, the switching loss was 20.4 mJ, increasing by 46.76%.

5.5. Comparative Analysis of EMI

By reducing the overshoot of I_d and V_ds during the turn-on and turn-off stages, the emission of high-frequency electromagnetic interference from the SiC MOSFET can be reduced. Under the conditions of V_ds = 300 V, I_d = 110 A, and R_g = 6.8 Ω, the spectrum analysis and comparison results for I_d and V_ds under the AGD and CGD circuits are as presented in Figure 12 and Figure 13, respectively. It is obvious that the current and voltage oscillations of CGD all generate spikes around 7.3 MHz, and the positions of the spikes are basically consistent with the oscillation frequency. However, the spectrum amplitude of AGD is significantly reduced, which verifies that the proposed AGD circuit can effectively mitigate electromagnetic interference in the SiC MOSFET switching process.

6. Conclusions

Based on the switching transient state feedback, an active gate drive (AGD) circuit for SiC MOSFETs was proposed in this paper. Experimental results showed that the proposed AGD circuit can effectively reduce the overshoot and oscillations of the SiC MOSFET drain current and drain-source voltage. The following conclusions were formed:

(1)

This paper proposes a high-precision transient detection method. The gate voltage and change rate of the drain current together serve as the basis for determining the current rise stage during the turn-on process, and the gate voltage and change rate of the drain-source voltage together serve as the basis for determining the voltage-rising stage during the turn-off process.

(2)

This experiments in this paper only reduced the gate drive current during the current-rising stage, injected the gate current during the voltage-rising stage, and did not perform any operations during other stages of the switching process. Therefore, as the experimental results indicate, without affecting the switching speed, the overshoot and oscillation of the drain current and drain-source voltage can be effectively suppressed.

(3)

The AGD scheme proposed in this paper has a simple structure and strong universality, eliminating the need for a digital signal processor. The resistance of the current extraction circuit and current injection circuit and the threshold voltage can be adjusted to satisfy the requirements of the switching speed, switching loss, current and voltage overshoot.