Research on Current Distribution Strategy Based on Interleaved Double Boost Converter

Abstract

In the new energy DC microgrid system, most of the new energy outputs DC power with a low voltage level and a large fluctuation range, which cannot be directly connected to the network. It needs to be boosted by a DC–DC converter, then connected to the power grid or supplied with a DC load. On the premise that the traditional DC–DC converter cannot meet the requirements of high-power applications, the interleaved dual boost converter (IDBC) has been widely used because of its low input current ripple, low device stress and high-power density. It is necessary to maintain the current balance of each phase of the converter during a heavy load and to improve the efficiency during a light load. This paper analyzes the working principle of the six-phase IDBC and reduces the high order model to the low order model according to the symmetry. Due to the current imbalance caused by the mismatch of the parasitic parameters of each phase, two current distribution strategies are designed for different operating. To balance the current of each phase when the converter is overloaded, the relationship between the phase current, parasitic parameters and duty cycle is analyzed based on the state space average method. The estimated parasitic parameters are used to obtain the duty cycle compensation of each phase to eliminate the current imbalance. In addition, to improve the overall efficiency of the converter when the converter connects with a light load, the optimal power distribution coefficient is obtained according to the parasitic parameters to achieve the optimization of the input power, so as to improve the efficiency of the converter. Finally, the simulation results verify the feasibility and effectiveness of the proposed control strategy.

1. Introduction

With the development of new energy technology, more and more photovoltaic, wind energy and fuel cells are connected to the microgrid [1]. In order to integrate the new energy power generation unit with a low output voltage into the microgrid, DC–DC converters are required to increase the output voltage. The IDBC has a high gain, which can be employed as the bridge between the source networks. The IDBC parallels several basic Boost topology inputs and outputs, which reduces the voltage stress on the switch tubes and other devices [2]. It has the characteristics of a low input current ripple and a small switching loss of the switch tubes. In addition, the duty cycle of the IDBC can be adjusted in the range of 0~1. The current stress and voltage stress of each device are balanced, which can be expanded to a multi-phase structure, suitable for large and medium power occasions.

The topology improvement of IDBC mainly focuses on the voltage gain by combining with other Boost technologies [3]. Some scholars introduced coupling inductors into traditional structures [4], which combines coupling inductors with voltage doubling units to further reducing the voltage stress of diodes. However, if the coupling inductor is used at the input port when the turn ratio is large, the input current is discontinuous, and additional passive components are required to smooth the input current waveform. By adding a capacitor on the basis of the original topology, the input and output share a ground [5]. The method of integrating a voltage multiplier and transformer in topology is presented by [6]. The voltage multiplier can be driven by a single transistor and used to increase the voltage gain of the converter, but the introduction of a high-frequency transformer and voltage multiplier unit increases the size and cost of the converter.

Current distribution shall be considered for the polyphase converter to make each phase device work near the rated operating point and reduce the possibility of converter failure [7]. However, in practical applications, due to uncontrollable factors such as measurement errors and device differences, the current of each phase of the converter cannot be completely equal, and the parasitic parameters of each phase are also different. So, the external characteristics are different. The common current sharing methods can be divided into the droop method and active current sharing method according to whether there is a current sharing bus [8]. The droop control makes the characteristic curve of each phase approach the same through the slope of the load regulation characteristic curve. The droop control is simple and does not require interconnected communication, but the regulation characteristic is poor [9]. In contrast, the active current sharing method has a better current adjustment capability and is suitable for various applications [10]. The outer loop of the current sharing control method is a voltage droop control for embedding virtual impedance, and the inner loop is the PI control, which can improve the dynamic and stable performance of the system. An improved independent current sharing method is proposed by [10]. By designing the current sharing ring in the voltage ring, the limitation caused by the small bandwidth of the voltage ring is reduced, and a good dynamic current sharing effect is achieved. Aiming at the problem of a secondary voltage drop and the uneven current of a parallel converter, ref. [11] proposes a method to realize current sharing by actively detecting the line impedance to compensate for the virtual impedance coefficient. An algorithm for compensating the current imbalance caused by resistance mismatch is proposed by [12]. This method estimates the degree of parameter mismatch by disturbing one phase duty cycle and measuring the deviation of other phases duty cycle. Finally, the current equalization control is realized by using the adaptive compensation coefficient. Moreover, a current sensorless control method is proposed [13]. The parasitic resistance of each phase is estimated in advance, and the compensation amount of the duty cycle of each phase was calculated. The voltage of switching nodes was changed to achieve a current sharing control. Taking the equivalent transfer function of a single module as the controlled object [14], a robust H ∞ loop is introduced into the design of the current sharing loop controller to improve the dynamic current sharing and anti-interference performance.

The current sharing control of the polyphase converter does not take into account the overall efficiency. Different phase parameters mean different efficiency characteristics. Therefore, the current sharing control cannot optimize the efficiency of the converter, especially under light load conditions [15]. To solve the problem of a low efficiency under light load conditions, the method of reducing the number of operating phases of the converter can be effectively suppressed [16], but this method is only applicable to converters with a large number of phases. The use of multiple converters can improve the overall efficiency [17]. Except that one converter works at a non-optimal working point, the rest work at the working point with the maximum efficiency to improve the overall efficiency. However, how to obtain the optimal selection of the converter in real time is not specifically given in the paper. Game theory is introduced into the study of efficiency optimization strategies [18,19,20] analyzed the efficiency characteristics of the system operation and they studied the impact of the circuit parameter differences on the overall efficiency. The efficiency characteristics of a single power source are obtained through the least square method. The genetic algorithm with mutation is used to solve the optimal value problem. Although the overall efficiency is improved, the control complexity is greatly increased. A hybrid power allocation method [21] is proposed for the input parallel output parallel converter, which has two working modes: in the steady state, a master–slave control is used to enhance the power loss allocation ability and reduce the loss concentration to improve the overall efficiency. Under the transient condition, when the output voltage exceeds the threshold value, interleaving control is adopted to improve the dynamic response ability and avoid the current oscillation between converters.

Based on the actual demand, this paper designs two current distribution strategies for different working conditions, and the main contributions are as follows:

• For heavy loaded converters, each phase current should be balanced. A current sharing control based on duty cycle compensation is proposed. Using the state space average method, the relationship among the current, parasitic parameters and duty cycle of each phase is derived. The duty cycle compensation amount of each phase is derived to achieve the current sharing control.
• Aiming for the low efficiency of the converter under a light load, a current distribution strategy of the energy outer loop current inner loop is designed, and the energy model of the IDBC is established. The overall efficiency of the converter is improved by adjusting the power distribution coefficient.

The rest of this paper is organized as follows: Section 2 introduces the modeling and principle analysis and Section 3 introduces the proposed model and traditional methods, in which Section 3.1 establishes the parasitic parameter estimation and Section 3.2 derives the duty cycle compensation. Section 4 establishes the allocation strategy based on efficiency optimization, in which Section 4.1 and Section 4.2, respectively, design the energy outer loop and current inner loop. In Section 4.3, the optimal power allocation is designed to improve the efficiency according to the difference in the power efficiency characteristics of each phase. In Section 5, the simulation and experimental verification are carried out. Section 6 summarizes the advantages and feasibility of the strategy proposed in this paper and gives the future research direction.

2. Modeling and Principle Analysis

The structure of the six-phase staggered double boost converter is shown in Figure 1, where $V_{in}$ is the input voltage and $R$ is the load. The converter consists of two modules, one is the upper module and the other is the lower module. Module A consists of three basic Boost cells and capacitor $C_a$, and the inductor $L_{a1}$, switch tube $S_{a1}$ and diode $D_{a1}$ are the first phase of module A, while the other two phases have similar structures: the structure of module B is symmetrical with that of module A, which is composed of three floating ground Boost units and capacitor $C_b$. The inductor $L_{b1}$, switch tube $S_{b1}$ and diode $D_{b1}$ are the first phase of module B, and the other two phases are similar: the input ends of the two modules are connected in parallel, and the output end is floating to the ground.

In order to simplify the analysis of the working principle, each inductance is assumed to be equal and large. The duty cycle d of all the six switch tubes is equal. Capacitance $C_a$ and $C_b$ are equal, and the voltages of the two capacitors are equal. The traditional interleaving technology is used to control the switches of the IDBC.

To reduce the input current ripple, the six-phase interlaced dual boost converter uses the traditional interlaced parallel technology to control the switch tube. The three-phase conduction sequence of module A is 120 degrees different in the phase order, and the three-phase conduction sequence of module B is 120 degrees different in the phase order. At the same time, the conduction phase of Sb1 is 60 degrees behind that of Sa1, that is, Sa1, Sb1, Sa2, Sb2, Sa3 and Sb3 are opened at 0, TS/6, TS/2, 2TS/3 and 5TS/6, respectively. Thus, the inductance current ripple of each phase can be offset by overlapping them. There are 12 operating modes in a switching cycle. When the duty cycle d is in different intervals, the operating state of the converter will be different.

The analysis and design are carried out in the range of 1/2 < d < 2/3. Considering the influence of the parasitic parameters on the inductance current in the six-phase staggered double boost converter, the parasitic parameters are added to the ideal model of the converter. The equivalent circuit is shown in Figure 2. In addition to their own characteristics, the inductance and capacitance in the figure mainly considers the influence of parasitic resistance. To simplify the analysis, it is assumed that the inductance and parasitic resistance of each phase of the converter are the same, the parasitic parameters of the switch are the same and the parasitic parameters of the diode are also the same Figure 3.

The state space average method is used to express the above 12 modes:

$$\dot{x}=A_{k}x+B_{k}u (k=1,2,\mathrm{...12})$$

(1)

where the state vector of the system $x={\left[i_{a1},i_{a2},i_{a3},v_a,i_{b1},i_{b2},i_{b3},v_b\right]}^T$; the independent source vector $u={\left[V_{in},V_S,V_D,I_o\right]}^T$; and the sum coefficient matrix $A_k=\left[\begin{array}{ll}{A}_k^a& 0\\ 0& A_k^b\end{array}\right]$, $A_k=\left[\begin{array}{ll}{A}_k^a& 0\\ 0& A_k^b\end{array}\right]$.

Assume that the six of the upper and lower modules correspond to 1–6 phases, then the duty cycle of each phase is $d_1$, $d_2$, $d_3$, $d_4$, $d_5$ and $d_6$. The circuit state is averaged in a cycle:

$$\dot{x}=Ax+Bu$$

(2)

The stable operating point of the converter $X=-A^{-1}BU$ can be obtained according to x = 0. Equation (2) can be rewritten as:

$$I_i=2\frac{{\displaystyle \sum _{k=1,k\ne i}^6\left[R_k({\displaystyle \sum _{l=1,l\ne k}^6(V_l-V_D)}\right]+I_o{\displaystyle \prod _{k=1,k\ne i}^6{R}_k}}}{{\displaystyle \sum _{m=1}^6{\displaystyle \sum _{n=1,m\ne n}^6(}{R}_m{R}_n)}}(i=1,2,\mathrm{...6})$$

(3)

where $V_i=\frac{V_{in}-d_i{V}_S-{\overline{d}}_i{V}_D}{{\overline{d}}_i}$, $R_i=\frac{d_i{r}_S-r_i-{\overline{d}}_i{r}_D}{{\overline{d}}_i}$. According to Equation (3), the phase current of the converter is not only determined by its own parameters and duty cycle, but also affected by the other parasitic parameters and the duty cycle.

3. The Proposed Model and Conventional Method

In order to restrain the influence of the parasitic parameter difference in each phase on each phase current, the current stress borne by each phase is limited. In this paper, a current sharing strategy based on duty cycle compensation is proposed. The duty cycle compensation is derived by using the relationship between the six-phase inductance current value and the parasitic parameters of the converter. Through an online parameter estimation, the compensation is introduced into the voltage control to achieve the current sharing control.

3.1. Parasitic Parameter Estimation

In order to eliminate the influence of the inconsistent device’s parasitic parameters on the average current distribution of the converter, it is necessary to compensate the duty cycle of each phase. Assume that:

$$\begin{array}{l}{d}_i=d_1-\mathsf{\Delta }{d}_i(i=2,3,\mathrm{...6})\\ I_1=I_2=I_3=I_4=I_5=I_6\end{array}$$

(4)

where phase a1 is taken as the reference phase and the other five are, respectively, compensated duty cycles.

Combining Equation (3) with Equation (4), the duty cycle $\mathsf{\Delta }{d}_i$ can be obtained:

$$\mathsf{\Delta }{d}_i=\frac{I_o(R_i-R_1)}{3V_{in}+I_o(R_1/{\overline{d}}_1-R_i/{\overline{d}}_i)}$$

(5)

Considering $3V_{in}\gg I_o(R_1/{\overline{d}}_1-R_i/{\overline{d}}_i)$, the above equation can be further simplified as:

$$\mathsf{\Delta }{d}_i=\frac{I_o(R_i-R_1)}{3V_{in}}$$

(6)

According to Equation (6), the duty cycle compensation of each phase can be directly obtained after measuring and estimating the input voltage, output current and parasitic parameters of each phase. The average distribution of each phase current can be achieved by adding the compensation amount to the duty cycle of the voltage controller output.

According to the above analysis, the compensation amount of each phase duty cycle needs to be calculated according to the value of the parasitic parameters of each phase. By connecting a resistance in series with each phase to equivalent the parasitic parameters of the phase and connecting a resistance in parallel at both ends of the capacitor to equivalent the residual loss [22] of the module, the equivalent circuit of the six-phase staggered double boost converter is obtained, as shown in Figure 4.

Since the input power should follow the reference value, the series equivalent parasitic resistance can be estimated by the following formula:

$$\begin{array}{l}\frac{d{\widehat{R}}_{Sak}}{dt}={\lambda }_S({\widehat{P}}_{outak}-P_{outak}){\left(\frac{V_{in}}{P_{inak}}\right)}^2\\ \frac{d{\widehat{R}}_{Sbk}}{dt}={\lambda }_S({\widehat{P}}_{outbk}-P_{outbk}){\left(\frac{V_{in}}{P_{inbk}}\right)}^2\end{array}$$

(7)

where ${\lambda }_S$ is the convergence coefficient of the equivalent series resistance. The output power of each phase $P_{outak}$ and $P_{outbk}$ and its estimated value ${\widehat{P}}_{outak}$ and ${\widehat{P}}_{outbk}$ can be obtained from the following:

$$\begin{array}{l}{P}_{outak}=(1-d_{ak})V_a{i}_{ak} \\ {\widehat{P}}_{outak}=P_{inak}-{\widehat{R}}_{Sak}{\left(\frac{P_{inak}}{V_{in}}\right)}^2\\ P_{outbk}=(1-d_{bk})V_b{i}_{bk} \\ {\widehat{P}}_{outbk}=P_{inbk}-{\widehat{R}}_{Sbk}{\left(\frac{P_{inbk}}{V_{in}}\right)}^2\end{array}$$

(8)

Similarly, since the output voltage should follow the voltage reference value, the parallel equivalent parasitic resistance can be estimated by Equation (9):

$$\begin{array}{l}\frac{d{\widehat{R}}_{Pa}}{dt}={\lambda }_P({\widehat{i}}_{da}-i_{da})\frac{{\widehat{R}}_{{}_{Pa}}^2}{V_a}\\ \frac{d{\widehat{R}}_{Pb}}{dt}={\lambda }_P({\widehat{i}}_{db}-i_{db})\frac{{\widehat{R}}_{{}_{Pb}}^2}{V_b}\end{array}$$

(9)

where ${\lambda }_P$ is the convergence coefficient of the parallel resistance. The estimated values of current and the input power can be obtained from the following formula:

$$\begin{array}{l}{i}_{da}={\displaystyle \sum _{k=1}^3(1-d_{ak})i_{ak}} , {\widehat{i}}_{da}=i_o+\frac{V_a}{{\widehat{R}}_{Pa}}\\ i_{db}={\displaystyle \sum _{k=1}^3(1-d_{bk})i_{bk} , {\widehat{i}}_{db}=i_o+\frac{V_b}{{\widehat{R}}_{Pb}}}\end{array}$$

(10)

3.2. Life Science Identifiers

Due to the existence of the switch, the converter is considered as a nonlinear system, and the process of switching between different modes can be considered as a linear system. Based on this characteristic, the linearized small signal model can be obtained by establishing the average value model and perturbation method, making a small perturbation near the stable working point and decomposing the average value component into the DC term and AC term.

According to Figure 4, the average model of the converter with the parasitic parameters can be obtained:

$$\left\{\begin{array}{l}{L}_{ak}\frac{d{i}_{ak}}{dt}=V_{in}-R_{Sak}{i}_{ak}-{\overline{d}}_{ak}{v}_a ,C_a\frac{d{v}_a}{dt}={\displaystyle \sum _{k=1}^3{\overline{d}}_{ak}{i}_{ak}-i_o-\frac{v_a}{R_{Pa}} }\\ L_{bk}\frac{d{i}_{bk}}{dt}=V_{in}-R_{Sbk}{i}_{bk}-{\overline{d}}_{bk}{v}_b ,C_b\frac{d{v}_b}{dt}={\displaystyle \sum _{k=1}^3{\overline{d}}_{bk}{i}_{bk}-i_o-\frac{v_b}{R_{Pb}} }\end{array}\right.$$

(11)

Add a small disturbance at the stable working point:

$$\begin{array}{l}{i}_{ak}=I_{ak}+{\widehat{i}}_{ak}(t),i_{bk}=I_{bk}+{\widehat{i}}_{bk}(t)\\ v_a=V_a+{\widehat{v}}_a(t),v_b=V_b+{\widehat{v}}_b(t)\\ d_{ak}=D_{ak}+{\widehat{d}}_{ak}(t),d_{bk}=D_{bk}+{\widehat{d}}_{bk}(t)\\ i_o=I_o+{\widehat{i}}_o(t)\end{array}$$

(12)

where $I_{ak}$, $I_{bk}$, $V_a$, $V_b$, $D_{ak}$ and $D_{bk}$ are the direct flow and ${\widehat{i}}_{ak}(t)$, ${\widehat{i}}_{bk}(t)$, ${\widehat{v}}_a(t)$, ${\widehat{v}}_b(t)$, ${\widehat{d}}_{ak}(t)$ and ${\widehat{d}}_{bk}(t)$ are corresponding to the AC flow. Substitute Equation (12) into Equation (11):

$$\left\{\begin{array}{l}\begin{array}{l}{L}_{ak}\frac{d[I_{ak}+{\widehat{i}}_{ak}(t)]}{dt}=V_{in}-R_{Sak}[I_{ak}+{\widehat{i}}_{ak}(t)]-[{\overline{D}}_{ak}-{\widehat{d}}_{ak}(t)][V_a+{\widehat{v}}_a(t)] ,\\ C_a\frac{d[V_a+{\widehat{v}}_a(t)]}{dt}={\displaystyle \sum _{k=1}^3[{\overline{D}}_{ak}-{\widehat{d}}_{ak}(t)][I_{ak}+{\widehat{i}}_{ak}(t)]-[I_o+{\widehat{i}}_o(t)]-\frac{V_a+{\widehat{v}}_a(t)}{R_{Pa}} }\end{array}\\ \begin{array}{l}{L}_{bk}\frac{d[I_{bk}+{\widehat{i}}_{bk}(t)]}{dt}=V_{in}-R_{Sbk}[I_{bk}+{\widehat{i}}_{bk}(t)]-[{\overline{D}}_{bk}-{\widehat{d}}_{bk}(t)][V_b+{\widehat{v}}_b(t)] ,\\ C_b\frac{d[V_b+{\widehat{v}}_b(t)]}{dt}={\displaystyle \sum _{k=1}^3[{\overline{D}}_{bk}-{\widehat{d}}_{bk}(t)][I_{bk}+{\widehat{i}}_{bk}(t)]-[I_o+{\widehat{i}}_o(t)]-\frac{V_b+{\widehat{v}}_b(t)}{R_{Pb}} }\end{array}\end{array}\right.$$

(13)

To simplify the calculation, we assume the following:

$L_{ak}=L_{bk}=L$, $I_{ak}=I_{bk}=I$, $i_{ak}(t)=i_{bk}(t)=i(t)$, $C_a=C_b=C$, $V_a=V_b=V$, $v_a(t)=v_b(t)=v(t)$, $R_{Sak}=R_{Sbk}=R_S$, $R_{pa}=R_{pb}=R_p$, $D_{ak}=D_{bk}=D$, $d_{ak}(t)=d_{bk}(t)=d(t)$.

By Laplace transformation of the above equation:

$$\left\{\begin{array}{l}sL\widehat{i}(s)=-R_S\widehat{i}(s)-\overline{D}\widehat{v}(s)-V\widehat{d}(s)\\ sC\widehat{v}(s)=3(\overline{D}\widehat{i}(s)-I\widehat{d}(s))-{\widehat{i}}_o(s)-\frac{\widehat{v}(s)}{R_P}\end{array}\right.$$

(14)

The transfer function of the capacitor voltage and duty cycle of the converter considering the parasitic parameters is further simplified:

$$G_{vd}(s)=\frac{v(s)}{d(s)}=-\frac{3R_{P}LIs+3I{R}_S{R}_P+3R_P(1-d)V}{R_{P}LC{s}^2+(R_P{R}_{S}C+2L)s+2R_S+3R_P{(1-d)}^2}$$

(15)

Double-pole double-zero compensation is selected in this paper, which also has a good suppression effect on the high-frequency interference, so it is often used in voltage control or the direct duty cycle control.

The current sharing control block diagram based on the duty cycle compensation is shown in Figure 5. $G_c$ is the transfer function of the voltage control, $G_{vd}$ is the transfer function of the capacitor voltage to the duty cycle and $G_m$ is the transfer function of the modulator. The transfer function is as follows:

$$G_c(s)=\frac{K(1+s/{\omega }_{z1})(1+s/{\omega }_{z2})}{s(1+s/{\omega }_{p1})(1+s/{\omega }_{p2})}$$

(16)

In order to improve the dynamic response of the system, the crossing frequency of the compensated system transfer function is set to 300 Hz. One of the three poles is fixed and set at zero to improve the low-frequency gain; two zeros can eliminate the phase lag caused by the double poles of the controlled object; and the two poles are set at the switching frequency of 20 kHz to accelerate the attenuation speed of the high-frequency terminal and improve the anti-interference capability.

According to Equations (5) and (6), the compensation amount of duty cycle can be obtained by sampling the values of the load current and input voltage and combining the estimated parasitic parameters.

4. Current Distribution Strategy Based on Efficiency Optimization

In order to maximize the efficiency of the six-phase staggered double boost converter, a double loop control of the energy outer loop current inner loop is designed. The energy loop control is to derive the energy model through the differential flatness of the converter, so as to convert the voltage regulation into the power control. The current loop is to ensure that the current of each phase can be distributed with an optimal efficiency. The specific control block diagram is shown in Figure 6.

4.1. Energy Outer Ring Design

Differential flatness theory is a concept of nonlinear systems, which reveals the structural property of nonlinear systems. In general, many nonlinear systems are differential flat. As long as a set of output vectors of the system can be found so that both the input vector and the state vector of the system can be represented by the set of the output vectors and their finite order derivatives, the system is a differential flat system, and the output vector is a flat output (Xu Liangcai et al., 2010). Nonlinear systems are defined as:

$$\left\{\begin{array}{l}\dot{x}=f(x,u),x\in R^n,u\in R^n\\ y=g(x)\end{array}\right.$$

(17)

If an output vector $z=h(x,u,\dot{u},\dots ,u^{(l)})$ can be found so that both the state vector and the input vector can be represented by the quantity and its finite order differential, then the system is differential flat.

First, judge whether the system is a differential flat system, make the state vector be two capacitor voltages $x={\left[x_1,x_2\right]}^T={\left[V_a,V_b\right]}^T$ and the input vector be the input power of the two modules $u={\left[u_1,u_2\right]}^T={\left[P_{ina},P_{inb}\right]}^T$. Select the energy of the two capacitors $z={\left[z_1,z_2\right]}^T={\left[E_1,E_2\right]}^T$ as the flat output, namely:

$$z={\left[z_1,z_2\right]}^T={\left[\frac{1}{2}{C}_a{V}_a^2,\frac{1}{2}{C}_b{V}_b^2\right]}^T$$

(18)

Expand the above equation:

$$x={\left[\sqrt{\frac{2z_1}{C_a}},\sqrt{\frac{2z_2}{C_b}}\right]}^T=\phi (z)$$

(19)

According to the equivalent circuit of the converter considering the parasitic parameters, it can be obtained that:

$$\dot{z}={\left[P_{outa}-P_{loada}-\frac{V_a^2}{R_{Pa}},P_{outb}-P_{loadb}-\frac{V_b^2}{R_{Pb}}\right]}^T$$

(20)

where $P_{outa}=P_{ina}-{{\displaystyle \sum _{k=1}^3{R}_{Sak}({\alpha }_{ak}\frac{P_{ina}}{V_{in}})}}^2,P_{outb}=P_{inb}-{{\displaystyle \sum _{k=1}^3{R}_{Sbk}({\alpha }_{bk}\frac{P_{inb}}{V_{in}})}}^2$, ${\alpha }_{ak}$ and ${\alpha }_{bk}$ are the power distribution coefficients of the two modules. Equation (20) can be derived as follows:

$$u=\psi (z,\dot{z})$$

(21)

The above analysis verifies that the system is a differential flat system with capacitor energy as the flat output.

Due to the symmetry of the topology, the energy models of the upper and lower modules are integrated into:

$$\begin{array}{l}E=\frac{1}{2}{C}_a{V}_a^2+\frac{1}{2}{C}_b{V}_b^2\\ \dot{E}=P_{out}-P_{load}-\frac{V_a^2}{R_{Pa}}-\frac{V_b^2}{R_{Pb}}\end{array}$$

(22)

To ensure that the capacitor energy can track the reference value, the following second-order controller is adopted:

$$\left({\dot{E}}_{ref}-\dot{E}\right)+2{\xi }_E{\omega }_E\left(E_{ref}-E\right)+{\omega }_E^2{\displaystyle \int \left(E_{ref}-E\right)dt}=0$$

(23)

When the energy regulation coefficient ${\xi }_E,{\omega }_E>0$, the controller can reach a stable state at the working point.

Similarly, integrate the power of the upper and lower modules:

$$P_{out}=P_{in}-{\displaystyle \sum _{k=1}^6{R}_{Sk}{({\alpha }_k\frac{P_{in}}{V_{in}})}^2}$$

(24)

Wherein, ${\alpha }_k$ is the power distribution coefficient of each phase, which can be adjusted to maximize the efficiency of the converter. The power distribution coefficient shall meet ${\displaystyle \sum _{k=1}^6{\alpha }_k=1}$. In order to obtain the reference value of the input power, Equation (24) can be rewritten as:

$$P_{in}=\frac{V_{in}^2-\sqrt{V_{in}^4-4V_{in}^2{P}_{out}{\displaystyle {\sum }_{k=1}^6{\alpha }_k^2{R}_{S_k}}}}{2{\displaystyle {\sum }_{k=1}^6{\alpha }_k^2{R}_{S_k}}}$$

(25)

By using the above formula, the reference value of the output power can be obtained from the reference value of the capacitor voltage, and then the reference value of the input power can be derived. The design of the energy loop control can be realized.

4.2. Current Inner Loop Design

The reference value of each phase current is obtained based on the power reference value output by the energy loop:

$$i_k^{ref}={\alpha }_k\frac{P_{in}^{ref}}{V_{in}}$$

(26)

The control objective of the current inner loop is to make each phase current track the reference current and adopt the sliding mode control with a good robustness, such as the sliding mode surface:

$$s_k=\left(i_k-i_k^{ref}\right)+k_{ik}{\displaystyle \int \left(i_k-i_k^{ref}\right)dt}$$

(27)

The derivative of the sliding mode surface is derived. When ${\dot{s}}_k=-{\lambda }_{ik}{s}_k$, the phase current will track its reference current. Equation (27) can be modified as follows:

$${\dot{e}}_k+(k_i+{\lambda }_i)e_k+k_i{\lambda }_i{\displaystyle \int e_{k}dt}=0$$

(28)

where $k_i$ and ${\lambda }_i$ are current regulation coefficients. The current regulation frequency ${\omega }_i^2=k_i{\lambda }_i$.

The duty cycle can be obtained from the reference value of each phase current:

$$\begin{array}{l}{d}_{ak}=1+\frac{1}{V_a}\left[R_{Sak}{i}_{ak}-V_{in}+L_{ak}\left(-{\lambda }_i{s}_{ak}\right)+\frac{d{i}_{ak}^{ref}}{dt}-k_i(i_{ak}-i_{ak}^{ref})\right]\\ d_{bk}=1+\frac{1}{V_b}\left[R_{Sbk}{i}_{bk}-V_{in}+L_{bk}\left(-{\lambda }_i{s}_{bk}\right)+\frac{d{i}_{bk}^{ref}}{dt}-k_i(i_{bk}-i_{bk}^{ref})\right]\end{array}$$

(29)

Similar to the voltage and current double loop control, the energy and current double loop control should consider the bandwidth of the two controls. The adjustment coefficients of the energy loop and current loop designed in this paper should meet the following conditions, as shown in

Table 1. Controller parameters.

Controller	Parameter	Value
Energy loop	${\xi }_E$	0.7
	${\omega }_E$	100 rad/s
Current loop	$k_i$	2000 rad/s
	${\lambda }_i$	2000 rad/s
	${\omega }_i$	2000 rad/s

:

4.3. Optimal Power Allocation

The power distribution coefficient ${\alpha }_k$ of each phase of the energy current double loop control designed above is the same, and the power of each phase will be equally distributed. However, this distribution ignores the difference in the efficiency characteristics of each phase and cannot ensure the maximum efficiency of the converter. In order to improve the conversion efficiency of the six-phase staggered double boost converter, the power distribution coefficients of each phase need to be adjusted to achieve a power redistribution. It can be seen from Equation (25) that adjusting the power distribution coefficient can adjust the value of the input power reference value to achieve the optimal control of converter efficiency.

The current distribution problem for efficiency optimization is essentially a problem of finding the extreme value of the k-1 variable function. The gradient descent method is the most basic method for solving the extreme value of the multivariate function. The minimum value of the function can be obtained by solving the point with a zero gradient:

$$\frac{\partial P_{in}^{ref}}{\partial {\alpha }_k}=0 ,(k=1,2,\mathrm{...5})$$

(30)

By solving the above equation, it can be obtained that the optimal power distribution coefficient to minimize the reference value of input power is:

$${\alpha }_k^{opt}=\frac{{\displaystyle {\prod }_{\begin{array}{l}j=1\\ j\ne k\end{array}}^6{R}_{Sj}}}{{\displaystyle {\sum }_{i=1}^6{\displaystyle {\prod }_{\begin{array}{l}j=1\\ j\ne i\end{array}}^6{R}_{Sj}}}}$$

(31)

The optimal power distribution coefficient can be obtained from the above equation. In order to avoid extreme cases, the optimal power distribution coefficient is very small due to the low output power of the converter. When the optimal power distribution coefficient is lower than a certain value, the controller cuts off the phase with the largest series resistance in the two modules and improve the power distributed in each phase by reducing the number to achieve an efficiency optimization.

The efficiency of the converter under a light load can be improved by optimizing the power distribution. If the parameters of each phase are identical, the power distribution coefficient will also be identical; when the parameters of each phase are inconsistent, the phase has a greater equivalent series resistance. Thus, the phase with a lower efficiency has less power distributed, and vice versa. The overall efficiency of the converter can be improved by a power redistribution. This power distribution method makes the aging degree of each phase more consistent and further improves the ability of current sharing.

5. Simulation and Experiment

In order to verify the correctness of the current distribution strategy proposed in this chapter, a simulation model is built using Simulink, which is specifically divided into the following three parts: a parasitic parameter estimation, a current sharing control based on the duty cycle compensation and a current distribution strategy based on efficiency optimization. The simulation parameters are shown in

Table 2. Simulation parameters.

Parameter	Value
Input DC voltage Vin	100 V
Reference value of output voltage Vref	300 V
Reference value of capacitor voltage VCref	200 V
Inductance L	330 μH
Capacitance C	1410 μF
output power Po	30 kW
switching frequency fsw	20 kHz

.

The estimation of the parasitic parameters is the premise of the first two current distribution controls. In order to verify the convergence of the parameter estimation, 0.2 Ω, 0.4 Ω, 0.2 Ω, 0.1 Ω, 0.2 Ω and 0.5 Ω resistors are successively applied to the six phases of the converter, and two 100 Ω resistors are, respectively, applied to both ends of the two capacitors.

As shown in Figure 7, the six-phase equivalent series resistance is 0.2523 Ω, 0.4629 Ω, 0.2512 Ω, 0.151 Ω, 0.2531 Ω and 0.5697 Ω, respectively, and the estimated parallel resistance is 76.19 Ω and 75.68 Ω. It can be seen that the series resistance values of the first, third and fifth phases are basically the same, the resistance value of the second phase is about 0.2 Ω higher than that of the three phases, the resistance value of the fourth phase is about 0.1 Ω lower than that of the three phases and the resistance value of the sixth phase is about 0.32 Ω higher than that of the three phases, which is basically consistent with the difference value of the input resistance. This shows that the parameter estimation can accurately estimate the equivalent parasitic parameters of the converter, laying the foundation for the subsequent current distribution control.

In order to verify the current sharing effect of the control algorithm, the six-phase staggered double boost converter without a current sharing compensation and with a current sharing compensation will be simulated, respectively, and the reference value of the output voltage will suddenly change to verify the dynamic response capability of the voltage control. The output voltage waveform and six-phase current waveform are shown in Figure 8 and Figure 9.

As shown in Figure 8, the designed compensation voltage control can perform a fast tracking of the given value. The voltage overshoot is only about 5 V, and the adjustment time is only ten microseconds. It has a good dynamic response capability. At the same time, the addition of duty cycle compensation has no effect on the voltage control.

It can be seen from Figure 9 that, due to the imbalance of the parasitic parameters of each phase, the current of each phase will be obviously unbalanced without a current sharing compensation. The phase current of the phase with smaller parasitic parameters will be relatively larger, while the phase current of the phase with larger parasitic parameters will be smaller; when the reference value of the output voltage changes from 300 V to 350 V, this imbalance will be aggravated when the load current increases. If the converter works under a heavy load, some phase currents may exceed the limit value, causing the converter to stop working. After adding a duty cycle compensation, it is obvious that each phase can basically realize the average distribution of the current. When the load current changes, the current of each phase will quickly return to the same value under the current sharing control, which greatly improves the current sharing performance of the converter.

The final verification is the current distribution control based on efficiency optimization. The input voltage of the converter is set as 100 V, the output voltage is 300 V, the power carried is 5~12 kW and the parasitic parameters of each phase remain unchanged. The precondition of the current distribution control based on efficiency optimization is to use the parasitic parameters to estimate the value of the series resistance of each phase, and then calculate the power distribution coefficient of each phase.

Figure 10 shows the comparison between the current sharing control and the efficiency optimization control under the load of 9 kW. Before 0.3 s, the traditional current sharing control is adopted, that is, the power distribution coefficient of each phase is 1/6. It can be seen that the phase with a different efficiency has the same power distribution, and the efficiency of the converter is 81.56%; after 0.3 s, the optimal power distribution coefficients calculated from the parasitic parameters are put into operation, which are 0.1792, 0.0916, 0.1799, 0.3005, 0.1779 and 0.0709, respectively. When the equal power distribution coefficient becomes the optimal power distribution coefficient, it means that the reference value of the input power is minimized, which also means that the converter efficiency is optimal. As shown in

Table 3. Converter efficiency under different loads.

Load Power (kW)	Current Sharing Control Efficiency (%)	Efficiency Optimization Control Efficiency (%)	Efficiency Increment (%)
5	79.38	80.12	0.74
6	80.64	81.46	0.82
7	81.3	82.32	0.98
8	81.57	82.79	1.22
9	81.56	82.97	1.41
10	81.33	82.96	1.63
11	80.95	82.8	1.85
12	80.43	82.5	2.07

, the converter efficiency rises to 82.97%, 1.41% higher than the current sharing control. In fact, the efficiency is improved by transferring the power on the phase with a low efficiency to the phase with a high efficiency. By using this control method, the aging degree of each phase of the converter can reach the same level, and then the current sharing control efficiency of the converter in high power situations can be improved to a certain extent.

Table 3 shows the corresponding efficiency under the current sharing control and efficiency optimization control when the converter is loaded with different loads under light load conditions, as well as the improved efficiency after adopting efficiency optimization control. In order to have a more intuitive understanding of the efficiency characteristics of the converter under different loads, the curve in Figure 11 is drawn using Matlab according to the data in Table 3. The red line is the efficiency of the converter using the current sharing control, and the blue line is the efficiency after efficiency optimization. They correspond to the left coordinate axis, and the green line is the increased efficiency value, which corresponds to the right coordinate axis.

It can be seen from Figure 11 that when the output voltage is 300 V, the efficiency of the converter increases first and then decreases with the increase in the load power. The reason for this is that when the output current is especially small, the switching loss of the switch tube is mainly affected by the switching frequency, so it accounts for a large proportion of the total loss, so the efficiency will increase with the increase in the load; however, when the output current continues to increase, the conduction loss of the switch increases with the increase in the current, and its proportion in the total loss gradually increases, and the efficiency starts to decline. The efficiency curves under the two control methods confirm this. Similarly, with the increase in the load, the efficiency increment of the efficiency optimization control also increases, because the control method reduces the loss of parasitic resistance, and the loss will increase with the increase in the current.

6. Conclusions

In this paper, two current distribution strategies are designed for the six-phase staggered double boost converter. Generally, due to the inevitable difference in the parasitic parameters of each phase, the current of each phase will be unbalanced. Under the heavy load working conditions, the current stress borne by some phases is likely to exceed the limit value, thus reducing the service life of the converter. This paper first uses the relationship between the current value of the six-phase inductor of the converter and the parasitic parameters to derive the duty cycle compensation amount and it also introduces the compensation amount through an online parameter estimation to achieve the current sharing control.

Aiming at the low efficiency of the converter under a light load, a current distribution strategy of the energy outer loop current inner loop is designed, and the energy model of the converter is established. The overall efficiency of the converter is improved by adjusting the power distribution coefficient. Simulink is used to build corresponding simulation models to verify the feasibility and effectiveness of the above two current distribution controls.

The future research directions of this paper are as follows: there is still much room for improvement in the topology of the interleaved dual boost converter, such as adding auxiliary circuits to improve the voltage gain or using soft switching technology to reduce the switching loss of the converter, so as to further improve the efficiency [23,24].

This paper studies the current distribution strategies in two scenarios and does not study how and when to switch these two control methods, which is also the main research direction in the future.