A Modified Multi-Level Inverter System for Grid-Tied DES Applications

Abstract

Energy harvesting from renewable energy sources is trending in the world due to inventions in modern technology. This paper proposes a grid-tied single-phase modified W-type 81-level inverter. Inverter design equations to calculate various parameters, such as the number of voltage levels and the number of DC power sources, along with the feedback controller equations, are developed to integrate the proposed topology with an electric power grid. The modeling of the control system for the proposed topology is carried out in the synchronously rotating reference frame for single-phase systems. The PWM generation part of the proposed inverter system makes use of the binary search nearest level algorithm to efficiently track the grid voltage signal. The proposed system integrates the inverter with the grid without the need for an output filter. The efficiency analysis shows that the proposed system delivers active and reactive power to the grid with an efficiency of around 90% and a THD of 1.04%. The voltage and current waveforms for the dynamic active and reactive power flow reveal that the proposed system exhibits a good transient and steady-state response. The overall system is simulated in MATLAB/Simulink and the results are verified using a hardware implementation of the prototype circuit.

1. Introduction

Renewable energy sources have reshaped modern electrical distribution systems and smart grids. Renewable energy sources, especially photovoltaic (PV) systems, are emerging as an essential part of most electric power systems. In the past few years, the development of green energy-based electric power systems has been occurring exponentially. Researchers are trying to find new and efficient ways to integrate renewable energy sources with power grids to restructure them into smart grids. The fundamental and most demanding part of the grid integration of renewable energy sources is an inverter. There are various types of inverters existing in the world that vary from simple H-bridge square wave types to multilevel inverters (MLIs) [1,2].

The next generation of two-level H-bridge inverters is pulse width modulation (PWM)-type inverters that utilize high-frequency PWM techniques. The main disadvantage of PWM-type inverters is that they have more switching losses due to high-frequency operation and are less efficient [3]. The grid integration of PWM-type inverters also requires a high weight and size of harmonic elimination filters to comply with grid requirements and standards. Moreover, for medium- and high-power applications, high-power rating switches are required which may not be readily available or become quite expensive. To overcome the problems associated with simple two-level and PWM-type inverters, researchers introduced numerous topologies of multilevel inverters [4,5,6,7,8,9].

A multilevel inverter provides certain advantages over the conventional H-bridge inverters, such as a smaller number of harmonics, low dV/dt stress on switching devices, a reduced size filter, low total harmonic distortion (THD), low electromagnetic interference (EMI), improved power quality, and smaller size of switching components [10,11,12,13,14,15].

One of the recent topics in the field of power electronics is the grid integration of renewable energy sources via inverters. Researchers are working on novel topologies of MLIs to come up with a cost-effective solution in the form of a reduced parts count of power electronic circuitry. In [16], an asymmetrical multilevel inverter topology using six unidirectional switches, one bidirectional switch, and two DC sources to generate nine levels is presented. The cascading of two such units yields seventeen levels. However, there is no explicit mechanism for the PWM implementation in such a way that the MLI can be operated in a closed loop for grid integration purposes with a controlled active and reactive power flow.

A Square T-Type MLI topology using four DC power sources and twelve switches is proposed in [17] and generates seventeen voltage levels at the output. The modified version of the MLI topology in [17] is presented in [18] with a modified name, K-type. The K-type MLI topology yields a thirteen level output using fourteen switches, two DC voltage sources, and two capacitors. The four voltage sources of the topology in [17] are replaced with two voltage sources and two capacitors in [18]. In this way, the total number of DC voltage sources is reduced to half.

The requirement of an H-bridge is essential to obtain negative voltage levels in an MLI topology that is only able to generate positive voltage levels. A T-type topology is presented in [19] with an H-bridge to generate both negative and positive higher voltage levels using ten switches. Another MLI topology presented in [20] uses four DC voltage sources and ten switches to generate thirty-one output voltage levels. The main shortcoming of the topology in [20] is that a higher number of isolated gate drivers are required.

A multilevel inverter topology comprised of twelve bidirectional switches to generate six levels is presented in [21]. The authors claimed to have it integrated with an electric power grid. However, due to the availability of only six levels, there is a need for an output filter for proper grid integration, otherwise the reverse current will damage the inverter. Moreover, the PWM control scheme for grid integration has not been explicitly explained. A magnetic-linked multilevel inverter to integrate PV systems with an electric power grid is presented in [22], along with its model predictive control. The magnetic-linked MLI configuration uses a toroidal ferrite transformer, fourteen switches, eight diodes, and three capacitors for a single phase 9-level active neutral-point clamped inverter. Although the control scheme for grid integration is properly elaborated, this configuration is more susceptible to EMI because of high-frequency switching to generate input voltage for the toroidal transformer.

This paper proposes a single-phase grid-connected 81-level inverter with the modified W-type multilevel inverter (MWMLI) topology previously presented in [23] for grid integration. The MWMLI configuration uses four input DC power sources, eighteen unidirectional switches, and eight isolated gate drivers to obtain an 81-level output voltage using an H-bridge. The four DC power sources can be obtained from distributed energy sources (DES), such as photovoltaic (PV) arrays connected in a suitable configuration to generate a golden ratio of power supplies. The numbering in Figure 1 shows the quantity of PV panels in a series connection for a specific voltage source and there are four DC power sources for the MWMLI topology. The configuration of the PV scheme as four DC power sources for the MWMLI is shown in Figure 1. The grid integration of the proposed inverter configuration, along with active and reactive power flow control is carried out using the αβ-dq transform domain for the sensed grid signals. The PWM generation is carried out using the binary search nearest level (BSNL) algorithm based on the output of the controller and a look-up table.

This paper is prepared as follows: Section 2 presents the proposed MWMLI topology and its general design equations along with switching states. Section 3 presents the grid integration along with active and reactive power flow control using an αβ-dq transform domain. Section 4 presents the simulation and experimental results. Section 5 discusses the results along with the pros and cons of the proposed system. In the end, Section 6 summarizes the results to confirm the novelty of the proposed grid-connected system and its applications.

2. Proposed MWMLI Topology

The single-phase MWMLI topology to obtain an 81-level output voltage is shown in Figure 2. It uses a total of eighteen unidirectional switches (S₁–S₁₄ and H₁–H₄) and four DC power sources (V₁–V₄) with a golden ratio of 1:3:9:27. The DC voltage source V1 has the lowest value as V_DC in the circuit. The H-bridge comprised of switches H₁–H₄ ensures the generation of negative voltage levels corresponding to each positive voltage level. With the golden ratio of 1:3:9:27, an 81-level (40 positives, 40 negatives, and a zero level) output voltage is obtained from the MWMLI configuration. The switching states for the gate pulses of MWMLI for all the voltage level magnitudes are shown in

Table 1. Switching states of MWMLI for all voltage magnitudes.

Sr. No.	S1	S3	S5	S7	S9	S11	S13	$\left|{\mathit{V}}_{\mathit{O}}\right|$
1	1	1	1	1	1	1	1	0
2	1	1	1	1	1	0	1	VDC
3	1	1	1	1	0	1	0	2VDC
4	1	1	1	1	0	0	0	3VDC
5	1	1	1	1	0	0	1	4VDC
6	1	0	1	0	1	1	0	5VDC
7	1	0	1	0	1	1	1	6VDC
8	1	0	1	0	1	0	1	7VDC
9	1	0	1	1	1	1	0	8VDC
10	1	0	1	1	1	1	1	9VDC
11	1	0	1	1	1	0	1	10VDC
12	1	0	1	1	0	1	0	11VDC
13	1	0	1	1	0	1	1	12VDC
14	1	0	1	1	0	0	1	13VDC
15	0	1	0	0	1	1	0	14VDC
16	0	1	0	0	1	1	1	15VDC
17	0	1	0	0	1	0	1	16VDC
18	0	1	0	1	1	1	0	17VDC
19	0	1	0	1	1	1	1	18VDC
20	0	1	0	1	1	0	1	19VDC
21	0	1	0	1	0	1	0	20VDC
22	0	1	0	1	0	1	1	21VDC
23	0	1	0	1	0	0	1	22VDC
24	0	1	1	0	1	1	0	23VDC
25	0	1	1	0	1	1	1	24VDC
26	0	1	1	0	1	0	1	25VDC
27	0	1	1	1	1	1	0	26VDC
28	0	1	1	1	1	1	1	27VDC
29	0	1	1	1	1	0	1	28VDC
30	0	1	1	1	0	1	0	29VDC
31	0	1	1	1	0	1	1	30VDC
32	0	1	1	1	0	0	1	31VDC
33	0	0	1	0	1	1	0	32VDC
34	0	0	1	0	1	1	1	33VDC
35	0	0	1	0	1	0	1	34VDC
36	0	0	1	1	1	1	0	35VDC
37	0	0	1	1	1	1	1	36VDC
38	0	0	1	1	1	0	1	37VDC
39	0	0	1	1	0	1	0	38VDC
40	0	0	1	1	0	1	1	39VDC
41	0	0	1	1	0	0	1	40VDC

.

The generic equations to calculate the number of DC power sources and the number of switching devices based on the number of voltage levels is given as:

$$N_{DC}={\log }_3\left(N_L\right)$$

(1)

$$N_S=2\left(2N_{DC}+1\right)$$

(2)

Using the golden ratio of DC power sources, the maximum number of levels for MWMLI topology is:

$$N_L=3^{N_{DC}}$$

(3)

The peak output voltage for the MWMLI topology is given as:

$$V_{o,pk}=\frac{\left(N_L-1\right)}{2}{V}_{DC}$$

(4)

where $V_{DC}$ is the lowest DC voltage source value equal to V₁ in this case.

The maximum blocking voltage (MBV), also denoted as the total standing voltage in [23], is the sum of the reverse blocking voltage of individual switching devices in the MWMLI topology. The MBV is an important parameter in the selection of suitable switches for a given power and voltage rating of an inverter. MBV for the MWMLI topology is given as:

$$MBV={\displaystyle \sum }_{i=1}^{14}{V}_{Si}+4V_{H_1}$$

(5)

Since the MWMLI topology is using the golden ratio of DC power sources,

$$MBV=266V_{DC}$$

(6)

3. Controller Implementation

The closed-loop control of the MWMLI topology for grid integration is developed based on its modeling in the synchronously rotating reference frame. In the modeling, the coupling inductance between the grid and the inverter is considered lossless. The state equations for the MWMLI using Park transformation [24,25] are given as:

$$v_d=L\frac{d{i}_d}{dt}-\omega L{i}_q+v_{gd}$$

(7)

$$v_q=L\frac{d{i}_q}{dt}+\omega L{i}_d+v_{gq}$$

(8)

where, $v_{gd}$ and $v_{gq}$ are the grid side d-axis and q-axis voltages, respectively. In Equations (7) and (8), the coupling terms $\omega L{i}_q$ and $\omega L{i}_d$ on the grid side should be decoupled on the controller side to nullify the coupling effect and design a proper PI controller for active and reactive power flow to the grid. The decoupled form of Equations (7) and (8) is given as:

$$v_d=L\frac{d{i}_d}{dt}+\omega L{i}_q+v_{gd}$$

(9)

$$v_q=L\frac{d{i}_q}{dt}-\omega L{i}_d+v_{gq}$$

(10)

where, $v_d$ and $v_q$ are the control inputs for the PWM generation block in Figure 3.

Binary Search Nearest Level Algorithm

The binary search nearest level algorithm (BSNLA) is used to generate the switching pulses based on the given reference voltage. This algorithm works as follows:

The reference signal $v_{\alpha }$ is sampled at a sufficient sampling rate above the Nyquist rate and the amplitude of every sample serves as the search index for the lookup table (LUT) of switching states. Based on the BSNLA, the switching states array for a voltage level nearest to the sample amplitude is sent to the output of the BSNLA/LUT block, as in Figure 3. The output of the BSNLA/LUT block is fed to the MWMLI. The flow chart of the implementation of BSNLA is shown in Figure 4.

4. Simulation and Experimental Results

The topology of MWMLI is simulated in MATLAB/Simulink using the BSNL algorithm for grid-tied operations. An ideal voltage source is taken as a grid and the output of the MWMLI is connected to the grid through a lossless inductance $L_g$. The parameters for the simulation of MWMLI topology in MATLAB/Simulink are shown in

Table 2. Simulation parameters of MWMLI.

Parameter	Value	Units
Inductance (Lg)	1	mH
Grid frequency (f)	50	Hz
Lowest DC voltage (VDC)	10	V
Value of Kp	100	-
Value of Ki	8000	-
Grid voltage amplitude (Vg)	400	Vpeak

. Active and reactive power is set as a reference, which is then dynamically step changed multiple times to different values during the simulation to observe the transient and steady-state operation of the grid-connected MWMLI. The simulation results for different combinations of active and reactive power flow to the grid are presented as the simulation cases (SC).

SC-1: Using the parameters specified in Table 2, the circuit of MWMLI along with BSNLA is simulated in MATLAB/Simulink and the resulting waveforms of voltage and current for dynamic active power flow to the grid are shown in Figure 5. The reference and the estimated d-axis currents corresponding to the current waveform in Figure 5 are plotted in Figure 6. Because of the active power flow only, the q-axis component of the current is zero and hence ignored in the plot.

SC-2: For a dynamic active and fixed reactive power flow to the grid, the MWMLI is simulated and the resulting voltage and current waveforms are shown in Figure 7. The reference and the estimated dq-axis currents corresponding to the current waveform of Figure 7 are plotted in Figure 8 as separate subplots for d-axis and q-axis components. As there is a non-zero reactive power flow to the grid in this case, the q-axis component is non-zero as compared to the previous case. It can be seen from Figure 8 that the q-axis component is non-zero and has a consant value of −5, whereas the d-axis component value is dynamically step changed proportional to the step change value in the active power flow.

SC-3: The simulation of MWMLI for various combinations of active and reactive power flow to the grid at a lagging power factor is also carried out in MATLAB/Simulink. The resulting waveforms of voltage and current showing dynamic step changes in the current proportional to the power flow are shown in Figure 9. The reference and the estimated dq-axis currents corresponding to the current waveform in Figure 9 are plotted in Figure 10 as separate subplots for d-axis and q-axis components. In this case, as both the active and reactive power flow commands are given to the controller dynamically, the resulting step changes are reflected in the d-axis and q-axis components of the current that are shown in Figure 10 as separate subplots.

The hardware implementation of the MWMLI is carried out using real components. To test the prototype, the DC power sources are built using switch mode power supplies (SMPS). Figure 11 shows the hardware circuit for the prototype testing of the MWMLI operation. The Elbert v2 FPGA board is used for the implementation of switching control for the MWLMI. The other hardware components used in the prototype development are listed in

Table 3. Hardware components used for prototype development.

Parameter	Quantity/Value
IRFP450	6
R6015ENX	8
UCC28700DBVR	2
IRF3205	12
CSD19534Q5A	2
T750342424	2
TLP250	16
KNF6450A	4
IR2103	2

. The experimental voltage and current waveforms at unity power factor and 0.85 lagging power factor are shown in Figure 12 and Figure 13, respectively.

The hardware prototype of the proposed MWMLI topology is tested for a non-linear independent load to determine the effectiveness when operating as a standalone. The resuting waveforms for voltage and current are shown in Figure 14. Another experiment with the voltage and current waveforms shown in Figure 15 is also performed at a modulation index of 0.88. It can be observed from Figure 15 that the voltage waveform is slightly distorted after decreasing the modulation index from unity. This is because the number of voltage levels are now reduced from 81, as some voltage levels are skipped.

The proposed grid-connected system is analyzed for efficiency computation at different loading conditions. Based on the loss and efficiency analysis equations presented in [23], the losses of the MWMLI are computed to determine the efficiency of the grid-connected operation. The efficiency of the grid-connected MWMLI system for unity power factor loads is above 90%, whereas the efficiency for lagging power factor loads is slightly less than 90%. The plot showing the efficiency trend versus power output is shown in Figure 16.

5. Discussion

The grid-connected 81-level MWMLI is implemented in MATLAB/Simulink for the simulation, and its hardware prototype is developed to verify the simulation results. The waveform of the current for the dynamic power flow to the grid shows that at the locations of step changes in the load, the controller efficiently tracks the step changes within two cycles of the grid frequency. The waveform results show that any combination of active and reactive power flow to the grid has approximately no impact on the waveshape of the MWMLI voltage. Since the THD of the MWMLI, as reported in [23], is 1.04%, there is no need for an output filter for the interconnection with the electric grid. The efficiency graph reveals that the MWMLI topology has an efficiency above 90% at unity power factor, whereas its efficiency for 0.85 lagging power factor loads is slightly less than 90%. The efficiency plot also shows that the efficiency starts to decrease slightly by increasing the output power for unity power factor loads. This effect is justified, as the conduction loss is proportional to the square of the current. A shortcoming of the proposed MWMLI topology is that it has slightly less efficiency when compared with other MLI topologies in the literature. However, the output power quality is improved due to the increased output voltage levels compared to those topologies. Another justification for this drawback is that there is no need for an output filter for the interconnection with the grid, as the MWMLI has better output voltage quality.

6. Conclusions

This paper presents a single-phase grid-connected 81-level MWMLI for real-time power flow to an electric grid. The proposed configuration uses an 81-level MWMLI that has eighteen switching devices and requires four DC power sources. The modeling of the controller for the generation of PWM pulses is carried out in a synchronously rotating reference frame along with the BSNL algorithm. The modeling of the single-phase system uses the concept of transformation of voltages and currents directly from αβ to the dq frame, with the β-components obtained virtually by delaying the α-component. The proposed grid-connected system is simulated in MATLAB/Simulink, and the simulation results are also verified by testing the hardware prototype. The key features of the proposed configuration, such as higher efficiency, THD within standards, and no filter requirement, make it suitable for grid-connected applications. The MWMLI system can be used to extract energy from renewable energy sources, such as PV systems, DESs, and other inverter based resources (IBRs). The energy extraction with high efficiency using the proposed MWMLI topology has a wide range of applications, such as standalone industrial systems, as well as grid-connected systems. The proposed MWMLI system also has good stability in terms of step changes in the load. As modern smart grids are being integrated with IBRs at multiple locations and the overall stability of the system is directly dependent on the stability of the individual components of the systems, the proposed scheme provides good stability under various loading conditions.