Battery Power Interface to Mitigate Load Transients and Reduce Current Harmonics for Increasing Sustainability in DC Microgrids

Abstract

In microgrids, battery chargers/dischargers are used to manage power flow between the battery and the DC bus and to regulate the DC bus voltage, ensuring safe operating conditions for sources and loads. These actions contribute to enhancing the sustainability of the microgrid by improving energy efficiency, extending battery life, and ensuring reliable operation. The classical converter adopted to implement the battery chargers/dischargers is the boost converter, which avoids high current harmonic injection into the battery because of its continuous input current. But due to the discontinuous output current, it introduces high current harmonics into the DC bus. This also occurs in Sepic, Zeta, or other DC/DC converters with discontinuous input or output currents. One exception is the Cuk converter, which has both continuous input and output currents. However, in the Cuk converter, the intermediate capacitor voltage is higher than the input and output voltages, thus imposing high stress on the semiconductors and requiring a costly capacitor with high energy storage. Therefore, this paper proposes the design of a battery charger/discharger based on a non-electrolytic capacitor boost converter. This topology provides continuous input and output currents, which reduces harmonic component injection, extends battery life, and increases operation efficiency. Moreover, it requires a lower intermediate capacitor voltage, thereby enhancing reliability. The design of this battery charger/discharger requires an adaptive sliding-mode controller to ensure global stability and accurate bus voltage regulation. A formal stability analysis and design equations are provided. The proposed solution is validated through detailed simulations, while the adaptive sliding-mode controller is specifically tested using a detailed software-in-the-loop approach.

1. Introduction

The sustainability of microgrids can be enhanced by improving energy efficiency, extending component lifespan, and ensuring safe operating conditions for sources, power converters, and loads. Key actions to achieve this include reducing current harmonics [1,2,3,4], which minimizes power losses and extends the lifespan of microgrid components. In addition, accurate regulation of the bus voltage ensures safe operation for all components within the microgrid. Moreover, subtle actions, such as operating the sliding-mode control (SMC) of power interfaces with fixed switching frequency, also contribute to the sustainability of microgrids. The fixed frequency allows for the selection of optimized MOSFET characteristics such as T_on, T_off, and R_DS(on), in contrast to selecting components for the worst-case or maximum switching frequency when a range of operation is used. This, in turn, increases efficiency and reduces the overall size of the converter [5,6,7].

Battery-based microgrids rely on chargers/dischargers to control the power flow between the battery and the DC bus. The classical boost converter is widely used for this purpose because of its continuous input current, which reduces harmonic current injections into the battery [1,2,3,4]. In [1], the authors propose a sliding-mode controller for a boost-based charger/discharger, which enhances disturbance rejection while regulating the bus voltage. Reference [2] presents a hybrid optimization method for a battery charger/discharger in a DC microgrid, combining the spider wasp optimizer and the dilated residual network, which reduces system cost and improves the battery power extraction. In [3], a review of soft-switched power-factor-correction (PFC) boost converters is provided, focusing on various PFC techniques and implementations using analog and digital circuits. Similarly, reference [4] compares different PFC topologies, emphasizing the requirements for battery chargers/dischargers, and proposing a cascade of boost and buck converters to maximize efficiency while ensuring proper voltage and current regulation. Despite the benefits of a boost converter, its discontinuous output current introduces significant current harmonics into the DC bus, affecting all connected components. Similar limitations arise in Sepic and Zeta converters, which draw discontinuous input or output currents.

The Cuk converter, in contrast, provides both continuous input and output currents [8], but its intermediate capacitor voltage exceeds both the input and output voltages, increasing stress on semiconductors and requiring a costly capacitor [9,10,11]. In [9], a Cuk converter is used to interface a PV module and a lithium-ion battery in a standalone photovoltaic energy storage system. The study integrates a positive-pulse-current battery charge control algorithm with a hill-climbing MPPT technique to extend the battery lifespan. Reference [10] presents a bipolar converter that combines Sepic and a Cuk converters, leveraging their advantages while using only one active switch, simplifying control circuitry. In [11], a modified Cuk converter is employed as a basic cell in a cascade topology, achieving a high voltage conversion ratio suitable for interfacing with high-voltage buses. Additionally, some Cuk converters operate in discontinuous conduction mode to simplify control circuits and provide power factor correction without an input filter. However, this mode generates high current harmonics at the converter’s output [12]. Despite the advantages of Cuk converters in battery interfacing, the high stress in the intermediate capacitor increases cost, necessitating alternative solutions.

The sliding-mode control is widely used with the classical boost converter in battery chargers/dischargers. SMC is frequently selected because of its robustness, stability, and fast dynamic response. However, its nature leads to the operation of a wide frequency range, which introduces challenges in converter design, such as sizing power components for the worst-case, i.e., the maximum switching frequency. Several authors have proposed using a fixed switching frequency in various applications, commonly reporting a reduction in losses and, in some cases, a decrease in power component size [5,6,7]. In [7], the authors apply a fixed switching frequency to a sliding-mode controller for an energy storage system connected to the electrical grid. They report that their solution eliminates the possibility of DC injection into the grid. In [6], a sliding-mode current controller with fixed switching frequency is applied to a utility interface inverter. The main advantages of this solution are power factor control and minimization of supply current harmonics. In [5], a control algorithm based on three decoupled SMC and three Kalman filters is proposed for a three-phase unity power factor rectifier. In this case, the switching spectrum is concentrated around the desired switching frequency, thus achieving the benefits of a fixed-frequency operation. As shown in these three studies, using a fixed switching frequency, in contrast to a variable switching frequency, reduces power losses and optimizes converter design. These characteristics can be used to enhance the sustainability of microgrids based on power converters.

To address those challenges, this paper proposes a battery charger/discharger based on a bidirectional version of the non-electrolytic capacitor (NEC) boost converter. This solution provides continuous input and output currents while maintaining a lower intermediate capacitor voltage compared to other converters, such as the Cuk structure. The NEC boost structure was introduced by Zhang et al. in [13] for considering an unidirectional power flow; thus, it was not suitable for battery chargers/dischargers. A modification to the NEC structure was developed in [14] to invert the power flow, thus producing an NEC buck converter. In the boost version, the input current is the sum of two inductor currents, and the output current is defined by a single inductor; thus, both input and output currents are continuous. Inversely, in the buck version, the input current is defined by a single inductor, while the output current is the sum of two inductor currents; hence, both input and output currents are continuous. Moreover, due to the circuit structure, the intermediate capacitor voltage is defined by the output voltage in the boost case; however, in the buck case, the intermediate capacitor voltage is defined by the input voltage. This is an advantage over other converters with continuous input/output currents like the Cuk converter, in which the intermediate capacitor voltage is defined by the output voltage divided by the duty-cycle [8], thus leading to very large voltages at low duty-cycles.

The main objective of this paper is to design a battery charger/discharger using a bidirectional NEC boost converter. The continuous input and output currents reduce the high order current harmonics, thus mitigating potential adverse effects on the battery and the load. To ensure proper operation of this battery interface, two controllers are designed: an adaptive sliding-mode current controller, which guarantees global stability of the entire converter, and an adaptive voltage controller to regulate the DC bus voltage, thus ensuring a safe and stable voltage level for all connected sources and loads. In addition, the sliding-mode controller ensures a fixed switching frequency, which enables appropriate component selection and converter design, minimizing high current harmonics, preventing potential damage to the battery, and maintaining power quality within the system. Finally, this paper includes both a formal stability analysis and control design equations to support the proposed approach.

The rest of the paper is organized as follows: Section 2 presents the analysis of the power stage, including the converter’s complete structure; it also describes the differential equations for each operation state and the steady-state relationships among parameters and variables. Section 3 focuses on the adaptive sliding-mode current controller, presenting the transversality, reachability, and equivalent control conditions. Section 4 introduces the adaptive voltage controller design, while Section 5 discusses the design of system components, such as inductors and capacitors. Validation is presented in Section 6 and Section 7: first, a simulation-based application example demonstrates the effectiveness of the design, and then, the implementation of the current and voltage controllers is verified using high-fidelity Software-In-the-Loop (SIL). Finally, the paper concludes in Section 8 with a summary of key findings and future research directions.

2. Power Stage Analysis

Figure 1 shows the circuital model of the proposed battery charger/discharger based on a bidirectional implementation of the NEC converter. The circuit is formed by two inductances $L_1$ and $L_2$, an intermediate capacitor $C_i$, and two MOSFETs driven by the control signal u and its complement $\overline{u}=1-u$. The NEC converter interfaces a battery $v_b$ with a DC bus formed by the capacitance $C_o$; the circuit also models the aggregated currents of the loads and sources connected to the bus as a single current source $i_o$. In order to provide a realistic representation of the power system, the parasitic resistances on the converter’s elements are also considered: the on-resistance of the MOSFETs ($R_{on}$), the inductors’ ESR ($R_{L1}$ for $L_1$ and $R_{L2}$ for $L_2$), and the capacitors’ ESR ($R_{Ci}$ for $C_i$ and $R_{Co}$ for $C_o$). Figure 1 also shows the proposed control structure, which is formed by an adaptive sliding-mode controller, used to ensure global stability by regulating both inductor currents in a stable profile, and an adaptive voltage controller, which is designed to regulate the behavior of the DC bus voltage.

Two circuit states are formed depending on the control signal value. The first state occurs when $u=1$ ($\overline{u}=0$), which is depicted at the top of Figure 2. In state 1 the battery charges the inductor $L_1$, while the intermediate capacitor $C_i$ is discharged to charge the inductor $L_2$. State 2 occurs when $u=0$ ($\overline{u}=1$), and it is observed at the bottom of Figure 2. In this second state the battery charges the inductor $L_2$, while the capacitor $C_i$ is charged. This behavior shows that the $C_i$ capacitor is used as an energy buffer for the inductors, isolating one inductor at a time; thus, this intermediate capacitance can be small, which can avoid unnecessarily large energy storage. In addition, Figure 2 shows that the battery current is the sum of the currents in both inductors for the two states, hence it has a continuous waveform. Similarly, the current provided to the DC bus $i_{out}$ is the $L_2$ current ($i_{out}=i_{L2}$), thus it is also a continuous waveform. Therefore, this power stage provides continuous input ($i_b$) and output ($i_{out}$) currents. This is an improvement over the classical boost converter that only provides continuous input current, while the output current is discontinuous [15], thus introducing undesired high-frequency harmonics to the DC bus. An alternative converter to provide continuous input and output currents is the Cuk topology, but it has higher voltage stress, as mentioned in the introduction; this aspect will be further discussed afterward.

The differential equations for the inductor currents and capacitor voltages in state 1 are as follows:

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{v_b-\left(i_{L1}+i_{L2}\right)·R_{on}-i_{L1}·R_{L1}}{L_1}}\end{array}$$

(1)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{v_{Ci}+v_b-v_{Co}-R_{Ci}·L_2-\left(i_{L1}+i_{L2}\right)·R_{on}-\left(i_{L2}-i_o\right)·R_{Co}-i_{L2}·R_{L2}}{L_2}}\end{array}$$

(2)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{v}_{Ci}}{dt}}={\displaystyle \frac{-i_{L2}}{C_i}}\end{array}$$

(3)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{v}_{Co}}{dt}}={\displaystyle \frac{i_{L2}-i_o}{C_o}}\end{array}$$

(4)

Similarly, the differential equations for the inductor currents and capacitor voltages in state 2 are as follows:

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{v_b-v_{Ci}-R_{Ci}·i_{L1}-\left(i_{L1}+i_{L2}\right)·R_{on}-R_{L1}·L_1}{L_1}}\end{array}$$

(5)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{v_b-v_{Co}-\left(i_{L1}+i_{L2}\right)·R_{on}-\left(i_{L2}-i_o\right)·R_{Co}-R_{L2}·i_{L2}}{L_2}}\end{array}$$

(6)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{v}_{Ci}}{dt}}={\displaystyle \frac{i_{L1}}{C_i}}\end{array}$$

(7)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{v}_{Co}}{dt}}={\displaystyle \frac{i_{L2}-i_o}{C_o}}\end{array}$$

(8)

Then, combining both states using the MOSFETs control signal u leads to the switched model, which describes all the non-linear dynamics of the power system, including the switching ripple:

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{v_b-v_{Ci}·\overline{u}-\left(i_{L1}+i_{L2}\right)·R_{on}-i_{L1}·R_{L1}-R_{Ci}·i_{L1}·\overline{u}}{L_1}}\end{array}$$

(9)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{v_{Ci}·u+v_b-v_{Co}-\left(i_{L1}+i_{L2}\right)·R_{on}-\left(i_{L2}-i_o\right)·R_{Co}-R_{L2}·i_{L2}-R_{Ci}·i_{L2}·u}{L_2}}\end{array}$$

(10)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{v}_{Ci}}{dt}}={\displaystyle \frac{i_{L1}·\overline{u}-i_{L2}·u}{C_i}}\end{array}$$

(11)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{v}_{Co}}{dt}}={\displaystyle \frac{i_{L2}-i_o}{C_o}}\end{array}$$

(12)

The average value of the MOSFETs control signal u corresponds to the duty cycle, as given in (13), where $T_{sw}$ is the switching period and $d^{\prime }=1-d$ is the complementary duty cycle; hence the averaged model of the power system is calculated as reported in (14), (15), (16) and (17).

$$\begin{array}{c}\hfill d={\displaystyle \frac{1}{T_{sw}}}·{\int }_0^{T_{sw}}udt\end{array}$$

(13)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{v_b-v_{Ci}·d^{\prime }-\left(i_{L1}+i_{L2}\right)·R_{on}-i_{L1}·R_{L1}-R_{Ci}·i_{L1}·d^{\prime }}{L_1}}\end{array}$$

(14)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{v_{Ci}·d+v_b-v_{Co}-\left(i_{L1}+i_{L2}\right)·R_{on}-\left(i_{L2}-i_o\right)·R_{Co}-R_{L2}·i_{L2}-R_{Ci}·i_{L2}·d}{L_2}}\end{array}$$

(15)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{v}_{Ci}}{dt}}={\displaystyle \frac{i_{L1}·d^{\prime }-i_{L2}·d}{C_i}}\end{array}$$

(16)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{v}_{Co}}{dt}}={\displaystyle \frac{i_{L2}-i_o}{C_o}}\end{array}$$

(17)

In addition, the input current, which is equal to the battery current, is given in (18), and the DC bus voltage is reported in (19).

$$\begin{array}{c}\hfill i_b=i_{L1}+i_{L2}\end{array}$$

(18)

$$\begin{array}{c}\hfill v_o=v_{Co}+\left(i_{L2}-i_o\right)·R_{Co}\end{array}$$

(19)

The stable relationships between the inductor currents and capacitor voltages are calculated from the averaged model when the differential equations are equal to zero:

$$\begin{array}{c}\hfill d={\displaystyle \frac{-x_b+\sqrt{x_b^2-4·x_a·x_c}}{2·x_a}}\mathrm{where}\left\{\begin{array}{c}{x}_a=-v_o-i_o·\left(R_{L1}+R_{L2}\right)\hfill \\ x_b=-v_b+2·v_o+2·i_o·R_{L2}\hfill \\ x_c=v_b-v_o-i_o·\left(R_{on}+R_{L2}\right)\hfill \end{array}\right.\end{array}$$

(20)

$$\begin{array}{c}\hfill i_{L1}·(1-d)=i_{L2}·d\end{array}$$

(21)

$$\begin{array}{c}\hfill v_{Ci}=v_o+i_o·\left(R_{L2}-{\displaystyle \frac{d}{1-d}}·R_{L2}\right)\end{array}$$

(22)

In addition, from the charge-balance principle at the bus capacitor, it is concluded that the average current of the inductor $L_2$ is equal to the load current, i.e., $〈i_{L2}〉=i_o$. Moreover, it must be pointed out that the stable voltage (at null load current) of the intermediate capacitor (22) is equal to the DC bus voltage $v_o$. Instead, the voltage of the intermediate capacitor of a Cuk converter [8] is ${\displaystyle \frac{v_o}{d}}$; thus, the proposed solution has a lower voltage stress in the components, stores less energy in the intermediate capacitor, and requires a lower voltage rating. Therefore, the topology adopted in this paper provides the same continuous input/output current characteristic available in a Cuk topology, but with lower voltage stress and rating.

Other important measurements are the ripple magnitudes in both inductor currents and capacitor voltages, which are calculated from the differential equations in each state. Those expressions take into account that the switching frequency $F_{sw}$ is the inverse of the switching period $T_{sw}$, i.e., $F_{sw}=1/T_{sw}$, as follows:

$$\begin{array}{c}\hfill \Delta i_{L1}={\displaystyle \frac{v_b-\left(i_{L1}+i_{L2}\right)·R_{on}-i_{L1}·R_{L1}}{2·L_1·F_{sw}}}·d\end{array}$$

(23)

$$\begin{array}{c}\hfill \Delta i_{L2}={\displaystyle \frac{v_b-\left(i_{L1}+i_{L2}\right)·R_{on}-i_{L2}·\left(R_{L2}+R_{Ci}\right)}{2·L_1·F_{sw}}}·d\end{array}$$

(24)

$$\begin{array}{c}\hfill \Delta v_{Ci}={\displaystyle \frac{i_{L2}·d}{2·C_i·F_{sw}}}={\displaystyle \frac{i_o·d}{2·C_i·F_{sw}}}\end{array}$$

(25)

$$\begin{array}{c}\hfill \Delta v_{Co}={\displaystyle \frac{\Delta i_{L2}}{8·C_o·F_{sw}}}={\displaystyle \frac{v_b·d}{16·L_2·C_o·{\left(F_{sw}\right)}^2}}\end{array}$$

(26)

$$\begin{array}{c}\hfill \Delta v_o={\displaystyle \frac{v_b·d}{16·L_2·C_o·{\left(F_{sw}\right)}^2}}+R_{Co}·\Delta i_{L2}\end{array}$$

(27)

Since the battery current is the sum of both inductor currents (18), and the inductor currents are in phase, as observed in (1) and (2), the ripple in the battery current is as follows:

$$\begin{array}{c}\hfill \Delta i_b=\Delta i_{L1}+\Delta i_{L2}\end{array}$$

(28)

The previous models will be used in the following sections to design the control system and power stage.

3. Adaptive Current Controller

The charger/discharger must operate with positive load current (discharge mode), null load current (stand-by mode), and negative load current (charge mode), which are very different operation conditions. Therefore, classical linear controllers designed for a particular condition could fail at other operation points. This problem is addressed by designing the current controller with the sliding-mode theory, which is able to guarantee global stability for the power converter in the entire operation range.

The first control objective is to ensure the stability of the power system. Analyzing the states in Figure 2, we observe that the intermediate capacitor voltage is the result of the difference between the inductor currents. Therefore, imposing condition (21) between $i_{L1}$ and $i_{L2}$ ensures the stability of the $C_i$ voltage, thus all the system becomes stable. This analysis leads to the following first control objective:

$$\begin{array}{c}\hfill O_1=\left\{i_{L2}-i_{L1}·{\displaystyle \frac{1-d}{d}}=0\right\}\end{array}$$

(29)

The second control objective is to regulate the current delivered to the bus capacitor, which will be used by the adaptive voltage controller to regulate the DC bus voltage. Since the first control objective (29) ensures the stable relation between both currents, regulating $i_{L1}$ or $i_{L2}$ provides the same result, just with a different gain. For mathematical simplicity, the second control objective is defined as given in (30), where $i_r$ is the desired reference for $i_{L1}$ current.

$$\begin{array}{c}\hfill O_2=\left\{i_r-i_{L1}=0\right\}\end{array}$$

(30)

Then, combining both control objectives $O_1$ and $O_2$ into a single switching function $\Psi$ gives the expression reported in (31). Finally, the sliding surface proposed for the SMC is reported in (32). It must be pointed out that such a sliding surface changes with the duty cycle, hence it is adapted to changes in the operation conditions.

$$\begin{array}{c}\hfill \Psi =i_r-{\displaystyle \frac{i_{L1}}{d}}+i_{L2}\end{array}$$

(31)

$$\begin{array}{c}\hfill \Phi =\left\{\Psi =0\right\}\end{array}$$

(32)

The conditions needed to ensure a stable operation of an SMC in power converters were established by Sira-Ramirez in [16]: transversality, reachability, and equivalent control conditions. Moreover, Sira-Ramirez demonstrated in [16] that fulfilling both transversality and reachability conditions also ensures the equivalent control condition; thus, the system is globally stable if both transversality and reachability conditions are guaranteed. Those two analyses are performed in the following subsections.

3.1. Transversality Condition

The transversality condition tests the ability of the controller to modify the system trajectory, which is needed to perform any control action. This condition is analyzed by searching for the presence of the control signal u in the derivative of the switching function $\Psi$; if it is present, the controller can modify the system behavior. This condition is formalized as follows:

$$\begin{array}{c}\hfill {\displaystyle \frac{d}{du}}\left({\displaystyle \frac{d\Psi }{dt}}\right)\ne 0\end{array}$$

(33)

Therefore, the first step is to calculate the time derivative of the switching function:

$$\begin{array}{c}\hfill {\displaystyle \frac{d\Psi }{dt}}={\displaystyle \frac{d{i}_r}{dt}}-{\displaystyle \frac{1}{d}}·\left({\displaystyle \frac{v_b-v_{Ci}·\overline{u}-\left(i_{L1}+i_{L2}\right)·R_{on}-i_{L1}·R_{L1}-R_{Ci}·i_{L1}·\overline{u}}{L_1}}\right)+\\ \hfill {\displaystyle \frac{v_{Ci}·u+v_b-v_{Co}-\left(i_{L1}+i_{L2}\right)·R_{on}-\left(i_{L2}-i_o\right)·R_{Co}-R_{L2}·i_{L2}-R_{Ci}·i_{L2}·u}{L_2}}\end{array}$$

(34)

Then, evaluating the transversality condition (33) using (34) results in the following expression:

$$\begin{array}{c}\hfill {\displaystyle \frac{d}{du}}\left({\displaystyle \frac{d\Psi }{dt}}\right)=-{\displaystyle \frac{v_{Ci}+R_{Ci}·i_{L1}}{d·L_1}}+{\displaystyle \frac{v_{Ci}-R_{Ci}·i_{L2}}{L_2}}\end{array}$$

(35)

In null load current the previous expression fulfills restriction (33) if $L_2\ne d·L_1$. So, there are two options: value (35) must be positive ($L_2<d·L_1$) or negative ($L_2>d·L_1$). With the aim of ensuring the lowest current harmonics injected into the DC bus, the option with the higher $L_2$ condition is selected. Finally, the worst-case occurs in charge mode ($i_o<0$):

$$\begin{array}{c}\hfill L_2>d·L_1·{\displaystyle \frac{v_{Ci}-R_{Ci}·i_{L2}}{v_{Ci}+R_{Ci}·i_{L1}}}\Rightarrow {\displaystyle \frac{d}{du}}\left({\displaystyle \frac{d\Psi }{dt}}\right)<0\end{array}$$

(36)

In conclusion, designing the power stage with restriction (36) ensures the transversality condition, which makes it possible to implement an SMC based on the switching function (31).

3.2. Reachability Conditions

The reachability conditions analyze the ability of the controller to reach the surface from an arbitrary operation point. This concept is summarized as follows:

• When the system is operating under the surface $\left(\Psi <0\right)$, then the derivative of the switching function must be positive $\left({\displaystyle \frac{d\Psi }{dt}}>0\right)$ to be able to reach the surface $\left(\Psi =0\right)$.
• When the system is operating above the surface $\left(\Psi >0\right)$, then the derivative of the switching function must be negative $\left({\displaystyle \frac{d\Psi }{dt}}<0\right)$ to be able to reach the surface $\left(\Psi =0\right)$.

The previous conditions are formalized as follows:

$$\begin{array}{c}\hfill \underset{\Psi \to 0^{-}}{lim}{\displaystyle \frac{d\Psi }{dt}}>0\mathsf{and}\underset{\Psi \to 0^{+}}{lim}{\displaystyle \frac{d\Psi }{dt}}<0\end{array}$$

(37)

An important aspect of this analysis concerns the control signal value u needed to change the sign of the switching function derivative. This is obtained from the sign of the transversality condition (36), which in this design is negative. This means that a positive change in u produces a negative switching function derivative, while a negative change in u produces a positive switching function derivative. Those conditions complement inequalities (37) as follows:

$$\begin{array}{c}\hfill \underset{\Psi \to 0^{-}}{lim}{\left.{\displaystyle \frac{d\Psi }{dt}}\right|}_{u=0}>0\mathsf{and}\underset{\Psi \to 0^{+}}{lim}{\left.{\displaystyle \frac{d\Psi }{dt}}\right|}_{u=1}<0\end{array}$$

(38)

Evaluating the practical reachability conditions (38) using the switching function derivative (34) leads to the following restrictions, where the steady-state condition $v_{Ci}\approx v_o$ is considered. The worst case for inequality (39) occurs in charge condition ($i_o<0$), and the worst case for inequality (40) occurs in discharge condition ($i_o>0$).

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_r}{dt}}>{\displaystyle \frac{-v_b+v_o-\left(i_{L1}+i_{L2}\right)·R_{on}-R_{L2}·i_{L2}}{L_2}}-\\ \hfill {\displaystyle \frac{-v_b+v_o-\left(i_{L1}+i_{L2}\right)·R_{on}-i_{L1}·R_{L1}-R_{Ci}·i_{L1}}{d·L_1}}\end{array}$$

(39)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_r}{dt}}<-{\displaystyle \frac{v_b-\left(i_{L1}+i_{L2}\right)·R_{on}-R_{L2}·i_{L2}-R_{Ci}·i_{L2}}{L_2}}+\\ \hfill {\displaystyle \frac{v_b-\left(i_{L1}+i_{L2}\right)·R_{on}-i_{L1}·R_{L1}}{d·L_1}}\end{array}$$

(40)

In conclusion, fulfilling the dynamic restrictions (39) and (40) is needed to ensure the reachability of the sliding surface. Finally, fulfilling restrictions (36), (39) and (40) ensure the existence of the sliding-mode, which guarantees the global stability of the system (29) to impose $i_{L1}=i_r$ (30).

3.3. Fixing the Switching Frequency

The theoretical implementation of the SMC control law is extracted from inequalities (38), as follows:

$$\begin{array}{c}\hfill u=\left\{\begin{array}{ccc}0\hfill & \mathsf{if}\hfill & \Psi <0\hfill \\ 1\hfill & \mathsf{if}\hfill & \Psi >0\hfill \end{array}\right.\end{array}$$

(41)

The main problem of the previous theoretical control law is the infinite switching frequency occurring around $\Psi =0$, i.e., inside the sliding surface. Therefore, it is a common practice to introduce a hysteresis band $\left[-\Delta \Psi ,+\Delta \Psi \right]$ to limit the switching frequency, which forms a practical control law:

$$\begin{array}{c}\hfill u=\left\{\begin{array}{ccc}0\hfill & \mathsf{if}\hfill & \Psi <-\Delta \Psi \hfill \\ 1\hfill & \mathsf{if}\hfill & \Psi >+\Delta \Psi \hfill \end{array}\right.\end{array}$$

(42)

Then the switching frequency is calculated from the switching function (31) and the inductor ripples (23) and (24). The ripple $\Delta \Psi$ in the switching function is calculated as given in (43), which considers that the average value of $i_{L1}·\left(1-d\right)$ is equal to the average value of $i_{L2}·d$ (control objective $O_1$), and the average value of $i_{L1}$ is equal to $i_r$ (control objective $O_2$).

$$\begin{array}{c}\hfill \Delta \Psi =\left|\Delta i_{L2}-{\displaystyle \frac{\Delta i_{L1}}{d}}\right|\end{array}$$

(43)

Then, defining $K_L=L_2/L_1$ as the relation between the inductors, and replacing the ripple magnitudes (23) and (24), leads to the following expression for the switching function ripple:

$$\begin{array}{c}\hfill \Delta \Psi ={\displaystyle \frac{d·\frac{v_b-\left(i_{L1}+i_{L2}\right)·R_{on}-i_{L2}·\left(R_{L2}+R_{Ci}\right)}{K_L}-\left[v_b-\left(i_{L1}+i_{L2}\right)·R_{on}-i_{L1}·R_{L1}\right]}{2·L_1·F_{sw}}}\end{array}$$

(44)

Adapting the hysteresis band using Equation (44) imposes a fixed frequency $F_{sw}$ to the battery charger/discharger. Therefore, this is an adaptive SMC designed to achieve two goals: guaranteeing the desired behavior under any operating condition (adapting $\Psi$) and providing a fixed frequency (adapting $\Delta \Psi$). Such a last characteristic is important since switching power losses increase with the switching frequency as reported in [17]. Similarly, the reliability of switching converters significantly decreases with increments in the switching frequency, as illustrated in [18]. Since Equation (44) shows that a fixed $\Delta \Psi$ value results in higher switching frequencies for higher $v_b$ and lower duty cycles, adapting $\Delta \Psi$ prevents additional power losses and reduces the failure rate in those operation conditions, thus making the battery charger/discharger more sustainable. Finally, the fixed value of the switching frequency must be selected to achieve a balance between size, switching losses, reliability, cost, and dynamic performance: low switching frequencies allow high reliability, reduced switching losses, and low implementation cost; instead, high switching frequencies provide a compact implementation and faster dynamic response.

4. Adaptive Voltage Controller

The adaptive sliding-mode current controller (ASMC) ensures regulated inductor currents, but the bus voltage is not regulated. Therefore, this section proposes an adaptive voltage controller to provide global stability to the DC bus.

4.1. Equivalent Model of the Current Control Loop

The first step is to model the power system under the action of ASMC designed in Section 3. Figure 3 shows, at the top, the circuital equivalent of the system, where the power converter is modeled by a dependent current source with gain ${\displaystyle \frac{1-d}{d}}$; such a gain is calculated from (29) and taking into account that $i_{L1}=i_r$ due to the ASMC action.

In the equivalent model the ASMC reference is provided by an adaptive voltage controller, and the ASMC output current interacts with both the DC bus capacitor and load current. Equation (45) reports the Laplace equation of the DC bus voltage obtained from the analysis of the output node (A).

$$\begin{array}{c}\hfill v_o={\displaystyle \frac{1+R_{Co}·C_o·s}{s·C_o}}·\left({\displaystyle \frac{1-d}{d}}·i_r-i_o\right)\end{array}$$

(45)

Figure 3 shows, at the bottom, the block diagram of the complete control system, including the structure of the proposed adaptive voltage controller: it is formed by a Proportional-Integral (PI) controller with adaptive parameters, and an adaptive law calculating those parameters. The following transfer function is obtained from that block diagram, which neglects the $R_o·Co$ factors since they have $ns$ units ($R_o$ in $\mathrm{m}\Omega$ and $Co$ in $\mathrm{\mu F}$), thus are much faster than the system dynamics:

$$\begin{array}{c}\hfill G_{vo,io}={\displaystyle \frac{v_o}{i_o}}={\displaystyle \frac{-s}{C_o·\left(1+\frac{1-d}{d}·k_p·R_{Co}\right)·s^2+\frac{1-d}{d}·k_p·s+\frac{1-d}{d}·k_i}}\end{array}$$

(46)

The previous transfer function $G_{vo,io}$ provides the dynamic relation between the DC bus voltage and the perturbations on the bus current, which are introduced by the sources and loads. An important characteristic of $G_{vo,io}$ is the transfer function modification caused by changes in the operation point (i.e., duty-cycle d), which is the motivation for designing an adaptive voltage controller.

4.2. Design of the Voltage Controller

The main problem of designing a PI controller using transfer function (46) is the coefficient variation depending on the duty cycle. This condition is faced by normalizing those coefficients as reported in Equation (47), which leads to the normalized transfer function $G_{voN}$ reported in (48). Then, the normalized parameters $k_{pN}$ and $k_{iN}$ are designed with $G_{voN}$ to ensure the global stability and desired performance in any operation condition.

$$\begin{array}{c}\hfill k_{pN}={\displaystyle \frac{1-d}{d}}·k_p\mathrm{and}{k}_{iN}={\displaystyle \frac{1-d}{d}}·k_i\end{array}$$

(47)

$$\begin{array}{c}\hfill G_{voN}={\displaystyle \frac{v_o}{i_o}}={\displaystyle \frac{-s}{C_o·\left(1+k_{pN}·R_{Co}\right)·s^2+k_{pN}·s+k_{iN}}}\end{array}$$

(48)

The controller is designed considering the strongest current perturbation in the DC bus: a step change in the load current with amplitude $\delta i_o$, which depends on the particular application. In the Laplace domain such a current perturbation is formalized as $i_o={\displaystyle \frac{\delta i_o}{s}}$. Moreover, this solution considers a unitary damping ratio to avoid large voltage oscillations, thus requiring the relation between $k_{iN}$ and $k_{pN}$ given in (49).

$$\begin{array}{c}\hfill k_{iN}={\displaystyle \frac{k_{PN}^2}{4·C_o·\left(1+k_{pN}·R_{Co}\right)}}\end{array}$$

(49)

Then, the bus voltage is calculated as the inverse Laplace transformation $v_o={\mathcal{L}}^{-1}\left\{G_{voN}·{\displaystyle \frac{\delta i_o}{s}}\right\}$. The time-domain expression resulting from such a procedure is given in (50), where $exp\left(·\right)$ calculates the exponential function.

$$\begin{array}{c}\hfill v_o=G_0·t·exp\left(-t·{\displaystyle \frac{P}{2}}\right)\\ \hfill \mathrm{where}{G}_0={\displaystyle \frac{-\delta i_o}{C_o·\left(1+k_{pN}·R_{Co}\right)}}\mathrm{and}P={\displaystyle \frac{k_{pN}}{C_o·\left(1+k_{pN}·R_{Co}\right)}}\end{array}$$

(50)

The main safety restriction in the DC bus concerns limiting the voltage deviations within a safe band $[-MO,+MO]$, which prevents overshoots that could damage the devices connected to the bus and avoids undershoots that could shut down the connected devices. The $MO$ magnitude corresponds to the maximum deviation of $v_o$, which occurs when the voltage derivative (51) is equal to zero.

$$\begin{array}{c}\hfill {\displaystyle \frac{d{v}_o}{dt}}=G_0\left[\left(1-{\displaystyle \frac{p}{2}}·t\right)·exp\left(-t·{\displaystyle \frac{p}{2}}\right)\right]\end{array}$$

(51)

Solving ${\displaystyle \frac{d{v}_o}{dt}}=0$ leads to the time $t_{MO}={\displaystyle \frac{2}{P}}$ when the maximum voltage deviation occurs. Then, replacing that $t_{MO}$ and solving for ${\left.v_o\right|}_{t=t_{MO}}=v_r\pm MO$ leads to the $k_{pN}$ value given in (52), which ensures the desired voltage limitation $v_r-MO\le v_o\le v_r+MO$.

$$\begin{array}{c}\hfill k_{pN}={\displaystyle \frac{2·\delta i_o·exp\left(-1\right)}{MO}}\end{array}$$

(52)

Finally, the settling time of the bus voltage is calculated from (50) by solving $t_s$ in ${\left.v_o\right|}_{t=t_s}=v_r·\left(1\pm ϵ\right)$, where $ϵ$ is the settling-time band; usually $ϵ=2\%$, but any other value can be adopted depending on the application.

The practical implementation of the adaptive voltage controller must be performed in terms of $k_p$ and $k_i$, thus reversing the normalization process (47) leads to the adaptive law:

$$\begin{array}{c}\hfill k_p={\displaystyle \frac{d}{1-d}}·k_{pN}\mathsf{and}{k}_i={\displaystyle \frac{d}{1-d}}·k_{iN}\end{array}$$

(53)

5. System Component Design

This section describes the selection of the power stage parameters, synthesis of the control algorithm, and implementation of the control law using a switching circuit.

5.1. System Parameters

The first step is to co-design the power stage parameters to ensure the global stability of the ASMC, and to fulfill the current and voltage ripple requirements imposed by the loads and sources connected to the DC bus. Finally, the design of the elements is performed in stand-by mode ($i_o=i_{L2}=i_{L1}=0$) to provide compact expressions.

5.1.1. Inductor Design

The transversality condition of the current ASMC requires fulfilling the $L_2$ restriction given in (36). Therefore, the most extreme case corresponds to the higher d value occurring at the maximum $v_o$ condition, i.e., d calculated from (20) with $v_o=v_r+MO$. Such a restriction for the inductors is summarized as follows:

$$\begin{array}{c}\hfill L_2>d_{max}·L_1\mathsf{where}{d}_{max}=1-{\displaystyle \frac{v_b}{v_o+MO}}\end{array}$$

(54)

$$\begin{array}{c}\hfill K_L={\displaystyle \frac{L_2}{L_1}}\Rightarrow K_L>d_{max}\end{array}$$

(55)

The value of $L_1$ is defined to impose a desired current ripple $\Delta i_b$ to the battery, which is calculated from Equation (28) in stand-by mode, as given in (56). Moreover, $L_2$ is calculated as given in (57) to fulfill the transversality condition.

$$\begin{array}{c}\hfill L_1\ge {\displaystyle \frac{v_b·d}{2·\Delta i_b·F_{sw}}}·\left(1+{\displaystyle \frac{1}{K_L}}\right)\end{array}$$

(56)

$$\begin{array}{c}\hfill L_2=L_1·K_L\end{array}$$

(57)

5.1.2. Capacitor Design

The reachability conditions of the current ASMC require fulfilling the dynamic restrictions (39) and (40) for the reference current derivative ${\displaystyle \frac{d{i}_r}{dt}}$, which is generated by the voltage controller. Since the previous $i_r$ derivative limits have different magnitudes, the lowest one (in stand-by mode) defines the safe design limit:

$$\begin{array}{c}\hfill lim\left({\displaystyle \frac{d{i}_r}{dt}}\right)=min\left(v_o-v_b,v_b\right)·\left({\displaystyle \frac{1}{d·L_1}}-{\displaystyle \frac{1}{L_2}}\right)\end{array}$$

(58)

Therefore, to fulfill the reachability restrictions (39) and (40), we needed to ensure that the maximum value of the reference current derivative is always lower than the limit (58):

$$\begin{array}{c}\hfill max\left({\displaystyle \frac{d{i}_r}{dt}}\right)<lim\left({\displaystyle \frac{d{i}_r}{dt}}\right)\Rightarrow max\left({\displaystyle \frac{d{i}_r}{dt}}\right)<min\left(v_o-v_b,v_b\right)·\left({\displaystyle \frac{1}{d·L_1}}-{\displaystyle \frac{1}{L_2}}\right)\end{array}$$

(59)

The dynamic behavior of the reference current is calculated from the block diagram at the bottom of Figure 3, disregarding the term $R_{Co}·C_o$ due to its small value. Then, including the normalization (47), the following expression is obtained:

$$\begin{array}{c}\hfill i_r=G_{irN}·i_o\mathsf{where}{G}_{irN}={\displaystyle \frac{k_{pN}·s+k_{iN}}{C_o·s^2+k_{pN}·s+k_{iN}}}\end{array}$$

(60)

Considering the same maximum perturbation $i_o={\displaystyle \frac{\delta i_o}{s}}$ discussed in the previous section, the time-domain waveform of the reference current is calculated as $i_r={\mathcal{L}}^{-1}\left\{G_{irN}·{\displaystyle \frac{\delta i_o}{s}}\right\}$, resulting in the following expression:

$$\begin{array}{c}\hfill i_r=\delta i_o·\left[1-exp\left({\displaystyle \frac{-k_{pN}·t}{2·C_o}}\right)+{\displaystyle \frac{k_{pN}·t}{2·C_o}}·exp\left({\displaystyle \frac{-k_{pN}·t}{2·C_o}}\right)\right]\end{array}$$

(61)

Then, the reference current derivative is calculated as given in (62). The maximum value of such a function occurs at $t=0$, resulting in the maximum current reference derivative reported in (63).

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_r}{dt}}={\displaystyle \frac{\delta i_o·k_{pN}}{C_o}}·\left[exp\left({\displaystyle \frac{-k_{pN}·t}{2·C_o}}\right)-{\displaystyle \frac{k_{pN}·t}{4·C_o}}·exp\left({\displaystyle \frac{-k_{pN}·t}{2·C_o}}\right)\right]\end{array}$$

(62)

$$\begin{array}{c}\hfill max\left({\displaystyle \frac{d{i}_r}{dt}}\right)={\displaystyle \frac{\delta i_o·k_{pN}}{C_o}}\end{array}$$

(63)

Replacing Equation (63) into (59) leads to the stability limit of $C_o$:

$$\begin{array}{c}\hfill C_o>{\displaystyle \frac{\delta i_o·k_{pN}}{min\left(v_o-v_b,v_b\right)·\left(\frac{1}{d·L_1}-\frac{1}{L_2}\right)}}\end{array}$$

(64)

The intermediate capacitor is calculated, using Equation (25), to provide a desired voltage ripple in $v_{Ci}$. From Equations (9) and (10) it is observed that the ripple on $v_{Ci}$ affects the inductor current derivatives, hence such a voltage ripple must be small to ensure a high precision on the current ripples magnitude. This condition is needed to ensure an accurate limitation of the switching frequency; therefore, a small ripple (lower than $2\%$) is needed. Finally, $C_i$ is calculated by solving (25) as follows:

$$\begin{array}{c}\hfill C_i={\displaystyle \frac{\delta i_o·d}{2·\Delta v_{Ci}·F_{sw}}}\end{array}$$

(65)

5.1.3. Synthesis of the System Process

The integration of the electrical components calculation and control design, using a unified process, impose a direct effect of the components values into the system performance (global stability, $MO$, $t_s$, ripples). The synthesis of such a design process, considering stand-by mode, is reported in Algorithm 1. The first step is to calculate $d_{max}$, which is used to calculate the stable relation $K_L$ between the inductors. Since expression (55) provides a minimum value for $K_L$, in Algorithm 1, selecting double the stability limit to account for inductance tolerances is recommended. Then, the stand-by duty cycle is also calculated.

Algorithm 1 Design of the power stage parameters

Require:  $v_b$, $v_r$, $MO$, $\delta i_o$, $F_{sw}$, $\Delta i_b$, $\Delta v_{Ci}$, $t_s$, $ϵ$ 1: $d_{max}\leftarrow \left\{1-{\displaystyle \frac{v_b}{v_r+MO}}\right\}$ 2: $K_L\leftarrow \left\{2·d_{max}\right\}$ 3: $d\leftarrow \left\{1-{\displaystyle \frac{v_b}{v_r}}\right\}$ 4: $L_1\leftarrow$ near commercial value of $\left\{{\displaystyle \frac{v_b·d}{2·\Delta i_b·F_{sw}}}·\left(1+{\displaystyle \frac{1}{K_L}}\right)\right\}$ including tolerance 5: $L_2\leftarrow$ near commercial value of $\left\{L_1·K_L\right\}$ including tolerance 6: $C_i\leftarrow$ near commercial value of $\left\{{\displaystyle \frac{\delta i_o·d}{2·\Delta v_{Ci}·F_{sw}}}\right\}$ including tolerance 7: $k_{pN}\leftarrow \left\{{\displaystyle \frac{2·\delta i_o·exp\left(-1\right)}{MO}}\right\}$ 8: repeat 9:     $C_o\leftarrow$ commercial value higher than $\left\{{\displaystyle \frac{\delta i_o·k_{pN}}{min\left(v_r-v_b,v_b\right)·\left(\frac{1}{d·L_1}-\frac{1}{L_2}\right)}}\right\}$ including tolerance 10:     $G_0\leftarrow {\displaystyle \frac{-\delta i_o}{C_o·\left(1+k_{pN}·R_{Co}\right)}}$ 11:     $P\leftarrow {\displaystyle \frac{k_{pN}}{C_o·\left(1+k_{pN}·R_{Co}\right)}}$ 12:     $t_s^{*}\leftarrow$ solve $\left\{ϵ·v_r-G_0·t_s^{*}·exp\left(-t_s^{*}·{\displaystyle \frac{P}{2}}\right)=0\right\}$ 13:     if $t_s^{*}>t_s$ then 14:         $C_o\leftarrow$ decrease to the near commercial value 15:     end if 16: until$t_s^{*}\le t_s$ 17: $k_{iN}\leftarrow \left\{{\displaystyle \frac{k_{pN}^2}{4·C_o·\left(1+k_{pN}·R_{Co}\right)}}\right\}$ 18: return$L_1$, $L_2$, $K_L$, $C_o$, $C_i$, $k_{pN}$, $k_{iN}$

The next step is to calculate the inductor $L_1$ to ensure the desired battery current ripple; this selection must take into account the inductor tolerance, hence it is selected as a commercial value higher than the calculated value. The selection of $L_2$ is performed next, also taking into account the element tolerance. Finally, the intermediate capacitor is also calculated, taking into account the element tolerance.

Then, the normalized parameter $k_{pN}$ of the voltage controller is calculated, which is used in an iterative loop to calculate the bus capacitor to fulfill two conditions: ensure the reachability conditions of the ASMC, and fulfill the desired settling time for the bus voltage calculated from (50). If the settling time is not fulfilled, the $C_o$ capacitor must be decreased until the desired value is reached. Finally, the normalized parameter $k_{iN}$ is calculated.

Algorithm 1 can be executed in any calculation software or programming language, and it can be used to automatize the design process. Section 6 will illustrate this algorithm with an application example.

It must be noted that the minimum value of $L_1$ is defined (56) to ensure the desired battery current ripple, and the minimum value of $L_2$ is defined in (57) to ensure stability. Similarly, the minimum value of $C_o$ is defined in (64) to ensure stability, and the minimum value of $C_i$ is defined in (65) to ensure the desired voltage ripple in the intermediate capacitor. It is recommended to select values around those limits, which would account for the tolerances of the commercial devices. However, values much larger than those limits will increase both the size and cost of the battery charger/discharge; thus, a balance between safe values and cost must be considered.

5.2. Switching Circuit

The next hardware to design is the switching circuit needed to implement the practical control law (42). Such a control law needs two analog comparisons and a memory device to keep the value of u; in addition, the power stage requires the complement of u, i.e., $\overline{u}=1-u$. Those functions are implemented as reported in Figure 4, where two classical (analog) comparators are used to detect the $\Psi >+\Delta \Psi$ and $\Psi <-\Delta \Psi$ conditions. The control signal u and its complement $\overline{u}$ are generated using an S-R flip-flop; thus, this compact switching circuit only requires three components: two classical comparators and an S-R flip-flop. The input signals for the switching circuit ($\Psi$, $+\Delta \Psi$, and $-\Delta \Psi$) are generated using a digital signal processor (DSP) running the control algorithm described in the next subsection.

5.3. Control Algorithm

The generation of the input signals for the switching circuit, i.e., $\Psi$, $+\Delta \Psi$, and $-\Delta \Psi$, requires the measurement of $i_{L2\left(k\right)}$, $v_{o\left(k\right)}$, and $v_{b\left(k\right)}$. Then, the instantaneous duty cycle is calculated, which is used to estimate $i_{L1\left(k\right)}$ current and adapt the voltage controller (PI) parameters in real-time. The next step is to calculate the reference current $i_r$ for the ASMC as the output of the adaptive PI controller, which is used to calculate the switching function $\Psi$. Then, the adaptive hysteresis band $[+\Delta \Psi ,-\Delta \Psi ]$ is calculated to provide a fixed frequency. Finally, the switching function ($\Psi$) and the limits of the hysteresis band ($+\Delta \Psi$ and $-\Delta \Psi$) are provided to the switching circuit. This real-time control circuit is summarized in the Algorithm 2, and its effectiveness is validated in Section 6 and Section 7.

Algorithm 2 Control algorithm
Require: $v_r$, $L_1$, $K_L$, $F_{sw}$, $k_{pN}$, $k_{iN}$, $\Delta T_p$
1:	loop
2:	measure $i_{L2\left(k\right)}$, $v_{o\left(k\right)}$, $v_{b\left(k\right)}$
3:	$x_{a\left(k\right)}\leftarrow -v_{o\left(k\right)}-i_{L2\left(K\right)}·\left(R_{L1}+R_{L2}\right)$
4:	$x_{b\left(k\right)}\leftarrow -v_{b\left(K\right)}+2·v_{o\left(K\right)}+2·i_{L2\left(K\right)}·R_{L2}$
5:	$x_{c\left(k\right)}\leftarrow v_{b\left(K\right)}-v_{o\left(K\right)}-i_{L2\left(K\right)}·\left(R_{on}+R_{L2}\right)$
6:	$d_{\left(k\right)}\leftarrow {\displaystyle \frac{-x_{b\left(K\right)}+\sqrt{x_{b\left(K\right)}^2-4·x_{a\left(K\right)}·x_{c\left(K\right)}}}{2·x_{a\left(K\right)}}}$	▹ Calculate the duty cycle
7:	$i_{L1\left(k\right)}\leftarrow \left\{{\displaystyle \frac{d_{\left(k\right)}}{1-d_{\left(k\right)}}}·i_{L2\left(k\right)}\right\}$	▹ Estimate $i_{L1}$ value
8:	$k_{p\left(k\right)}\leftarrow \left\{{\displaystyle \frac{d_{\left(k\right)}}{1-d_{\left(k\right)}}}·k_{pN}\right\}$	▹ Adaptive $k_p$ value
9:	$k_{i\left(k\right)}\leftarrow \left\{{\displaystyle \frac{d_{\left(k\right)}}{1-d_{\left(k\right)}}}·k_{iN}\right\}$	▹ Adaptive $k_i$ value
10:	$e_{v\left(k\right)}\leftarrow \left\{v_r-v_{o\left(k\right)}\right\}$	▹ Bus voltage error
11:	$\int e_{v\left(k\right)}\leftarrow \left\{\left[\int e_{v(k-1)}\right]+e_{v\left(k\right)}·\Delta T_p\right\}$	▹ Integral of the error
12:	$i_{r\left(k\right)}\leftarrow \left\{k_{p\left(k\right)}·e_{v\left(k\right)}+k_{i\left(k\right)}·\int e_{v\left(k\right)}\right\}$	▹ Current reference for the ASMC
13:	${\Psi }_{\left(k\right)}\leftarrow \left\{i_{r\left(k\right)}-{\displaystyle \frac{i_{L1\left(k\right)}}{d_{\left(k\right)}}}+i_{L2\left(k\right)}\right\}$	▹ Adaptive switching function
▹ Adaptive hysteresis band:
14:	$\Delta \Psi \leftarrow \left\{{\displaystyle \frac{d_{\left(k\right)}·\frac{v_{b\left(k\right)}-\left(i_{L1\left(k\right)}+i_{L2\left(k\right)}\right)·R_{on}-i_{L2\left(k\right)}·\left(R_{L2}+R_{Ci}\right)}{K_L}-\left[v_{b\left(k\right)}-\left(i_{L1\left(k\right)}+i_{L2\left(k\right)}\right)·R_{on}-i_{L1\left(k\right)}·R_{L1\left(k\right)}\right]}{2·L_1·F_{sw}}}\right\}$
15:	$\int e_{v(k-1)}\leftarrow \int e_{v\left(k\right)}$	▹ Store $\int e_{v\left(k\right)}$ value
16:	return $+\Delta {\Psi }_{\left(k\right)}$, ${\Psi }_{\left(k\right)}$, $-\Delta {\Psi }_{\left(k\right)}$	▹ Signals for the switching circuit
17:	end loop

6. Application Example and Simulation Results

The 12 V DC microgrid has been the standard for decades, thanks to the automotive industry. Still, current power demands have pushed it to its limits: high currents generate voltage drops and inevitable thermal losses. Increasing cable thickness is no longer viable due to weight and cost. Therefore, migrating to 48 V is the most practical option.

The 48 V DC bus is emerging as a key solution for increasing energy efficiency and reducing cable weight in high-power applications. In factories and robotics, it powers motors, actuators, and sensors with lower $I^{2}R$ losses and better motion control. In hospitals, it powers critical medical equipment, ensuring continuity and safety. Data centers are adopting 48 V racks for servers and GPUs, which reduces distribution losses and improves power density. In telecommunications, it supports 5G base stations and backup systems with 48 V batteries. The automotive industry utilizes it for 48 V mild-hybrid architectures, where it manages start-up, steering, and auxiliary systems, complementing the existing 12 V network. The standardization of 48 V reduces costs, simplifies integration, and accelerates the transition to more efficient and sustainable systems. The integrated converter/controller design proposed in this paper can be applied to multiple industrial systems requiring DC/DC conversions.

The case study proposed in this section illustrates both the design and control processes for the battery charger/discharger. The example, whose requirements are outlined in

Table 1. Application data.

Requirement	Value
Battery voltage ($v_b$)	12 V
Reference for Bus voltage ($v_r$)	48 V
Maximum load current perturbation $max\left(\delta i_o\right)$	2 A
Maximum safe deviation the bus voltage ($MO$)	2 V
Maximum settling time of the bus voltage ($t_s$) for $ϵ=2\%$ band	1 ms
Maximum current ripple for the battery ($\Delta i_b/i_b$)	20%
Maximum voltage ripple for the intermediate capacitor ($\Delta v_{Ci}/v_{Ci}$)	2%
Switching frequency ($F_{sw}$)	50 kHz

, examines the interface between the traditional 12 V DC bus and the promising 48 V DC bus, which is prevalent in multiple industrial applications as previously discussed. The power is limited to 100 W, and therefore, the load current is limited to 2 A. Then, a maximum voltage deviation defined at ±2 V and the settling time at 1 ms ensure compliance with the ISO 21780:2020 standard (mild-hybrid) [19] and with future standards being developed for BEVs (Battery Electric Vehicles) and PHEVs (Plug-in Hybrid Electric Vehicles). The battery current ripple ($\Delta i_b$) is designed to be a 20% of the steady-state current ($i_b$) to prevent damages, while the voltage ripple ($\Delta v_{Ci}$) in the intermediate capacitor is set to 2% of the steady-state voltage ($v_{Ci}$) to avoid large voltage oscillations in the inductors. Finally, the switching frequency of the power stage ($F_{sw}$) is set to 50 kHz to enable the controller implementation in a low-cost device and minimize switching losses.

The parameter calculation is performed following the Algorithm 1. First, the $d_{max}=0.76$ value is calculated, which leads to $K_L=1.5$. Then, $d=0.75$ is used to calculate $L_1=93.75\mathsf{\mu }$H, and including a 5% tolerance leads to the near commercial values for $L_1=100\mathsf{\mu }$H and $L_2=150\mathsf{\mu }$H. The commercial inductor PQ108081-101MHF [20] from ITG Electronics (NY, USA) is selected for $L_1$, which has an ESR $R_{L1}=22\mathrm{m}\Omega$; similarly, the commercial inductor 60B154C [21] from Murata Power Solutions (Atlanta, USA) is selected for $L_2$, which has an ESR $R_{L2}=38\mathrm{m}\Omega$.

The next calculation yields $C_i=15.62\mathsf{\mu }$F, and including a 20% tolerance leads to the nearest commercial value for $C_i=22\mathsf{\mu }$F; the commercial capacitor R75GW5220AA00J [22] from KEMET (Taipei, Taiwan) is selected, which has an ESR equal to $R_{Ci}=2.2\mathrm{m}\Omega$. The normalized $k_{pN}$ parameter for the voltage controller must be calculated first to ensure the maximum overshoot restriction, resulting in $k_{pN}$ = 0.7358 A/V. Finally, the bus capacitor is calculated as $C_o=18.4\mathsf{\mu }$F, and including a 20% tolerance and 25% for safety factor leads to the commercial value $C_o=44\mathsf{\mu }$F; this value is selected in order to have two parallel-connected $22\mathsf{\mu }$F R75GW5220AA00J capacitors, which provides redundancy in the case of one capacitor failure, and an ESR equal to $R_{Co}=1.1\mathrm{m}\Omega$. Following the procedure reported in Algorithm 1, the $C_o$ commercial capacitor imposes a settling time of $t_s$ = 0.56 ms < 1 ms, thus fulfilling the application requirements. Then, the normalized $k_{iN}$ = 3.0758 kA/(V·s) parameter for the voltage controller is calculated. Finally, two N-channel MOSFETs AOB290L [23] from Alpha & Omega (Sunnyvale, CA, USA) are selected, which have on-resistances $R_{on}=3.2\mathrm{m}\Omega$.

Table 2. System parameters.

Parameter	Part	Value	Cost
$K_L$	—	$1.5$	—
$L_1$ and $R_{L1}$	PQ108081-101MHF	$100\mathsf{\mu }$H and $22\mathrm{m}\Omega$	USD 9.2
$L_2$ and $R_{L2}$	60B154C	$150\mathsf{\mu }$H and $38\mathrm{m}\Omega$	USD 2.42
$C_i$ and $R_{Ci}$	R75GW5220AA00J	$22\mathsf{\mu }$F and $2.2\mathrm{m}\Omega$	USD 6.13
$C_o$ and $R_{Co}$	two parallel R75GW5220AA00J	$44\mathsf{\mu }$F and $1.1\mathrm{m}\Omega$	USD 12.26
MOSFET $R_{on}$	two AOB290L	$3.2\mathrm{m}\Omega$	USD 9.44
$k_{pN}$	—	0.7358 A/V	—
$k_{iN}$	—	3.0758 kA/(V·s)	—

summarizes the system parameters.

6.1. Circuital Simulation of the NEC Battery Charger/Discharger

The proposed power stage (Figure 1) was implemented in the power electronics simulator PSIM ver. 2020 [24] from Powersim (Troy, MI, USA) using the inductors, capacitors and MOSFETs listed in Table 2. Moreover, the switching circuit depicted in Figure 4 was also implemented in PSIM using analog comparators and a flip-flop S-R. Finally, the control algorithm (Algorithm 2) was coded in C-language and implemented in PSIM using a C-block, which simulates the operation of a microprocessor.

The first simulation, reported in Figure 5, considers fast load current perturbations (10 kA/s) with an amplitude of 2 A (as defined in Table 1). Figure 5a shows the system operation under discharge ($i_o>0$), stand-by ($i_o=0$) and charge ($i_o<0$) conditions, where the DC bus voltage $v_o$ is stable and constrained to the required safe range [46 V, 50 V]; in addition, the control system ensures a null steady-state error for all conditions. Figure 5a also confirms the correct operation of the current ASMC, since the $i_{L1}$ current performs a correct tracking of the reference $i_r$ generated by the voltage controller. The stability of the power stage is evident in the stable waveform of $v_{Ci}$, which fulfills the stable relation given in Equation (25). Finally, Figure 5a confirms the continuous condition of the battery current, thus avoiding the large current harmonics present in the classical boost converter.

Figure 5b shows a zoom of the same simulation for the first current transient, i.e., between [6 ms, 6.7 ms]. This figure confirms that the maximum deviation ($MO$) and maximum settling time ($t_s$), defined in Table 1, are fulfilled. In addition, the correct tracking of $i_r$ is evident, since the average value of $i_{L1}$ is equal to $i_r$. Figure 5b depicts the switching function $\Psi$, which is always trapped inside the hysteresis band $\pm \Delta \Psi$, thus confirming the stability of the ASMC. Finally, the continuous waveform of the battery current enables us to calculate the current ripple $\Delta i_b$ = 1.5 A, which fulfills the design restriction listed in Table 1.

The second simulation, reported in Figure 6, illustrates the capability of the proposed solution to provide a fixed switching frequency. First, Figure 6a shows the system behavior with a classical hysteresis band (fixed $\Delta \Psi$), which allows a stable operation but with variable switching frequency. The simulation considers ±10% variations in the battery voltage, where the DC bus voltage is correctly regulated with some variations in the voltage ripple. Similarly, the switching function $\Psi$ is trapped inside the hysteresis band, which is constant since $\Delta \Psi$ is a fixed value. This classical (fixed) band produces a change in the switching frequency of up to 27%, which is the condition that must be avoided.

In contrast, the operation of the proposed solution based on the adaptive hysteresis band (44) is observed in Figure 6b. This test considers the same variations on the battery voltage, obtaining also a correct regulation of the DC bus voltage with an almost constant ripple. However, in this case, the hysteresis band $\Delta \Psi$ is adapted to compensate for the perturbations on $v_b$, ensuring a stable ASMC operation. Finally, this simulation confirms the correctness of the proposed strategy since the switching frequency is constant and equal to the desired value, thus removing the classical disadvantage of sliding-mode controllers.

In conclusion, the NEC converter-based charger/discharger system was simulated at five different operating points, as shown in

Table 3. Specification of the operating points for the NEC converter simulations.

Operating Point	${\mathit{v}}_{\mathit{o}}$	${\mathit{v}}_{\mathit{b}}$	${\mathit{i}}_{\mathit{o}}$
1	48 V	13 V	+2 A
2	48 V	12 V	−2 A
3	48 V	12 V	0 A
4	48 V	12 V	+2 A
5	48 V	11 V	+2 A

. It can be verified that in all cases it meets the requirements listed in Table 1, ensuring global stability and a safe DC bus voltage with a constant switching frequency.

6.2. Comparison with a Classical Battery Charger/Discharger Based on a Boost Converter

The bidirectional boost converter is widely adopted to design battery chargers/dischargers. Such a preference is based on the small size of the circuit, control simplicity, and continuous input current, which prevents high-frequency current components from entering the battery. Figure 7 shows a classical battery charger/discharger based on a bidirectional boost converter, which also includes the parasitic resistances on the MOSFETs, inductor, and bus capacitor. Such a circuit highlights the main problem of this classical solution: the output current $i_{out}$ delivered to the DC bus capacitor is defined by the second MOSFET ($MO{S}_2$) current, which is discontinuous. This undesired condition forces the bus capacitor ($C_{ob}$ in Figure 7) to filter the discontinuous output current $i_{out}$, thus requiring a much larger bus capacitor in comparison with the proposed NEC battery charger/discharger.

In order to evaluate the performance of the proposed solution, the parameters and control system of the bidirectional boost converter were calculated following the procedure reported in. Such a calculation was focused on providing a fair comparison; thus, the boost parameters must ensure the same input current ($i_b$) and output voltage ($v_o$) ripples, with the same switching frequency. The inductor of the boost converter was calculated as $L_b=65\mathsf{\mu }$H, where the commercial inductor 7443783533650 from Wurth Elektronik (Watertown, MA, USA) can be used; such an inductor has a series resistance $R_{Lb}=14.44\mathrm{m}\Omega$ and a cost of USD 13.46. Since the bus capacitor must filter the discontinuous output current of the boost structure, achieving the desired output voltage ripple requires a very large bus capacitance $C_{ob}=440\mathsf{\mu }$F, which is 10 times higher than the bus capacitor of the NEC solution. Such a bus capacitance can be obtained by using 20 parallel R75GW5220AA00J capacitors, resulting in $R_{Cob}=0.11\mathrm{m}\Omega$. Finally, the MOSFETs are the same ones used in the NEC solution, i.e., AOB290L with $R_{on}=3.2\mathrm{m}\Omega$.

Figure 8 shows the circuital simulations of both boost and NEC battery charger/dischargers. The top of Figure 8a reports the input (battery) currents $i_b$ imposed by both solutions, where it is confirmed that both converters provide the same current harmonics. This is confirmed at the top of Figure 8b, which shows the single-sided amplitude spectrums of the input currents: both solutions produce the same harmonic content, where the main component occurs at the switching frequency (50 kHz). The middle waveforms in Figure 8a correspond to the bus voltages $v_o$, where the NEC solution imposes a sinusoidal ripple due to the output second-order filter, while the boost solution imposes a triangular ripple due to the first-order filter at its output. In both cases the amplitude of the bus voltage $v_o$ ripple is the same. The middle waveforms in Figure 8b show the single-sided amplitude spectrums of those bus voltages, which are equivalent: since the NEC converter has a sinusoidal waveform, its harmonic content at 50 kHz is higher, but the harmonic components at higher frequencies are lower than the components produced by the boost converter. Those simulations confirm the correct design of the classical boost converter as a charger/discharger.

The bottom of Figure 8a shows the output current $i_{out}$ for both battery charger/dischargers, where $i_{out}=i_{L2}$ for the NEC converter and $i_{out}=i_{MOS2}$ for the boost converter. Those simulations confirm the continuous characteristic of the output current in the NEC solution, and the discontinuous output current of the boost solution is also observed. The bottom of Figure 8b shows the single-sided amplitude spectrums of those output currents, where the boost converter introduces a much higher harmonic content into the DC bus capacitor. Such a condition can be quantified by calculating an equivalent Total Harmonic Distortion for DC signals $TH{D}_{DC}$ as given in (66), where $I_{DC}$ is the DC single-sided amplitude (0 Hz), and $I_2,I_3,I_4,\cdots$ are the single-sided amplitude at higher frequencies. The resulting $TH{D}_{DC}$ value for the NEC solution is $TH{D}_{NEC}=0.246$, while the boost solution produces $TH{D}_{Boost}=2.493$, hence the classical boost solution introduces 10 times more harmonic content than the proposed NEC alternative.

$$\begin{array}{c}\hfill TH{D}_{DC}={\displaystyle \frac{\sqrt{I_2^2+I_3^2+I_4^2+\cdots }}{I_{DC}}}\end{array}$$

(66)

Wang et al. demonstrated in [25] that the reliability of DC buses is reduced when the capacitance is increased. Therefore, taking into account that the boost battery charger/discharger requires 10 times the bus capacitors used in the NEC battery charger/discharger, the proposed NEC solution significantly improves the DC bus reliability. Moreover, the work in [25] also demonstrates that high current ripples in DC bus capacitors affect the capacitor health due to the large current stress. We observe from the bottom traces of Figure 8b that the NEC solution imposes a much smaller current stress on the bus capacitor, thus reducing the capacitor degradation.

Concerning the overall energy stored in both circuits, the boost converter requires 6.51 times the energy used by the NEC solution, thus the proposed solution is more sustainable. Finally, the element cost of the NEC solution, calculated from Table 2, is USD 39.45, while the element cost of the boost solution is USD 145.5. Therefore, the elements of the proposed NEC battery charger/discharger are 73% cheaper in comparison with the classical boost solution, which improves the sustainability of battery chargers/dischargers and DC microgrids.

7. Controller Implementation and SIL Verification

Before soldering the first MOSFET on a power board, designers and quality managers share a common concern: will the converter behave as the model predicts when tens of amps and hundreds of volts are flowing? Power semiconductors are unforgiving: a poorly tuned control can trigger surges that destroy switches in microseconds, an unstable current loop can saturate the magnetic core and melt the copper, and poor thermal compensation can reduce lifetime to hundreds of hours instead of years. Simulating the power processing system, whether a DC/DC converter for batteries or other applications, allows us to test thousands of load, fault, and transient scenarios in minutes, with no risk of smoke and no prototyping cost. Pre-simulation not only saves material and time; it is the only way to certify that, when the final hardware comes to life, it will respond with the accuracy, efficiency, and robustness that safety standards and users demand [26,27,28,29,30].

The SIL (Software-in-the-Loop), PIL (Processor-in-the-Loop), and HIL (Hardware-in-the-Loop) simulation methods form a progressive sequence of embedded system validation, each located at a different point in the development flow and with an increasing level of integration of physical components. SIL runs entirely in a workstation environment: the control model and the plant model reside on the same computer, both compiled for the native architecture. This stage allows running thousands of test cases in minutes, obtaining code coverage and debugging with conventional software tools; however, it ignores rounding phenomena, memory limits, and latencies specific to the target microcontroller. It is, therefore, ideal for validating logic, control algorithms, and early regression testing, but does not detect stack overflow errors or data type incompatibility [31,32,33].

PIL introduces the first layer of realism by moving the control code to the physical target CPU, while the plant continues to be simulated on the computer. The test environment is connected via a serial channel, JTAG, or Ethernet, synchronizing data frames between the two domains. In this way, the numerical behavior (floating or fixed-point), memory usage, and latency of real interrupts are validated, but without the need for sensors and actuators. The simulation speed is 10 to 100 times slower than SIL, but still sufficient for functional testing and performance benchmarks. In addition, it allows measuring CPU load and isolating cross-compilation failures before reaching the prototype [34,35,36,37,38,39].

HIL represents the most complete stage: the plant is replaced by a hardware simulator that dynamically emulates sensors and actuators, while the control runs on the final electronic control unit (ECU). The simulator generates real electrical signals (PWM, CAN, Ethernet TSN, currents, voltages) and can inject faults such as short circuits or electromagnetic noise. Fidelity is maximized, but so is the infrastructure cost and setup time for each bench. HIL is used to validate safety standards (ISO 26262, DO-178C) [40,41], final regression tests, and long-duration tests that would be impossible in a real system [42,43,44,45,46,47].

Comparatively, the three approaches complement rather than replace each other. SIL offers the most favorable cost-cover ratio in early phases; PIL bridges the gap between host and target environment, reducing integration surprises; HIL brings the final certainty to the physical world. Execution speed decreases from SIL to HIL, while accuracy and cost increase. In many modern development flows, all three levels are orchestrated in CI/CD pipelines (Continuous Integration-Continuous Deployment), so that commits first pass automated SIL, then PIL, and, after passing coverage and performance thresholds, are promoted to a distributed HIL bank [48,49,50]. This strategy enables early detection of defects, when their correction costs are minimal, while ensuring compliance with safety and regulatory requirements prior to mass production.

7.1. High-Fidelity SIL Simulation

In this work, a SIL simulation is performed, that is, the controller code is executed on the computer, along with the NEC converter model. Communication between the controller and the plant occurs entirely within the simulation environment of the computer. However, this simulation is called a high-fidelity SIL because the effects of the hardware within the software environment are modeled. The behavior of the 12-bit ADC and DAC at a frequency of 100 kSPS is simulated, but the simulation itself is still a completely computer-run process. It is not testing the efficiency of the compiler, the actual latency of the ADC interrupt, or whether the 12-bit code produces memory overflows in the actual microcontroller. The controller logic is being tested to ensure it works correctly, despite the limitations of a 12-bit system and a reduced sampling frequency.

Adding float-to-12-bit integer conversion, and vice versa, along with a fixed sample rate, is very useful in digital controller validation, as it allows three things:

• Check the impact of quantization: verify if the loss of 12-bit resolution (rather than the float precision of a computer) affects the stability or performance of the controller.
• Confirm the impact of discretization: ensure that the chosen sampling rate (e.g., 100 kSPS) is fast enough for the controller and does not introduce a time delay that destabilizes the control loop.
• Test the robustness of the algorithm: ensure that the algorithm can handle the rounding and truncation effects that will inevitably occur in the final hardware.

By doing this, the SIL simulation moves from being a purely functional test to an implementation test. It is the logical intermediate step to gain confidence in the design before moving to the PIL stage, where it will test whether the 12-bit code executes as expected on the physical processor.

Figure 9 shows the component diagram of the SIL simulation system. The NEC Converter component is the switched model of the converter based on differential equations. Its outputs are signals representing the electrical variables of the system, currents and voltages, represented in 64-bit floating point format [51]. Its inputs are two Boolean signals that control the switching of the two MOSFETs in the converter.

A prevalent native data type in modern microcontrollers or digital signal processors (DSP) is the 32-bit floating point [51], so before introducing the electrical variables to the ADC, the outputs of the NEC Converter component, which are 64-bit floats, are converted to 32-bit floats. In the same way, the outputs of the Microcontroller component are converted to 64-bit floats for comparison purposes, as this is performed on the computer hosting the SIL simulation.

Within the Microcontroller component, as shown in Figure 10, three key components are visible: the 12-bit ADC converter (ADC_12bit component) and 12-bit DAC converter (DAC_12bit component), which operate at a frequency of 100 kSPS, and the 32-bit floating-point CPU (CPU_32bit component), which executes the control law. Before the external signals are passed to the CPU, they must be converted to the 32-bit floating-point format to calculate the control signals.

To take advantage of 100% of the dynamic range of the ADC, and taking into account the simulation results of Figure 5 and Figure 6, before delivering the signals V_o, i_L2, and V_b to the ADC, their offset and maximum value are defined according to

Table 4. Characteristics of the input signals in the simulation with the 12-bit ADC converter.

Signal	Offset	Range	Resolution
Vo	44 V	8 V	19.54 mV/bit
iL2	−3 A	6 A	14.65 mA/bit
Vb	10 V	4 V	0.98 mV/bit

.

7.2. Implementation of the Control Law

The switching circuit reported in Figure 4 performs analog comparisons between the switching function $\Psi$ and the adaptive hysteresis limits $\pm \Delta \Psi$, both generated inside a microcontroller. This requires high precision to ensure that $\Psi$ is always trapped inside $\pm \Delta \Psi$, thus requiring very high sampling frequencies for the ADC inside the microcontroller. This problem can be avoided by isolating the high-frequency component of $\Psi$: from the expression of the control objective $O_1$, given in (29), it is observed that the current ripple of $O_1$ is zero since $i_{L2}=i_{L1}·(1-d)/d$. Moreover, from the expression of the control objective $O_2$, given in (30), it is observed that the current ripple of $O_2$ is equal to the ripple in $i_{L1}$. Therefore, the high-frequency component of $\Psi$ corresponds to the high-frequency component of $i_{L1}$.

Based on the previous analysis, the real-time implementation of the switching function must be modified to remove the high-frequency component from the ADC. This modification takes into account that the ASMC control law (42) sets the flip-flop ($u=1$) when $\Psi >\Delta \Psi$, and resets the flip-flop ($u=0$) when $\Psi <-\Delta \Psi$. Then, replacing the expression of $\Psi$ reported in (31) to isolate $i_{L1}$ leads to the modified control law given in (67). Such an expression provides the hysteresis band for the switching circuit in terms of $i_{L1}$, which is directly connected to the analog comparators, thus avoiding the requirement of high sampling frequencies since the hysteresis band can be calculated once or twice for each switching period. In fact, for this implementation, the sampling frequency is set to twice the switching frequency, i.e., 100 kSPS (${10}^5$ samples per second), which is available in many low-cost microcontrollers.

$$\begin{array}{c}\hfill \left\{\begin{array}{ccc}\mathsf{Set}\mathsf{condition}(u=1):\Psi >\Delta \Psi & \Rightarrow & d·\left(i_r+i_{L2}-\Delta \Psi \right)>i_{L1}\\ \mathsf{Reset}\mathsf{condition}(u=0):\Psi <-\Delta \Psi & \Rightarrow & d·\left(i_r+i_{L2}+\Delta \Psi \right)<i_{L1}\end{array}\right\}\end{array}$$

(67)

The modification to the switching circuit that eliminates the need for a high sampling frequency for the ADC is modeled by the AnalogComparator component in Figure 9. The implementation is quite simple as it is shown in Figure 11.

7.3. SIL Simulation Results

This section presents the results of the high-fidelity Software-in-the-Loop (SIL) simulation developed for the NEC converter-based bidirectional charger/discharger. In this simulation the control system runs on the workstation at a realistic speed but incorporates, for the first time in this type of study, the combined effects of 12-bit quantization and the reduced sampling frequency of the ADC and DAC converters present in the final ECU. The objective is to establish a critical comparison against the conventionally accepted solution: the PSIM model, widely used in the industry for its speed and nominal accuracy, but operating with floating-point variables and theoretically infinite resolution.

The dynamic limitations imposed by the embedded hardware, 12-bit sample encoding, and 100 kSPS sampling frequency were integrated in the SIL platform, which allows for the anticipation of saturation phenomena, loss of resolution, and aliasing that could compromise current and voltage regulation during fast load transients. The converter, controller, and test scenarios are the same as those replicated in PSIM and presented in Section 6, so it is possible to isolate the unique influence of quantization and undersampling.

Quantitative analysis focuses on the accuracy of output and intermediate capacitor voltages, inductors and battery currents, and switching frequency. For those variables, the overshoot and settling time are analyzed for load changes, and for the switching frequency to be maintained at around 50 kHz. The above demonstrates the extent to which SIL simulation reveals deviations from models of higher abstraction, which PSIM cannot predict. Therefore, it justified the need of incorporating the real limits of the measurement channel and the control loop for validating critical chargers/dischargers.

The constraints set for the performance of the NEC converter-based charger/discharger were reported in Table 1, and the simulation results using PSIM are reflected in Figure 5 and Figure 6. The SIL simulation of the same system with the same performance constraints is shown in Figure 12. Note that at ±2 A variations in the load, it is evident that the reference for the output voltage, 48 V, and its maximum deviation, ±2 V, are fulfilled. Likewise, the settling time after the change in the load remains around 1 ms. For the intermediate capacitor voltage, a maximum ripple of 2%, ±0.96 V, was defined, which is satisfied. Finally, the switching frequency oscillates around 50 kHz ± 0.2 kHz, i.e., with an error near 0.4%. In this simulation, the battery voltage was kept constant, 12 V, and to draw on the same axis as the charging current, an offset of −12 V was applied.

After detailed analysis of the quantitative results of the PSIM simulation versus the SIL simulation of the NEC-based charger/discharger, it is concluded that the data demonstrates excellent performance of the adaptive sliding mode controller in the SIL environment, even under the restrictive conditions imposed. Quantization of the ADC and DAC to 12 bits, together with a sampling rate reduced to only 100 kSPS, did not compromise the stability and efficiency of the controller, which maintained robust reference tracking and effective disturbance rejection. These results represent a first vote of confidence in the controller design, validating its ability to operate under realistic deployment conditions. Furthermore, the observed performance suggests that the controller could be successfully deployed on a low-cost commercial microcontroller while maintaining its functionality and efficiency. This breakthrough opens the door to future tests on real hardware, where its robustness and adaptability in practical applications are expected to be confirmed, thus consolidating its potential for efficient and affordable power systems.

For comparative purposes, the SIL simulation results of the same system with the same performance constraints, but using a classical PI controller, are reported in Figure 13. There, it can be seen that the output voltage is maintained at 48 ± 2 V, but with a strong oscillation when the load is −2 A, and the settling time is not met, since it is longer than 1 ms. The intermediate capacitor voltage ripple is maintained at around ±1 V, while the switching frequency deviation becomes about 2%, i.e., 1 kHz. As expected, the performance of the adaptive sliding mode controller is much better than that of the classical PI controller.

Table 5. Performance comparison of the NEC converter controlled with sliding-mode controller vs. classical PI controller.

	Variable	Error-SMC	Error-PI	Comparison
Load from 2 A to 0	$v_o$	0.2818 V	0.3657 V	PI 29.8% > SMC
	$v_{Ci}$	0.4375 V	0.6741 V	PI 54.1% > SMC
	$F_{sw}$	45.7756 Hz	70.2216 Hz	PI 53.4% > SMC
	Variable	Error-SMC	Error-PI	Comparison
Load from 0 to −2 A	$v_o$	0.2663 V	0.3464 V	PI 30.1% > SMC
	$v_{Ci}$	0.6220 V	0.7120 V	PI 14.5% > SMC
	$F_{sw}$	55.8947 Hz	260.3202 Hz	PI 365.7% > SMC

shows the performance parameters for the NEC converter controlled by the ASMC compared to the classic PI controller. Errors were calculated using the average absolute value given by $MAE={\displaystyle \frac{1}{N}}\sum \left|y_i-\overline{y_i}\right|$.

The error analysis was performed during two of the three transients: when the load changed from +2 A to 0 A, and when the load changed from 0 A to −2 A. In both cases, the error in the output voltage, the intermediate capacitor voltage, and the switching frequency were greater when the NEC converter was controlled with the classic PI controller. The closest error values between the two controllers occurred in the intermediate capacitor voltage during the 0 to −2 A transient. For the other cases and variables, the system error under the PI controller was greater by more than 30%. It is noteworthy that the switching frequency, in the 0 to −2 A transient, using the PI controller had an average error of 365.7% greater than the proposed sliding mode controller.

It should be noted that during the transition from +2 A to 0, the DC bus voltage when the converter was controlled using the PI controller exceeded 50 V for a short time, which means that it does not meet the requirements for which it was designed. Finally, both solutions provide similar settling times, which in general fulfill the design restriction.

8. Conclusions

This paper presented a novel approach to designing a non-electrolytic capacitor (NEC) DC-DC boost converter for battery charging/discharging applications, focusing on enhancing the sustainability of a microgrid by improving reliability, performance, and extending battery life. The proposed NEC-based solution offers significant advantages over existing alternatives. Unlike the conventional Cuk converter, which exhibits both step-up and step-down capabilities, the NEC converter exclusively operates in the step-up mode. This condition permits fully utilizing the control’s dynamic range (duty cycle between 0 and 1), minimizing the saturation risk and increasing the system flexibility for step-up chargers/dischargers. Furthermore, the NEC converter requires a significantly lower intermediate capacitor voltage than the Cuk (in this case, 60 V for the Cuk and 48 V for the NEC), reducing the voltage stress on components. Also, the above translates to lower energy storage requirements, enabling the use of components with lower voltage ratings, ultimately leading to cost reductions, improved efficiency, and enhanced sustainability of the whole system. While the boost converter also offers step-up functionality, its discontinuous output current challenges battery charging applications. The NEC converter, in contrast, provides continuous currents at both the input (battery side) and output (DC bus side), mirroring the desirable characteristic of the Cuk while avoiding its limitations. An adaptive sliding-mode control strategy was implemented to control the NEC converter effectively. Adaptive SMC offers inherent advantages in robustness against parametric variations and guarantees global stability, a critical aspect often lacking in linear control techniques. Moreover, the adaptive nature of the controller ensures optimal performance across the entire operating range, not just guarantee stability. This design maintains a constant switching frequency (around 50 kHz), unlike classical SMC implementations that suffer from variable switching frequency. The fixed switching frequency allows for the selection of optimized MOSFET characteristics such as T_on, T_off, and R_on, increasing efficiency and reducing the overall size of the converter. The proposed solution was validated through the simulation of an application example that showed accurate results. The controller is particularly well-suited for practical implementation on platforms such as DSPs, as it simplifies the design of sensing filters and reduces hardware requirements. For this reason, the adaptive sliding-mode controller was also specifically tested using a high-fidelity software-in-the-loop (SIL) approach.

Adopting SIL simulations is advantageous over Hardware-In-the-Loop (HIL) or experimental testing because it allows control algorithms to be validated in a purely virtual environment, without the need for physical hardware. This results in lower initial costs and faster iteration speeds, as changes to the software can be tested immediately without reconfiguring real laboratory equipment. In addition, SIL allows thousands of extreme cases or injected faults to be run in minutes, something that is impractical with physical prototypes or real plants. It also facilitates multidisciplinary collaboration by eliminating dependencies on available hardware. Although HIL and real-world testing are crucial in later phases, SIL accelerates the early detection of logical errors and the optimization of control strategies, reducing risks and costs before moving to more expensive validations.

To increase the academic value of this work, which is still in the SIL stage, and to prepare for the HIL/experimental field, the following future works are proposed:

• Quantify the parametric uncertainty of a battery-converter system using Morris–Sobol analysis in SIL to prioritize sensors and calibrations.
• Design and validate an online residual observer that detects and isolates sensor/actuator faults without real hardware.
• Release the SIL model (MATLAB/Simscape) with test cases, which will enable the community to reproduce and compare algorithms.
• Generate a lightweight digital twin model (time step shorter than 1 ms) suitable for microcontrollers, which can be used to demonstrate its functional equivalence against the detailed SIL.
• On the other hand, to prepare this work for different types of simulation scenarios, a hybrid framework of an average/event-driven model for a power converter is proposed, enabling multi-hour simulations of a battery charger/discharger controlled by the ASMC.