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Article

RLC Circuit Forecast in Analog IC Packaging and Testing by Machine Learning Techniques

1
PhD Program in Strategy and Development of Emerging Industries, National Chi Nan University, Nantou 54561, Taiwan
2
Siliconware Precision Industries Co., Ltd., No. 123, Sec. 3, Dafeng Rd., Dafeng Vil., Tanzi Dist., Taichung City 42749, Taiwan
3
Department of Information Management, National Chi Nan University, Nantou 54561, Taiwan
*
Author to whom correspondence should be addressed.
Micromachines 2022, 13(8), 1305; https://doi.org/10.3390/mi13081305
Submission received: 29 June 2022 / Revised: 6 August 2022 / Accepted: 9 August 2022 / Published: 12 August 2022
(This article belongs to the Special Issue Hardware-Friendly Machine Learning and Its Applications)

Abstract

:
For electronic products, printed circuit boards are employed to fix integrated circuits (ICs) and connect all ICs and electronic components. This allows for the smooth transmission of electronic signals among electronic components. Machine learning (ML) techniques are popular and employed in various fields. To capture the nonlinear data patterns and input–output electrical relationships of analog circuits, this study aims to employ ML techniques to improve operations from modeling to testing in the analog IC packaging and testing industry. The simulation calculation of the resistance, inductance, and capacitance of the pin count corresponding to the target electrical specification is a complex process. Tasks include converting a two-dimensional circuit into a three-dimensional one in simulation and modeling-buried structure operations. In this study, circuit datasets are employed for training the ML model to predict resistance (R), inductance (L), and capacitance (C). The least squares support vector regression (LSSVR) with Genetic Algorithms (GA) (LSSVR-GA) serves as an ML model for forecasting RLC values. Genetic algorithms are used to select parameters of LSSVR models. To demonstrate the performance of LSSVR models in forecasting RLC values, three other ML models with genetic algorithms, including backpropagation neural networks (BPNN-GA), random forest (RF-GA), and eXtreme gradient boosting (XGBoost-GA), were employed to cope with the same data. Numerical results illustrated that the LSSVR-GA outperformed the three other forecasting models by around 14.84% averagely in terms of mean absolute percentage error (MAPE), weighted absolute percent error measure (WAPE), and normalized mean absolute error (NMAE). This study collected data from an IC packaging and testing firm in Taiwan. The innovation and advantage of the proposed method is using a machine approach to forecast RLC values instead of through simulation ways, which generates accurate results. Numerical results revealed that the developed ML model is effective and efficient in RLC circuit forecasting for the analog IC packaging and testing industry.

1. Introduction

Circuit simulation work in the integrated circuit (IC) packaging process depends on model complexity in geometry and electromagnetic materials. Properly simulating IC packaging plays a vital role in catching potential EMC, power, and signal integrity issues early in the design process and overcoming major pitfalls. The elimination of manual processing is required to reduce the time and effort from customer requirement specifications to IC packaging design, testing, manufacturing, and to determine the tools and process options for application design. Implementation takes prediction, evaluation, and decision making with machine learning-centric databases, tools, and design models. Learning-based tools and process models must continuously improve through additional design experience [1,2].
Machine learning (ML) solved many problems that were originally difficult to solve in data science. Many studies have shown that machine learning and optimization algorithms are suitable for solving different problems in the IC packaging and design processes, reducing design errors and design cycle time [3]. Table 1 shows the latest research on the IC packaging process using machine learning.
The signal passes through the substrate of the printed circuit board. Simulation provides the designer with a pre-optimized design concept. Ren et al. [4] introduced a graph neural network to predict network parasitics and device parameters by converting circuit schematics into graphs and utilizing key GNN-based modeling techniques. The results showed that the average simulation error was reduced from over 100% and estimated by designers to be less than 10%. Shook et al. [5] proposed a new machine learning-based parasitic estimation method for pre-layout custom circuit designs. For various analog circuits, the results show a reduction in the average error between pre-layout and post-layout circuit simulations from 37% to 8%.
For optimization and evaluation of package structural characteristics, Wu and Chu [6] proposed and verified an analog-driven design method for chip package integration structure design optimization. The study’s results suggest that the random forest algorithm can predict stress for chip package-integrated design. Hsiao and Chiang [7] proposed applying the RF model to predict the reliability of wafer-level packaging. The designers can easily optimize the WLP structure and shorten the design cycle. Lee et al. [8] developed a chip-to-package interactive risk assessment platform using finite element analysis, meta-modeling, and genetic algorithm optimization methods.
Heat transfer analysis of package structures is important in package functional testing. Acharya et al. [9] used three ML algorithms, random forest, support vector regression, and a neural network to model thermal behavior through hotspot temperature simulation data evaluation. They proposed an ML-based thermal design method and provided a reference frame for future packaging materials. Durgam et al. [10] used several machine learning methods to predict the temperature of the heat source on the substrate. The results showed that the temperature agreement between the prediction and the simulation was less than 10%. Jing et al. [11] proposed using the genetic algorithm to optimize the temperature curve prediction model in the reflow soldering process. The results show that the predicted value meets the error accuracy requirements. The results also prove that the established mathematical model can effectively predict temperature curves.
The power delivery network (PDN) must reliably supply power to functional blocks in an integrated circuit (IC). A robust PDN design has always been a critical challenge. Cecchetti et al. [12] developed a Genetic Algorithm (GA) and Artificial Neural Network (ANN) model for iterative optimization of the placement of decoupling capacitors in a PDN. They concluded that the GA-ANN model is consistent with the results of commercial simulator optimization. Sourav et al. [13] presented an ML architecture that combined neural networks and regression trees to predict printed circuit board (PCB) inductance and resistance. They employed an LSTM model to predict voltage drop as a function of time. The average prediction accuracy of the proposed method is 94%.
There have been many models utilizing machine learning and optimization to solve issues in IC packaging. Mao et al. [14] proposed a machine learning (ML) model based on the backpropagation (BP) method for predicting three-dimensional board-level drop responses for ball grid array (BGA) encapsulation structures. Jin et al. [15] constructed several machine learning methods to accurately predict the radiated electric field of wire-bonded ball grid array packages. They optimized model parameters to minimize the prediction error of each model. Their conclusion shows that DNN is an effective and feasible prediction model. Wang et al. [16] proposed a reverse design method based on convolutional neural networks for the fast optimization and design of encapsulation structures. Schierholz et al. [2] provided a database that allows for the study of machine learning tools and techniques in signal integrity, power integrity, and electromagnetic compatibility. It contains printed circuit board (PCB)-based interconnects and physics (PB). The corresponding frequency domain data of the tool can be used for different types of structural simulations.
Table 1. Summary of ML-based IC packaging process applications.
Table 1. Summary of ML-based IC packaging process applications.
LiteratureYearsApplicationMethod(s)
Ren et al. [4]2021Predict net parasitics and device parametersGNN
Shook et al. [5]2020Parasitic estimationRandom forest
Wu and Chu [6]2021The structural design optimization of chip package integrationRandom forest
Hsiao and Chiang [7]2020Packaging reliability analysis and predictionRandom forest
Lee et al. [8]2021Interactive risk assessment of chip packagingFEA, MOGA
Acharya et al. [9]2021Predict the thermal behavior of a power electronics packageRandom forest, SVR, ANN
Durgam et al. [10]2022The optimization of temperature on printed circuit boardXG Boost, ANN, SVR, RFR
Jing et al. [11]2021Predicting the temperature curve of SMT reflow solderingGenetic Algorithm
Cecchetti et al. [12]2020Power delivery network (PDN)ANN, Genetic Algorithm
Sourav et al. [13]2020Power delivery network (PDN)Regressor trees, LSTM
Mao et al. [14]2022Predicting three-dimensional board-level drop responses for ball grid array (BGA) encapsulation structuresBPNN
Jin et al. [15]2022Predicting the radiated electric field of a wire-bonded ball grid array packageDNN, SVR, K-nearest neighbors, LR
Wang et al. [16]2021Full wave radiation simulation of package design processCNN
Schierholz et al. [2]2021Signal integrity (SI) and power integrity (PI) database based on PCB interconnectionANN, Genetic Algorithm
This study attempted to use least squares support vector regression with genetic algorithms to predict the RLC (resistance, inductance, and capacitance) values currently generated by simulation methods. The genetic algorithms were employed to determine LSSVR parameters to improve forecasting accuracy. The designed method employs a machine learning approach to forecast RLC values instead of through simulation ways and generates more accurate results than the three other machine learning models. The rest of this study is organized as follows. Section 2 provides the substrate and interface electrical transfer properties based on IC packages. Section 3 briefs the LSSVR model and genetic algorithms. The flowchart of the LSSVR-GA model for predicting RLC values is also addressed and presented. Numerical results are illustrated in Section 4. Conclusions are indicated in Section 5.

2. The Substrate and Interface of the IC Package Transmit Electrical Properties

In IC packaging design, the substrate is used as a carrier. The functions of the substrate are to protect and carry the IC chip and serve as a medium for circuit signal transmission. Integrated circuit packaging is the final stage of semiconductor component manufacturing. As a method for connecting the die to the external circuit, the chip’s packaging considers the pin configuration, electrical performance, heat dissipation, and the chip’s physical size. There are many typical packaging forms in the semiconductor industry [17,18]. Currently, the most common internal packaging methods of integrated circuits are wire bonding (WB) and flip chip (FC) packages. Flip chip packaging connects the chip to the bump and then turns the IC chip over to directly connect the bump and substrate. The wire bonding package places the chip on the substrate (chip pad) and then uses the wire bonding technology to connect the chip to the connection point on the substrate. The IC substrate acts as a buffer interface for electrical connection and transmission between the IC die and the PCB through the conductive routing and vias (VIA) network, as shown in Figure 1.
The RLC circuit is essential to evaluate the overall interface transmission capability in the IC packaging design process. It is a circuit structure composed of resistors, capacitors, and inductors. Parasitic effects associated with ICs and printed circuit board (PCB) conductors and their paths are essential parameters of the electrical transport model. The parasitic effects of RLC lines in the IC package process can cause signal integrity problems due to signal attenuation and delay [20,21].
In the process of IC substrate generation, the substrate design is first performed according to the target circuit specification. The netlist of the corresponding circuit is associated with performing a post-layout simulation to verify the corresponding layout performance. If the post-layout simulation results are violated, the designer will adjust his layout and re-simulate. Figure 2 shows that this process is repeated until the simulated substrate design conforms to the RLC electrical specifications for interface transmission. The current process requires multiple simulation runs to meet the desired target circuit specification. Therefore, any inaccuracies in the design or components can produce misleading post-layout simulation results. Such misleading results can reduce yield and increase circuit design waste time.
Signal transmission relies on the interconnected line group. According to the transmission line theory, the transmission line calibration model can replace the electrical characteristics of the signal and use an equivalent model. When the system simulation is based on the transmission line calibration model, the substrate RLC model, IC input/output buffer information specification (IBIS) model, and PCB electrical properties model are applied to the system simulations for system verification. The process is shown in Figure 3.

3. Forecasting RLC Values of Integrated Circuits by LSSVR-GA Models

3.1. LSSVR Models with Genetic Algorithms

The LSSVR method can be traced back to the SVM (Support Vector Machine) proposed by Cortes and Vapnik [22]. The SVM can handle classification and regression problems and performs better on small samples. Suykens and Vandewalle [23] proposed LSSVM. It solves the high computational burden problem of the SVM. The problem used to solve regression is called LSSVR [24].
Consider a given data set { x i , y i | i = 1,2,3, …, n}, where x i R d is the ith input data including d features, and y t R is the ith output data. Establishing the model for the LSSVR is as follows in Equation (1):
y   x = ω T · φ x + b
where ω T is the transposed form of the weight matrix, φ x represents a nonlinear function that maps from the original dimensional feature space to a higher dimensional feature space, and b is a bias value.
The optimization problem to be solved by the model is presented as Equation (2):
M i n   F ω ,   e = 1 2 ω T ω + 1 2 γ i = 1 n e i 2 S u b j e c t   t o :   y i = ω T φ x i + b + e i
where F ω ,   b is lose function, γ is the regularization parameter, and e means the random error.
Because of the constraints, the optimal solution to the computational problem is very complicated. The Lagrange function is optimized and presented in Equation (3) to solve this problem:
L ω ,   b ,   e i ,   l i = F ω ,   b i = 1 n l i (   ω T φ x i + b + e i y i )
where L ω ,   b ,   e t ,   l t is the Lagrange function and l is the Lagrange multiplier. After optimization using the KKT condition (Karush–Kuhn–Tucker condition), the formula is described in Equation (4)
L ω = 0 ω = i = 1 n l i φ x i L b = 0 i = 1 n l i = 0 L e i = 0 l i = γ e i L l i = 0   ω T φ x i + b + e i y i = 0
The kernel function K x , x t is considered as follows in Equation (5):
K x , x i = φ x T φ x i
Finally, the model estimation formula by LSSVR can be obtained with Equation (6):
y = i = 1 n l i K x , x i + b
There are common kernel functions such as the string kernel [25], the radial basis function kernel (RBF) [26], and the polynomial kernel [27]. This study used the RBF kernel function in Equation (7), and the RBF kernel utilizes high-dimensional nonlinear mapping to resolve the nonlinear relationship between dependent and independent variables. The RBF kernel learned more complex decision boundaries:
K x , x i = exp ( x x i 2 2 σ 2 )
where σ is the parameter of the RBF kernel function. The decision of these two parameters— γ and σ —would affect the accuracy of the LSSVR model, so GA was performed to optimize these two parameters. The complete concept of GA was advocated by John Holland [28,29]. GA simulates the natural evolution law of natural ecology, imitates the survival of the fittest in the natural group, eliminates the inferior, and converges into a balanced mechanism under repeated iterations. GA is a search method used to solve optimization problems. Genes can select, crossover, and mutate. Better genes are passed to the new generation, and the inferior genes will be eliminated gradually. GA has been widely applied in solving optimization problems, data searches, artificial intelligence, and machine learning.

3.2. LSSVR-GA Architecture for RLC Prediction

Figure 4 illustrates the framework of the LSSVR-GA model in RLC (resistance, inductance, and capacitance) forecasting. It consists of 3 modules: data preprocessing, GA for parameter selection, and the LSSVR model for RLC forecasting. To solve the time-consuming problem of calculating the parameters for complex simulation software while verifying substrate designs, this study proposed a machine learning method to predict the RLC values for different product types.
The experimental data were semi-structured historical data provided by SPIL (Siliconware Precision Industries Co., Ltd.), including two different IC package process products, FC and WB. The historical data of different products of two-layer, four-layer, and six-layer PCB were selected based on these two processes. The three dependent variables for each product are resistance (R), inductance (L), and capacitance (C). The independent variables (X1~Xn) include ball, bump, base, L1, L2, L3, L4, L5, via, and wire. In the data preprocessing stage, this study integrated these scattered semi-structured data into one-to-one corresponding structured data between dependent and independent variables according to product types. It filled the missing values with 0. Table 2 describes the features and samples in predicting RLC for different data sets of substrate products.
The preprocessed data sets were divided into 80% training data and 20% testing data. The training data were used to build the LSSVR model with the parameters optimized by GA. Before applying GA, it is necessary to encode the parameters to be optimized into a group of chromosomes. The common encoding methods include binary, real, multi-objective, parallel, chaotic, and hybrid GA [30]. Considering the simplicity of implementation for factory operators, this study used the binary-coded GA to optimize the parameters of LSSVR, and each digital bit represented a gene. The length of the chromosome was defined according to the spatial range of the actual problem to be solved. The real number represented by the binary encoded was calculated as Equation (8).
R V = L B + i = 1 l d i · 2 i 1 2 l 1 · U B L B
where R V is the real number represented by the binary encoded, L B is the lower bound of the spatial range, U B is the upper bound of the spatial range, l is the encoded bit length, and d i is the bit value of the ith bit.
Figure 5 shows the LSSVR model’s encoded parameters—γ and σ —and the operation of real numbers. Each parameter consists of 10 genes, and the LSSVR model has two parameters. These two parameters represent 20 genes as a chromosome. The lower and upper bounds of the two parameters are both 1 and 500, and the real numbers represented are calculated accordingly. It is also necessary to define the optimized procedure settings of LSSVR-GA. The population size, iteration, crossover rate, and mutation rate were arranged at 40, 20, 0.8, and 0.1, respectively. When starting GA, the parameters must first be initialized as the input parameter of the LSSVR model. The training result of the LSSVR model is calculated by the fitness function. This is to evaluate the stopping conditions for GA. If conditions are not met, it will go through the process as in Figure 6, Figure 7 and Figure 8, and the GA selection-crossover-mutation process will have a new generation. Good chromosomes have more opportunities to be selected. Unfit and less fit chromosomes are gradually eliminated. Therefore, the updated parameters are used as input parameters of the LSSVR model. To find the best-fit parameters of LSSVR, repeat the fitness function to compute the evaluation until the GA stop condition. Then, set the best-fit parameters of LSSVR in the final LSSVR model and perform RLC predictions.

4. Numerical Results

Predicted results are evaluated and analyzed with the testing data to examine the effectiveness and interpretability of the proposed method. The evaluation is measured by mean absolute percentage error (MAPE (%)), weighted absolute percent error measure (WAPE (%)), and normalized mean absolute error (NMAE), as shown in Equations (9)–(11).
M A P E % = 100 n i = 1 n Y ^ i Y i Y i  
W A P E % = 100 i = 1 n Y ^ i Y i i = 1 n Y i
N M A E = 1 m a x   Y m i n Y   1 n i = 1 n Y ^ i Y i
where Y ^ i is the ith predict value, Y i is the ith actual value, and i = 1~n.
Three other forecasting models with genetic algorithms, namely backpropagation neural networks (BPNN-GA), random forest (RF-GA), and eXtreme gradient boosting (XGBoost-GA), were employed to deal with the same data. Table 3 illustrates parameters determined by genetic algorithms to predict LCR values of different forecasting models. Lewis [31] reported that forecasting performance measured by MAPE values could be depicted in Table 4. Table 5 lists the MAPE, WAPE, and NMAE values of the four forecasting models.
The average performance of these six products is at the levels of good or highly accurate in predicting RLC using LSSVR-GA models. Furthermore, the LSSVR-GA models can generate average more accurate results than the other three forecasting models in terms of MAPE, WAPE, and NMAE.

5. Conclusions

This study outlines an efficient method for predicting RLC circuit simulation in the IC package process using LSSVR-GA hybrid models. This method can be used to predict the integrity of RLC circuits. The ability to accurately predict analog circuits is essential to the IC package industry due to the timesaving in substrate design and process optimization. The numerical results revealed that the designed LSSVR-GA method is a feasible, effective, and efficient alternative for forecasting RLC values. For future research, one potential direction is to employ deep learning approaches to cope with the same data sets used in this study to improve forecasting accuracy. The other possible direction is to apply the presented LSSVR-GA framework to more complex circuit cases to examine performance.

Author Contributions

Conceptualization, Y.-P.W. and P.-F.P.; methodology, J.-P.L. and Y.-L.L.; software, J.-P.L. and Y.-L.L.; validation, H.-C.L. and C.-Y.S.; formal analysis, J.-P.L. and Y.-L.L.; data curation, H.-C.L. and C.-Y.S.; writing—original draft preparation, J.-P.L. and Y.-L.L.; writing—review and editing, P.-F.P.; visualization, J.-P.L. and Y.-L.L.; supervision, Y.-P.W. and P.-F.P.; funding acquisition, Y.-P.W. and P.-F.P. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by Siliconware Precision Industries Co., Ltd., grant number 110A052.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Acknowledgments

The raw data of this work were supported by Huei-Chi Yang of Siliconware Precision Industries Co., Ltd.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. IC Package connections with substrate [19]. (a) Flip chip; (b) wire bonding.
Figure 1. IC Package connections with substrate [19]. (a) Flip chip; (b) wire bonding.
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Figure 2. IC substrate generation process.
Figure 2. IC substrate generation process.
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Figure 3. The illustration of RLC model system simulation and verification provided by SPIL (Siliconware Precision Industries Co., Ltd., Taichung City, Taiwan).
Figure 3. The illustration of RLC model system simulation and verification provided by SPIL (Siliconware Precision Industries Co., Ltd., Taichung City, Taiwan).
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Figure 4. The framework of LSSVR-GA model for RLC values prediction.
Figure 4. The framework of LSSVR-GA model for RLC values prediction.
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Figure 5. The LSSVR parameter encoding and operation of representing real numbers.
Figure 5. The LSSVR parameter encoding and operation of representing real numbers.
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Figure 6. The binary encoding for parameters of LSSVR at the stage of initial population.
Figure 6. The binary encoding for parameters of LSSVR at the stage of initial population.
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Figure 7. The binary encoding for parameters of LSSVR after multi-point crossover.
Figure 7. The binary encoding for parameters of LSSVR after multi-point crossover.
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Figure 8. The binary encoding for parameters of LSSVR after mutation from chromosome C to E.
Figure 8. The binary encoding for parameters of LSSVR after mutation from chromosome C to E.
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Table 2. The features and samples in predicting RLC for different substrate products.
Table 2. The features and samples in predicting RLC for different substrate products.
Data SetsFeatures (X Variables)Samples
BallBumpBaseL1L2L3L4L5ViaWireTotal
FC_2L_T11122 2 8 X2232
FC_4L_T1112222 6 16 X999
FC_6L_T11122222210 24 X742
WB_2L_T11 22 218 X1400
WB_4L_T11 2222 6116 X2704
WB_6L_T11 22222210124 X450
Table 3. Parameters of forecasting models provided by genetic algorithms in LCR values prediction.
Table 3. Parameters of forecasting models provided by genetic algorithms in LCR values prediction.
MethodParametersLs (nH)Cs (pF)R (mΩ)Ls (nH)Cs (pF)R (mΩ)Ls (nH)Cs (pF)R (mΩ)
ProductsFC_2L_T1FC_4L_T1FC_6L_T1
GA-LSSVRgamma3.5241220.2197266.8764386.9266388.4704336.2926237.4034386.9266199.8153
sigma490.82692.30061.71761.46923.24764.04662.16501.46921.0638
GA-BPNNlearning rate0.2781630.7259690.3801880.3169920.775010.6681170.6090520.1680280.1674687
momentum0.7906030.4152670.4249050.8038410.7488880.7705310.8647270.8903410.186707
GA-RFNTG *162122313281268423491316159
MTRY *777161415222423
NS *322513911910511
SSD *35671512231623
MN *9999999990941009590
GA-XGBoostCB *0.96520.950190.948830.880560.855480.977950.833690.839640.95994
SS *0.737810.953130.95390.935090.936430.93740.98560.933920.9727
MD *91099991097
learning rate0.07920.09810.086080.088130.081830.095190.045560.077210.07101
gamma0.037030.440820.98670.267360.004730.999120.01180.006210.19647
MW *4.674953.02243.603893.511563.603873.885133.150735.408023.43816
Lambda *0.841431.02740.736090.625971.062270.666750.587331.234250.66977
ProductsWB_2L_T1WB_4L_T1WB_6L_T1
GA-LSSVRgamma487.8397461.7180253.7229260.8126138.0979291.6471264.8891386.9266261.5888
sigma2.10641.66393.57262.19261.67622.30012.06931.46924.8404
GA-BPNNlearning rate0.1958290.5581810.8971480.2707610.6526790.4052380.3011580.861550.105814
momentum0.8642130.658590.6947710.8947080.7658610.881960.3188450.6396950.634643
GA-RFNTG *338179356275435193492381255
MTRY *777141113222421
NS *211620332932848
SSD *75451165718
MN *97100999910098999685
GA-XGBoostCB *0.916550.887320.870730.983520.942730.827350.907110.816660.94269
SS *0.526060.702420.925290.660740.891150.913670.745130.906110.9466
MD *1081099101089
learning rate0.096890.066310.088150.095640.082110.087660.090080.096760.08981
gamma0.009290.029310.110650.016120.000160.17680.014590.010580.48457
MW *3.520745.638883.381814.186124.37463.626823.12843.441934.72415
Lambda *0.568061.174060.879220.788790.778850.522110.72321.139340.79814
* NTG: the number of trees to grow; MTRY: the number of variables used at each split; NS: the minimum size of terminal nodes; SSD: the sample sizes to draw; MN: the maximum number of terminal nodes trees in the forest can have; CB: subsample percentage of columns while generating new trees; SS: the subsample ration of training cases; MD: the maximum depth of the tree; MW: the minimum sum of weights related to child nodes; lambda: the L2 regularization term of weights.
Table 4. Levels of forecasting accuracy measured by MAPE [31].
Table 4. Levels of forecasting accuracy measured by MAPE [31].
MAPE Values (%)Accuracy
<10Highly accurate prediction
10–20Good prediction
20–50Reasonable prediction
>50Inaccurate prediction
Table 5. Forecasting results of different models in terms of MAPE, WAPE, and NMAE.
Table 5. Forecasting results of different models in terms of MAPE, WAPE, and NMAE.
Product TypeMethodLs (nH)Cs (pF)R (mΩ)
MAPE (%)WAPE (%)NMAEMAPE (%)WAPE (%)NMAEMAPE (%)WAPE (%)NMAE
FC_2L_T1GA-LSSVR16.8815.630.0481813.2513.470.056346.206.480.02528
GA-BPNN18.0317.550.0541013.9313.490.056427.486.720.02623
GA-RF18.6418.790.0579213.4313.440.056197.256.960.02712
GA-XGBoost19.0119.490.0600814.1214.020.058628.747.770.03029
FC_4L_T1GA-LSSVR12.188.920.016256.755.110.0152712.155.990.00845
GA-BPNN35.8622.670.041309.818.120.0242325.0514.350.02024
GA-RF12.309.610.017518.606.950.0207416.687.800.01100
GA-XGBoost15.1611.060.020157.546.010.0179617.857.870.01110
FC_6L_T1GA-LSSVR10.357.810.053839.097.420.0480411.998.330.04320
GA-BPNN10.378.740.060199.268.630.0558815.7712.870.06674
GA-RF10.408.560.058979.468.350.0540212.109.740.05053
GA-XGBoost10.879.150.063029.328.270.0535212.2310.450.05420
WB_2L_T1GA-LSSVR13.2812.630.055185.615.250.020187.216.790.02781
GA-BPNN15.2313.390.058526.646.000.0230711.409.710.03980
GA-RF13.8612.400.054176.105.860.022559.708.980.03680
GA-XGBoost13.4211.480.050156.626.070.023379.058.050.03298
WB_4L_T1GA-LSSVR14.5411.650.033016.715.840.0207410.007.100.02697
GA-BPNN16.0012.190.034539.197.530.0267613.199.200.03497
GA-RF14.9612.280.034809.167.790.0276710.598.080.03071
GA-XGBoost15.8111.740.033257.336.350.0225510.107.470.02840
WB_6L_T1GA-LSSVR8.689.280.058806.487.310.039044.084.890.03481
GA-BPNN9.959.210.058386.566.630.035414.364.630.03299
GA-RF10.139.920.062896.616.790.036247.398.180.05819
GA-XGBoost9.608.750.055466.606.730.035936.717.430.05285
AverageGA-LSSVR12.6510.990.044217.987.400.033278.606.600.02775
GA-BPNN17.5713.960.051179.238.400.0369612.879.580.03683
GA-RF13.3811.930.047718.898.190.0362410.628.290.03573
GA-XGBoost13.9811.940.047028.597.910.0353310.788.170.03497
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Lai, J.-P.; Lin, Y.-L.; Lin, H.-C.; Shih, C.-Y.; Wang, Y.-P.; Pai, P.-F. RLC Circuit Forecast in Analog IC Packaging and Testing by Machine Learning Techniques. Micromachines 2022, 13, 1305. https://doi.org/10.3390/mi13081305

AMA Style

Lai J-P, Lin Y-L, Lin H-C, Shih C-Y, Wang Y-P, Pai P-F. RLC Circuit Forecast in Analog IC Packaging and Testing by Machine Learning Techniques. Micromachines. 2022; 13(8):1305. https://doi.org/10.3390/mi13081305

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Lai, Jung-Pin, Ying-Lei Lin, Ho-Chuan Lin, Chih-Yuan Shih, Yu-Po Wang, and Ping-Feng Pai. 2022. "RLC Circuit Forecast in Analog IC Packaging and Testing by Machine Learning Techniques" Micromachines 13, no. 8: 1305. https://doi.org/10.3390/mi13081305

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