1. Introduction
Following current trends, such as the “Internet of Things” (IoT), “Industry 4.0”, and “Smart Everything”, the number of sensors to measure non-electrical quantities, such as pressure, temperature, distance, light or concentration of chemical substances, rapidly increases. For example, only the market for microsystems is expected to be 49 billion devices and 22 billion USD, respectively, worldwide by 2027 [
1].
Driven by wearable applications, the field of flexible electronics gradually became a very relevant topic in recent years. In particular, fully flexible electronics have the benefit of adaption to a surface when mounting on any complex 3D surface or the possibility of following the motions of a body.
Hence, flexible electronics are currently a key enabling technology for dynamic and flex-to-fit applications in today’s electronic devices. These systems can be used for monitoring the physiological parameters of a person, such as wearable sensors, or for any application that would cause strong stresses when mounting a rigid sensor to any 3D object [
2]. Furthermore, flexible electronics are beneficial for the structural health monitoring of lightweight structures due to their low mass and flexibility.
However, up until now, sensors and actuators are often realized by mechanical microelectromechanical systems (MEMS) using microfabrication technologies on rigid wafer substrates made of silicon, gallium arsenide, or other semiconducting materials. The same applies to microcontrollers based on CMOS technology [
3,
4,
5,
6]. Furthermore, the standard technology for the integration of sensors, actuators and microcontrollers into a circuit are rigid printed circuit boards (PCB) based on materials such as FR4. Rigid PCBs combine the advantage of low costs and easy maintenance with good reliability and, hence, are suitable for applications in harsh environments with high mechanical stresses and elevated temperatures [
7]. Even though they have a vast range of applications, both of the aforementioned technologies, i.e., the fabrication of sensors and MEMS on rigid wafer substrates as well as their integration on rigid PCBs, are not usable for applications that require thin and flexible substrates [
2].
When using flexible substrates, the typical materials are polymers, such as polyethylene terephthalate (PET), polyethylenenaphthalate (PEN), polyimide (PI), polycarbonate (PC), polyethersulphone (PES), polyacrylates (PAR), polycyclic olefin (PCO) and poly(para-xylylene) (Parylene). [
8,
9,
10,
11,
12,
13] In contrast to the other materials, Parylene can be particularly used to realize an ultra-thin and biocompatible flexible PCB with thicknesses of only 10 µm–20 µm. This includes multiple redistribution layers, which are fabricated by using established microsystem technologies and, hence, feature structure sizes as small as 10 µm [
11].
With respect to the integration of electrical components, some concepts are established for the direct fabrication of sensors on flexible substrates, e.g., pressure sensors and strain sensors. Usually, this type of sensor directly uses properties of the substrate itself as the strain sensor bases on the stretchability of the substrate or requires the usage of new materials [
14,
15,
16]. Printing technologies can be directly performed on flexible substrates for the realization of electrical interconnects and contacting chips and the fabrication of sensor structures themselves. Hence, by printing technologies, devices such as pressure sensors [
17], radio frequency identification tags (RFID) [
18,
19], solar cells [
20], light emitting diodes (LED) [
21], transistors [
22], passive microwave antennas [
23] and electrical chip interconnects [
24] can be realized. However, the variety of devices and the performance that this technology can realize are limited. Moreover, in general, the direct processing on flexible substrates is limited since the established substrate materials are neither compatible with the standard wafer-level processing using aggressive chemicals and high temperatures nor do the non-wafer-level methods for the direct processing on flexible substrates, such as additive manufacturing, offer a sufficient resolution for the fabrication of complex and highly integrated devices. Furthermore, most of the established standard packaging methods, such as soldering or bonding, can only be applied to flexible substrates, but with limitations due to inappropriate process conditions, particularly high temperatures. Particularly, the application of standard packaging and integration methods is not possible for the established ultra-thin Parylene flexible PCB [
11].
In order to combine the advantages of ultra-thin, flexible substrates and electronics with those of conventional micro technologies, a new approach for the fabrication of flexible electronics is the transfer of structures and components fabricated on rigid wafers using conventional technologies and a subsequent transfer to a flexible substrate. Kim et al. presented an interesting approach for the transfer of graphene from rigid to flexible substrates. Considering the high temperatures above 1000 °C needed for the fabrication of graphene, established materials for flexible substrates cannot be used for direct deposition. Hence, the authors deposited graphene on a copper substrate and deposited Parylene C layers of 15 µm and 25 µm, followed by peel-off, the electrochemical delamination of Parylene or the etching removal of the substrate. In doing so, the graphene was pulled off together with the Parylene and, thus, was transferred onto a flexible free-standing Parylene substrate. [
25] Similarly to this, Kim et al. demonstrated the transfer of inkjet-printed silver electrodes to Parylene using peel-off from a PDMS sacrificial layer [
26].
The requirement for the success of the peeling-off method is an insufficient adhesion of the material to be transferred to the rigid carrier substrate and good adhesion to the Parylene. In order to apply this method to multiple material systems and transferred structures of higher dimensions rather than a single atomic layer, we propose the usage of an additional sacrificial layer.
In this study, we investigate the adaption and extension of the described transfer process to transfer the metallic structures deposited by different technologies, as well as whole dies, electronic components and multiple materials systems, to an ultra-thin, flexible Parylene C substrate. Parylene C (Poly(2-chloro-p-xylylene)) is used due to its outstanding combination of excellent properties, which are as follows: a highly 3D conformal deposition from the gas phase and at room temperature, low Young’s modulus (flexibility), biostability and biocompatibility, optical transparency, chemical inertness, dielectric properties and low permeability for gases and moisture [
27,
28,
29].
The approach for the transfer process of structures from rigid substrates to flexible free-standing Parylene substrates used in this paper is depicted in
Figure 1. In doing so, different scenarios for the transfer of (a) metallic structures, (b) semiconductor dies, and (c) packaged electronic components are differentiated.
It is important to note the differences in the setup for the transfer of the dies and electronic components (
Figure 1b,c). Whereas the electrical contacts between the silicon die and the printed parts are covered and protected with Parylene in the final setup for (b), these contacts are accessible for the setup described for (c). The difference is schematically depicted in
Figure 2 with the related sections in this paper.
2. Materials and Methods
For all the experiments, 6″ silicon wafers or silicon chips, respectively, were used as rigid carrier substrates (
Figure 1 (1)). For the sacrificial layer, 80% hydrolyzed polyvinyl alcohol (PVA) was used, which was obtained from Sigma Aldrich. The PVA was spin-coated at 1500 rpm for 20 s in an aqueous solution of 4.7 w%, followed by subsequent drying at 105 °C for 5 min in air (2). The PVA was chosen as a sacrificial layer since it can be dissolved by water, and thus, a completely solvent-free process can be realized. After the deposition of the sacrificial layer, the structure to be transferred is deposited (3) to (5), whereas different scenarios were tested, including (a) the transfer of metals only, (b) the transfer of semiconductor dies with subsequent metallization, and (c) the transfer of packaged electronic components with previous metallization, respectively. Subsequent to this, 15 µm of Parylene C was deposited by chemical vapor deposition (CVD) using the Gorham process, as depicted in
Figure 3, and a Plasma Parylene LC 300 RW from Plasma Parylene Systems GmbH (PPS), Germany (6). In doing so, in the first step, 30 g of a solid dimer was sublimed at 130 °C, followed by pyrolysis at 740 °C, and hence, thermal cracking into monomers. In the final step, the linear polymer chains were formed at 40 °C. The setup was completed by a cool trap at −80 °C and a vacuum pump [
27,
28,
29].
For lift-off, a scalpel was used to cut the Parylene film at the edge and provide access for the water. Afterwards, the substrate was placed in DI water at room temperature overnight to dissolve the PVA and release the Parylene, including the transferred structures (7).
2.1. Transfer of Metallic Structures
For the transfer of metallic structures, different metals and deposition methods were investigated following the general process flow depicted in column (a) of
Figure 1. For all metallic structures, the meander design given in
Figure 4, with a total length (l) of ~11 cm, was used. The line width (w) was varied between 100 µm and 250 µm. For the investigation of the transferability of larger area structures, a metallic pad of 2 mm × 2 mm was realized on each end of the meander. In order to verify the function of the structures after the transfer, these pads were connected, and electrical measurements were performed.
The metallic structures were realized by the maskless direct deposition of nanoparticle silver inks using aerosol jet printing (AJ300 system of Optomec Inc., USA) and subsequent sintering post-treatment. In order to compare the influence of the material and ink composition on the transfer results, two silver nanoparticle inks were used: Bando SW1020 on the water base and GenesInk S-CS31506 on the solvent base. Both inks are based on silver nanoparticles and were used as received. The printing settings for printing with the Bando Ink were 800 sccm for the atomizer, 750 sccm for the exhaust, and 60 sccm for the sheath gas. The substrate temperature was maintained at 80 °C, and the printing speed was kept constant at 8 mm/s. When printing with GenesInk, the atomizer, exhaust and sheath gas flows were set at 950 sccm, 925 sccm and 60 sccm, respectively, whereas the printing speed was 5 mm/s. The sintering condition was 120 °C in air for 2 h for both inks. In order to investigate the influence of the height of the structure to be transferred, a second group of meanders was printed twice.
Alternatively to the printing, the metal structures were realized by sputtering. For this, shadow masks with the same design given in
Figure 4 were fabricated by laser ablation in sheets of stainless steel. The line width in the shadow masks varied between 75 µm and 100 µm. Gold and platinum were sputtered on PVA-coated silicon chips using a desktop sputter tool (BalTec SCD 050 Sputter Coater). The sputtering was performed at a pressure of 0.04 mbar and a current of 60 mA. In order to vary the thickness of the sputtered structures, the two metals were deposited with different sputtering times of 400 s and 750 s each. After sputtering, the Parylene was deposited, followed by a subsequent lift-off.
The thickness of all the metallic structures was measured before the deposition of Parylene C using a KLA Tencor Alpha-Step 500 Surface Profilometer and averaged over three different measurement positions. After the deposition of Parylene C, the lift-off of the structures was performed, and the electrical resistance (R) was measured to compare its values before the lift-off. In order to prove the success of the transfer process, the electrical resistance of each metallic structure, as well as of the transferred chips, was measured before and after the transfer process using a PeakTech 2010DMM multimeter. Afterwards, the electrical conductivity (σ) was calculated by the following equation, considering the height (h) and width (w) of the metallic structures as well as their total length (l) of 11 cm.
Additionally, the samples were bent on some cylindrical test specimens with different diameters (d). The used diameters are given in
Table 1, as well as the strains (ε), which are introduced by the bending test. For the calculation of the strain, the following equation was used, assuming a sample thickness (t) of 15 µm.
During the bending test, the samples were observed concerning delamination for diameters of ≥1 cm, and their electrical resistance was measured to calculate the electrical conductivity, as described above.
2.2. Transfer of Dies
In order to investigate the integration of whole dies and chips, respectively, the process flow depicted in column (b) of
Figure 1 was followed. Semiconductor dies were thinned to achieve some flexibility using the BrewerBond
® process described elsewhere [
30]. It can be briefly summarized as follows: spin coating of an adhesive on a carrier wafer as well as the wafer to be thinned, followed by subsequent temporary bonding and wafer thinning by grinding and chemical mechanical polishing. Afterwards, the temporarily bonded wafer compound is attached to a dicing frame, and the carrier wafer is mechanically debonded, followed by dicing. Additionally, these chips were metallized before positioning the carrier substrate by sputtering gold and platinum for 750 s and 1000 s using the same tool and parameters as mentioned earlier. Both metals were selected due to their different adhesion on silicon: gold adheres poorly to silicon without any additional adhesion-promoting layer, whereas platinum adheres well. The thinned and metallized 5 mm × 5 mm silicon chips of 60 µm thickness were positioned on the PVA by pick-and-place. In order to achieve good sticking, the chips were positioned while the PVA was still liquid. It is important to note that the metallized and, thus, conductive side of the chip was covered by Parylene after the transfer (
Figure 2, left setup). Hence, gaining direct access to enable electrical contacting is not possible.
For transferring the devices with top-side contacts that are covered and protected by Parylene after the transfer process, it is important to investigate how the external access can be realized for the electrical contacts without patterning and opening the Parylene itself, respectively. For this reason, conductive paths were printed on the metallized side of the chip, and the contact pads were printed on the PVA as well as the connection of these contact paths with the contact pads. For the printing, the aerosol jet and GenesInk S-CS31506 were used again, with the parameters described in
Section 2.1. Since the conductive path between the contacts on the chip and the pads on the PVA has to bridge the step induced by the chip thickness, all structures were printed twice. After printing the contact pads, Parylene deposition and lift-off were performed as described in
Section 2.1.
2.3. Transfer of Electrical Components
In addition to the transfer of silicon dies, the transferability of electronic components is also of practical relevance (see column (c) in
Figure 1 as well as
Figure 2). Hence, bulky packaged LEDs of 2.0 mm × 2.0 mm × 1.4 mm width, length and depth, which are usually designed for surface mounting (SMD), were used to investigate the transferability. The LEDs are obtained from CML innovative Technologies (CMD28-21 Series SMT LEDs) and have a red color, a maximum forward voltage of 2.8 V and a current of 20 mA.
For the sample preparation, two contact pads and two electrical connectors were printed on the PVA using the aerosol jet and the GenesInk S-CS31506 again, as described in
Section 2.1. Afterwards, the LED was glued onto the printed electrodes using conductive glue LOCTITE ABLESTIK ICP 4015, which is a silver and silicone-based glue. The glue was cured in accordance with the datasheet at 80 °C for 30 min in air. After this, the Parylene deposition and lift-off were performed. In order to prove the successful transfer of the LED, it was tested as to whether it was still glowing after the transfer when applying a forward voltage using a Statron power supply, type 3225.
2.4. Transfer Mechanism
For a better understanding of the transfer mechanism, the adhesion of the metallic structures was tested in several ways. First, all flexible metallic structures were tested by a tape test in similarity to ASTM D3359. In doing so, the samples were glued with their back side (the side without any metallic structures) to silicon wafers with double-sided adhesive tape (TESA 4965). In the next step, another adhesive tape (TESA 4289) was attached to the front side and slowly peeled off again after a waiting time of 1 min. Afterwards, the samples were inspected. The adhesive tapes used for the test were selected to use the tape with stronger adhesion (11.8 N/cm on stainless steel) for the fixation of the sample on the silicon and the one with less adhesion (5.5 N/cm on stainless steel) for the peel-off. For reference, the described tape test was also performed for all metals, which were deposited directly on Parylene. In order to quantify the adhesion strength of the transferred metal on Parylene, pads with a size of 1 cm × 1 cm were printed using the described aerosol jet technology and Genesink S-CS31506 and transferred onto Parylene. For comparison, the Parylene was metallized directly with the same technology. Both samples were metallized with 12 pads, lifted, and the pads were cut using regular scissors. Next, two stainless steel studs with a contact area of 5 mm × 5 mm were glued onto the metallic pad and Parylene, respectively, using Pattex “Sekundenkleber” (liquid cyanoacrylate glue). The glue was dried overnight in ambient conditions. For the measurement of the tensile strength, a TIRA Test 2805 was used with a force sensor (serial number 63026, K series) with a nominal load of 1 kN and a sensitivity of 2 mV/V. Within the tensile test, the pulling force was measured based on time and displacement, and the pull force was derived from its peak value (
Figure A1 in
Appendix A). In doing so, a testing speed of 3 µm/s and a pre-force of 5 N were applied. The two surfaces of the ruptured sample on the studs were analyzed in the light microscope (Eclipse L200, Nikon Corporation, Japan) to determine the rupture area and calculate the adhesion strength of the metal to the Parylene. Finally, this experiment was repeated using the same equipment and procedure but an additional high-speed video capture of the rupture event.
As indicated in
Figure 1 (7) and
Figure A2 in
Appendix B, respectively, in contrast to the conventionally metallized Parylene samples, the transferred structures were embedded into the Parylene and had interfaces on three sides, i.e., on the top side and the edges. In order to analyze whether the additional interfaces of Parylene with the transferred structures influence the adhesion compared to Parylene, which was metallized directly, a sample was prepared in which the transferred metal structure features only one interface with Parylene. The process is described in detail in
Appendix B. Afterwards, the described tape test was performed on the obtained metallized Parylene. For a detailed analysis of the interfaces between the transferred structures and Parylene, the samples were embedded into epoxy (EpoFix Harz and a related hardener by Struers GmbH, Germany), outgassed in vacuum and hardened for 24 h. Subsequently, a cross-section was made using silicon carbide-based abrasive paper, as well as MD-Dur and MD-Nap polishing wheels with a DiaPro diamond suspension (3 µm and 0.25 µm, respectively). After fabrication, these cross-sections were analyzed by light microscopy.
Finally, the roughness of the metallic structures was investigated before and after the transfer process. In doing so, the roughness of the conductive path was measured using confocal microscopy (confovis GmbH, Germany) after steps (3) and (6) of the process depicted in
Figure 1a and on the accessible metal side. Since the aerosol jet-printed structures (GenesInk S-CS31506) feature the highest roughness, this metallization method was selected for this investigation.
4. Discussion
The results successfully demonstrate the feasibility of the transfer of metallic structures, dies, and components as well as whole setups of dies or components with metallic conductive paths from rigid substrates to flexible Parylene substrates.
Aside from the novelty of the method for the integration itself, this transfer technology overcomes the limitations of ultra-thin, flexible and temperature-sensitive materials that impede the usage of established integration technologies, such as wire bonding, soldering or printing, and dispensing, respectively. Hence, it closes an open research gap for the integration of dies and components on flexible substrates, such as the ultra-thin flexible Parylene PCB [
11]. Additionally, the described new transfer process can be an alternative to fan-out wafer packaging [
31].
Moreover, the investigated transfer technology enables the merger of conventional wafer processing by microsystem technologies and packaging technologies. By doing so, smaller structure sizes can be realized on flexible substrates, and hence, the next level of miniaturization is enabled. The improved integration of dies, chips and discrete components also enables a smoother fabrication with fewer fabrication steps, particularly considering that the Parylene substrate can also act as an encapsulation and barrier layer. Hence, the presented transfer technology helps to reduce energy consumption and save resources. In summary, the transfer technology enables a unique combination of the advantages of different microsystem technologies and packaging technologies to realize the next generation of ultra-thin flexible electronics.
Considering the fact that the Parylene coating and sacrificial layer release are the last process steps in the presented technology flow, particularly, fabrication and integration processes with an increased thermal budget are avoided. Hence, the alteration of the Parylene properties is prevented as well [
32].
Finally, the described transfer process can be used to increase the adhesion of metallic structures on Parylene as well as to fabricate flexible metallic surfaces of high smoothness in similarity to template-stripped metals described elsewhere [
33]. This relates particularly to printed structures, which usually feature a high roughness due to their sinter structure and can be advantageous for improving the electrical contact resistances.
Hence, the presented technology is an advantageous tool for multiple applications.
5. Conclusions
A new and efficient process was established for the transfer of sputtered and printed metallic structures to a flexible substrate. The successful transfer was demonstrated for a variety of geometries, thicknesses, metals and metallization technologies. The transferred structures were found to be bendable until a minimal bending diameter of 0.5 cm without any damage and with a reversible change in the electrical resistance, independent of the metal and applied metallization technology. The adhesion of the transferred structures to the Parylene was proven to be excellent and better than for the direct metallization. Finally, cross-sectional images and an investigation of the roughness of the transferred structures reveal more details of the performance of the new process.
Furthermore, the transfer of thinned silicon dies and packaged electrical components was demonstrated successfully using the established process. In doing so, all electrical contacts of the chips are transferred as well.
Thus, the presented technology closes a gap between the established micro technologies on rigid substrates, such as wafers, and processing on flexible substrates. Hence, the demonstrated technology provides a new and fundamental, paradigm-changing opportunity for the fabrication of flexible electronics by combining the established microsystem technologies, additive manufacturing, pick-and-place, and conventional packaging technologies.
Additionally, the presented transfer technology can be used to integrate components on the ultra-thin, flexible Parylene PCB [
11]. Particularly, this new method overcomes the limitations that conventional packaging technologies, such as wire bonding, soldering or direct printing, feature on ultra-thin, flexible and temperature-sensitive substrates.