1. Introduction
As market demand evolves, the future development of power modules (PMs) must not only meet system specifications, but also achieve high efficiency, high switching frequency, and high reliability under high operating temperature [
1]. Many PM-related applications, on the one hand, have space constraints (e.g., aircraft, EVs, unmanned vehicles, robotic arms), and on the other hand, require high power and high frequency (e.g., DC–DC converters, AC–DC–AC variable frequency drives (VFD), uninterruptible power supplies). This would likely lead to a high-power density and excessive temperatures, which may successively cause higher power loss, eventually going into thermal runaway and reliability issues [
2]. It is evident that high power density PMs face many challenges, such as the specifications of the system requirements for high power applications, the selection of power semiconductor devices (PSDs), low inductance circuit designs, system layout designs, thermal management, and even reliability. The performance and specification requirements for PMs and PSDs differ among various applications [
3]. With the advancement of material and process technologies, the use of wide bandgap (WBG) SiC and gallium nitride (GaN) as semiconductor materials for high-power and high-frequency transistors has become common practice because of their many benefits over conventional Si materials, such as lower power loss, higher breakdown voltages, higher operating electric fields, higher operating temperatures, and higher switching frequencies [
4,
5,
6,
7,
8,
9]. Under high voltage and high temperature operating conditions, it was found [
8] that the performance of SiC PSDs is far superior to that of Si PSD. In addition, WBG materials can improve efficiency, reduce size and weight, and lower system costs [
10].
SiC devices possess high current rates and therefore faster switching capabilities, compared with Si ones, making them more sensitive to module encapsulation, parasitic parameters, and gate drive parameters. For instance, large voltage spikes occur during switching transients due to short pulses with a high current rate when the switching frequency is high. In addition, parasitic inductance will resonate with the parasitic capacitance, resulting in increased electromagnetic interference (EMI) and disturbance ringing [
11]. Moreover, parasitic inductance may bring about significant overshoots and ringing in the current and voltage waveforms, which would, in turn, result in increased EMI. In this respect, PSDs demand a higher voltage rating than what is needed. Consequently, the parasitic inductances in both the power and gate circuits must be minimized to suppress the induced overvoltage and overcurrent. To alleviate these issues, an RC snubber circuit [
12,
13], the increased gate resistance (R
g) of the gate control circuit [
14], or even reduced parasitic inductance via electromagnetic suppression/cancellation [
15] can be an effective means. However, there is a tradeoff in the former two approaches, as both can lead to additional power loss and reduced efficiency, which would counter the purpose of using the expensive SiC PSDs. By contrast, electromagnetic cancellation via the layout design of PMs could be a more effective way to reduce parasitic inductance, where three-dimensional [
15,
16,
17,
18,
19] and planar [
12] architectures have been proposed as effective solutions for reducing parasitic inductance and even enhancing thermal performance. For instance, it was revealed [
18] that magnetic field cancellation between two terminals, as a result of the P-N terminal overlap arrangement in the unique structure of a 3D-stacked module, can lead to an exceptional decrease in parasitic inductance. Moreover, incorporating the PSDs into the power circuits in such a way that unwanted parasitic inductances can be removed is a feasible alternative for achieving low parasitic inductance. Using this approach, Chen et al. [
19] proposed a SiC-based, half-bridge module with a hybrid packaging method based on the incorporation of the printed circuit board (PCB) and the direct bonded copper (DBC) structure. This structure allows the minimization of the parasitic inductances through the optimization of current communication loops, driver locations, and gating connections. Furthermore, Raab et al. [
12] developed a high efficiency, fast-switching, and reliable full-SiC PM based on a novel planar packaging technology for More Electrical Aircraft (MEA) applications through the integration of snubber capacitors, gate drivers, and online temperature measurement solutions for health-monitoring. Additionally, two isolated gate driver ICs were employed to assure decreased and symmetric gate loop inductances, further facilitating symmetric current sharing during the switching transients.
IC substrates and cooling systems are the primary heat dissipation passages of PMs. A proper selection of substrate materials and the use of effective cooling systems are critical to the device’s thermal performance and even thermal–mechanical reliability. DBC alumina (Al
2O
3 and AlN) ceramic substrates have been widely used in various power electronics applications due to technology maturity, good thermal and mechanical performances, and even low production costs, especially the Al
2O
3 DBCs. As a result of a lack of an oxide layer for copper (Cu) bonding, the production cost for the AlN DBCs is markedly higher than that of the Al
2O
3 ones because of the greater manufacturing difficulty and lower yield despite having superior thermal performance. Moreover, these insulators are brittle in nature and thus vulnerable to stress cracking [
20,
21]. It is worth noting that a thicker insulator causes not only higher electrical insulation but also greater thermal resistance, which is not ideal for high power applications. To address these challenges, several different types of substrates were proposed, including insulated metal substrates (IMS), Si
3N
4, direct plate copper (DPC), etc. Among them, IMS is an attractive alternative as a result of its low cost in manufacturing, the good mechanical property of the insulation layer, great efficiency in layout usage, and even superior thermal and electrical performances [
21,
22]. Their thermal performance can be upgraded through the use of a thinner dielectric layer though this may unfortunately lead to a lower electrical resistance [
23]. It was reported that a Cu- and Al-based IMS substrate with an insulating layer (IL) thickness of 0.12 mm outperforms an Al
2O
3 DBC substrate with an IL thickness of 0.38 mm in thermal performance [
22].
The power loss generated by the internal PSDs of PMs during operation can induce a significant temperature rise, ultimately affecting their performance and reliability. An accurate estimation of their power loss and efficiency during operation is a crucial issue in the development of PMs. In general, the switching loss of PMs tends to increase with the switching frequency, and in addition, temperature would play a significant role in the power loss, especially the conduction loss [
24], which may further trigger thermal runaway. During the past years, there have been many reports on switching loss evaluation through theoretical analysis and experimental characterization [
14,
24,
25,
26]. For example, Xiong et al. [
25] introduced a physically based semiconductor device modeling method to examine the switching loss of a power MOSFET device, and in accordance with the new physical insights, to evaluate the widely used switching loss estimation approach. Qi et al. [
26] found that the switching loss of the Si MOSFET and IGBT devices is positively proportional to temperature, while it is the opposite for the SiC MOSFET. Cheng et al. [
14] conducted numerical analysis and experimental measurements to investigate the switching transients and power loss of an SOT-227 packaged Si MOSFET PM and the associated three-phase power MOSFET inverter during load cycles. To effectively evaluate the PM electrical behavior and even power loss, Dutta [
27] applied an electromagnetic-circuit co-simulation (ECC) approach to analyze the switching response of a three-dimensional stacked wire bondless IGBT power module under various system configurations. Lin et al. [
28] investigated the conducted EMI issue on an AC–DC switching power adaptor with a flyback converter topology through ECC.
Although there have been some studies on the parasitic inductance, switching waveforms, and system operation and performance of SiC PMs over the past years, there is still limited development of a comprehensive systematic exploration of Si/SiC integrated hybrid PMs (iHPMs) from PM design to system operation. This study attempts to develop a 30 kHz/12 kW SiC/Si iHPM (
Figure 1) for industrial servo motor drives. This iHPM integrates three functions—a brake circuit, a three-phase Si rectifier, and a three-phase SiC inverter within a single package to achieve a minimized current path. An insulated metal substrate (IMS), rather than a DBC substrate, is used to provide structural support to these power devices and components, and to facilitate electrical isolation and thermal transfer from the device to a base plate, a heatsink, and even a cooling system. A special focus of this PM development is placed on the inductance cancellation design in the rectifier and inverter circuit in order to accomplish a reduced parasitic inductance. To control the output voltage of the three-phase inverter, a space-vector pulse width modulation (SVPWM) technique is implemented. The switching characteristics, dynamic behavior, and performance of the iHPM during the three-phase switching operation are characterized experimentally and theoretically. Moreover, in order to demonstrate the performance advantage of the SiC MOSFET inverter system in terms of system power loss and efficiency, the Si IGBT inverter system inside a commercial integrated PM (iPM) is experimentally analyzed.
2. Development of Sic/Si Integrated Hybrid Power Module
Power conversion system designs, such as inverters and converters, for small AC motors in industrial applications face increasing needs and also challenges in meeting stringent specification requirements for reliability, size, cost, and energy efficiency. Traditionally, various power conversion designs are fulfilled using discrete power semiconductor packages [
29]. Although they have several advantages, such as reduced cost, great flexibility in choice of PSDs, low power, and a simple topology, these packaging approaches would require a relatively much larger and more intricate PCB design to satisfy the constraints of spacing and layout of these discrete power packages and active and passive components. This problem can be properly addressed using an integrated packaging solution, allowing for a reduction in stock holding and handling costs and assembly effort, in comparison with the discrete one.
The prototype of the proposed iHPM is illustrated in
Figure 1a, and its electrical layout is presented in
Figure 1b, which incorporates three major components, namely a brake circuit, a three-phase rectifier, and a three-phase inverter. For minimized switching loss and increased power conversion effectiveness, twelve SiC power MOSFET devices with SiC body diodes are implemented in the inverter. Furthermore, for cost efficiency, the three-phase rectifier is made up of six Si diodes connected in series and in parallel. These power components are mounted onto an electrically isolated IMS. In addition, this power conversion system is connected to an external AC power supply and a servo motor. Specifically, this iHPM utilizes an AC energy source, rectifies it to a stable DC voltage, converts the DC into three-phase AC through an SVPWM control scheme, and then feeds it into an induction motor based on the demands of load torque and speed. In this AC motor drive system, the three-phase voltage source SiC inverter is the core component in the power module for regulating the voltage level and voltage frequency for load speed control. The output power requirement for the iHPM is 12 kW. It is noted that a gate driver is employed to drive the gate voltage of these power switches of the SiC inverter. Considering the size limits, the gate control unit is not packaged in the iHPM. The design considerations for the three-phase SiC inverter are briefly described in the following. Two parallel-connected SiC power MOSFET devices per switch are used to upgrade the current rating. The output, transfer, and body diode characteristics, measured using a curve analyzer, are reported in
Figure 2, and the diode characteristics of the rectifier diodes are depicted in
Figure 3. For safety, the module design includes a brake circuit between the three-phase Si rectifier and SiC inverter. The brake circuit implements an Si IGBT device to control the brake and an Si diode to discharge the energy using the external resistor. It is noted that the resistor for energy discharge is not included in this power module. The SiC MOSFETs rated at 1200 V and 149 A at 100 °C, produced by Wolfspeed, and the Si diodes rated at 1800 V and 100 A, manufactured by YENYO technology, are implemented. The maximum junction temperature rating of the power chips is 175 °C.
A substrate is a crucial part of and a determining factor in a power module, that highly affects its electrical, thermal, and mechanical performance. In contrast to the double-sided DBC substrate, IMS is a single-sided substrate, suggesting that only one side (i.e., the Cu side) can be installed with electronic components. IMSs have been extensively reported in the literature on power electronics applications [
21,
22,
30,
31,
32]. According to the literature data, the thermal performance of an IMS is believed to be typically inferior to AlN DBC substrates mainly due to the low thermal conductivity of their dielectric layer. However, in addition to simplifying the manufacturing process and enabling the feasibility of multi-stacked layers, this technology also allows thermal and electrical isolation performance enhancements through the optimization of the material, the number of layers, and the thickness of the conductive and dielectric layers. For example, the thermal performance of IMS can be upgraded by using a thinner high thermal conductivity thermal interface material (TIM). According to the vendor’s datasheet, the TIM with a thickness of 100 μm possesses a breakdown voltage greater than 6 kV, thereby having the potential to achieve good electrical insulation or prevent current leakage between the conductive layers. In this work, for a better compromise between cost and performances [
21], an advanced IMS that applies a polymer-based material as an electrical insulator is employed. This IMS, as reported in
Figure 4a, is made up of a 3 mm thick metal Cu baseplate covered by a thin epoxy-based layer of 0.01 mm thickness as a dielectric and a 0.3 mm thick Cu trace layer. During the three-phase switching operation, the IMS is further attached using thermal grease to an Al heatsink with a cooling fan for fast heat dissipation. These twelve power MOSFET devices are mounted on the top Cu islands of the IMS using a SAC305 solder, and then connected via 10 Al bond wires to establish a three-phase bridge power module. In order to protect these bond wires from fusing, the bond wire number is determined based on the maximum loading current. It is worthwhile mentioning that there needs to be a connection wire for facilitating an electrical conduction from the gate pin to the gate pad of the power chip, and from the sense pin to the source side.
Package parasitic inductances can be extensively minimized via a cancellation design by virtue of a proper module layout (substrate pattern) and pin assignment designs.
Figure 4b displays the Cu trace layout and pin assignment designs. Noticeably, there are AC input pins (R, S, T) and DC output pins for the three-phase Si rectifier, DC input pins (P, N), and AC output pins (U, V, W) for the three-phase inverter, and an output pin between the IGBT and the diode for external wiring to the resistor for the brake circuit. Moreover, the gate control also needs one control pin and one sense pin for all these inverter power switches, and also one control pin for the Si IGBT device of the brake circuit. The pin assignment must follow the control board design, and also needs to comply with isolation protection standards, such as those set by the International Electrotechnical Commission (IEC), to prevent short circuits caused by differences in high potential. In this study, the pin assignment design is shown in
Figure 4b, which matches the design of a state-of-the-art commercial Si IGBT integrated PM. As shown in this figure, the DC input pins, i.e., P and N, and also the DC output pins, i.e., DC+ and DC−, are designed adjacent to each other as much as possible to ensure that the positive and negative current paths in the substrate can be interleaved to reduce the parasitic effects, in accordance with the design rule for inductance cancellation. In this power module, the high side (hereinafter referred to as the “HS”) is near the output pin, and the lower side (hereinafter referred to as the “LS”) is near the DC input pin. The same design logic, in terms of pin assignment and Cu circuit layout, is also applied to the three-phase Si rectifier. The gap between the top Cu islands is about 1 mm. Because the top side of the power module is filled with a molding compound, the 1 mm gap width is sufficient to keep them electrically isolated from each other. The dimension of the proposed 1200 V/200 A SiC/Si iHPM is listed in
Table 1.
Figure 5 demonstrates the schematic diagram of a cross-sectional view of a portion of the iHPM structure near the SiC inverter.