A Novel 6500 V SiC Trench MOSFET with Integrated Unipolar Diode for Improved Third Quadrant and Switching Characteristics

Abstract

A 6500 V SiC trench MOSFET with integrated unipolar diode (UD-MOS) is proposed to improve reverse conduction characteristics, suppress bipolar degradation, and reduce switching loss. An N type base region under the trench dummy gate provides a low barrier path to suppress hole injection during the reverse conduction operation. The reverse conduction voltage V_ON is reduced to 1.11 V, and the reverse recovery charge (Q_RR) is reduced to 1.22 μC/cm². The gate-to-drain capacitance (C_GD) and gate-to-source capacitance (C_GS) of the UD-MOS are also reduced to improve switching loss due to the thick oxide layer between the trench gate and dummy gate. The proposed device exhibits an excellent loss-related figure of merit (FOM). It provides a high-voltage SiC MOSFET prototype with potential performance advantages for voltage source converter-based high voltage direct current applications.

1. Introduction

The voltage source converter-based high-voltage direct current (VSC-HVDC) transmission with high flexibility and controllability is a key approach to the construction of a high-proportion clean energy grid. The high-voltage (6500 V and above) SiC MOSFET is a promising candidate for VSC-HVDC transmission to increase power efficiency and reduce the volume of the system [1,2,3]. In the VSC, the freewheeling diode of SiC MOSFET operates during the dead time period. However, the utilization of the integrated PN body diode causes potential issues. Firstly, the reverse recovery charge Q_RR and reverse conduction voltage V_ON considerably increase loss. Secondly, the basic plane dislocations (BPDs) generate stacking faults (SFs) in the drift region by absorbing the energy from charge recombination [4], which degrades the V_ON and leakage current of SiC MOSFET [5]. For the 6500 V SiC MOSFET with a thicker drift region, many more SFs could be generated based on same initial BPDs density, spelling more serious bipolar degradation issues [6].

To prevent SiC MOSFET bipolar degradation issues, a common solution is utilizing the externally antiparallel Schottky barrier diode (SBD) for freewheeling operation [7], but this increases the parasitic parameters and size of the MOSFETs-based power module [8]. However, for the monolithic integrated diode schemes, SBD-integrated MOSFETs have been reported [9,10,11] and the source-controlled channel-diode-embedded SiC MOSFETs have been demonstrated [12,13], whereas Schottky contact and the uneven gate oxide layer-related reliability issues have yet to be introduced [14,15,16,17]. Gate-controlled channel-diode-embedded SiC MOSFETs have also been fabricated [18,19,20], which allow the forward and reverse conduction currents to share the same MOS-channel path. However, this brings a huge challenge to achieving a better trade-off between low reverse conduction voltage and reasonable threshold voltage [18].

In this paper, a 6500 V SiC trench MOSFET with integrated unipolar diode (UD-MOS) is proposed to improve reverse conduction characteristics, suppress bipolar degradation issue, and reduce switching loss. Compared with the asymmetric trench MOSFET (C-MOS), the performance with its operation mechanism of UD-MOS is demonstrated by numerical simulations, involving doping-dependent mobility, high-field saturation mobility, Shockley–Read–Hall (SRH) recombination, Auger recombination, incomplete ionization of impurities, and impact ionization models.

2. Device Structure and Mechanism

The schematic cross-section view of the 6500 V SiC C-MOS and UD-MOS is shown in Figure 1. Compared with the C-MOS, the polysilicon gate of UD-MOS splits into two parts with a thick oxide layer. The left one is the true gate electrically connected to the gate electrode, while the right one is the dummy gate electrically connected to the source electrode. An N type region (i.e., N base region) beneath the dummy gate for electrons from the CSL region to N+ region, forms a unipolar diode (UD) as illustrated in Figure 1b.

For the zero-bias condition, the potential barrier distribution of the integrated unipolar diode of UD-MOS is shown in Figure 2. Compared with the body diode of C-MOS, the decrease of potential barrier from the P+ region to the SiC/SiO₂ interface (i.e., along line A′-A of Figure 1) makes a relatively low potential barrier (i.e., V_UD) for electrons transported from the CSL to N+ region. It should be noted that the V_UD is still relatively higher than the potential barrier of the CSL region and the N+ region as shown in Figure 2d. In other words, the electrons cannot flow through the N base region to the N+ region under this condition.

When in blocking condition, although the increasing V_DS lowers the barrier of the CSL region and N base region due to the drain-induced barrier lowering effect, the V_UD is still high enough to ensure blocking capability, as shown in Figure 3a. When in the reverse conduction condition, the potential barrier of the CSL region is raised by the negative V_DS. Once the potential barrier of the CSL region exceeds V_UD, the electrons from the CSL region can flow through the N base region to the N+ region, as shown in Figure 3b. Therefore, the potential height of the N base region determines both the blocking and reverse conduction characteristics of UD-MOS. Furthermore, a barrier height analysis model is given here to inform the design of the V_UD as follows,

$$V_{\mathrm{UD}}=V_{\mathrm{P}}-\frac{{\varphi }_{\mathrm{Si},\mathrm{SiC}}+V_{\mathrm{GS}}-\frac{q{N}_{\mathrm{CH}}{t}_{\mathrm{CH}}^2}{2{\epsilon }_{\mathrm{SiC}}}}{\frac{{\epsilon }_{\mathrm{SiC}}{t}_{\mathrm{ox}}}{{\epsilon }_{\mathrm{ox}}{t}_{\mathrm{nch}}}+1}-\frac{q{N}_{\mathrm{CH}}{t}_{\mathrm{CH}}^2}{2{\epsilon }_{\mathrm{SiC}}}$$

(1)

where V_P is the potential barrier height of P+ region, ϕ_Si,SiC is the work function difference between N-type polysilicon and the P+ region, ε_SiC is the dielectric constant of SiC, ε_ox is the dielectric constant of oxide, q is the elementary charge, t_CH is the thickness of the N base region, and N_CH is the doping concentration of the N base region, respectively. According to (1), even though the negative V_GS can enhance blocking capability by increasing the V_UD, it also results in a high reverse conduction voltage V_ON of UD-MOS. Moreover, the positive V_GS even reduces the V_UD to make the unipolar diode turn on, causing the UD-MOS to lose gate control when in the forward conduction condition [17]. Therefore, the dummy gate not controlled by the gate electrode is introduced to guarantee both the forward and reverse conduction capability. Furthermore, the thickness t_CH and doping concentration N_CH of the N base region also affect the V_UD. With the increase of t_CH and N_CH, the V_UD decreases, as shown in Figure 4. The influence of breakdown voltage (BV) and V_ON on t_CH and N_CH is discussed further in the following section.

3. Results and Discussion

With the increase of t_CH and N_CH, the V_ON (@V_GS = 0 V, I_DS = −3 A/cm²) and BV (@I_DS = 1 × 10⁻⁸ A/cm²) of UD-MOS decrease, as shown in Figure 5. It should be noted that the V_ON is mainly the voltage drop of the UD (i.e., V_UD) and the thick epi-layer. The thicker t_CH and higher N_CH bring lower V_ON, but also lead to premature breakdown. Therefore, considering both the V_ON and BV of the UD-MOS, the t_CH and N_CH are designed to be 170 nm and 8 × 10¹⁶ cm⁻³, respectively. The key structural parameters of the C-MOS and UD-MOS are shown in

Table 1. Key Structure Parameters of the SiC C-MOS and UD-MOS.

Parameters	UD-MOS	C-MOS
cell pitch (μm)	3.35	3.15
drift region thickness (μm)	60	60
drift region doping (cm−3)	1.2 × 1015	1.2 × 1015
polysilicon width (μm)	0.8	0.8
trench depth (μm)	0.9	0.9
trench width (μm)	1.1	0.9
oxide thickness (nm)	50	50
CSL doping (cm−3)	3 × 1016	3 × 1016
JFET width (μm)	1.3	1.3
P+ region thickness (μm)	1.7	1.7
P+ region doping (cm−3)	1 × 1019	1 × 1019
N base length (μm)	0.35	−
N base thickness (nm)	170	−
N base doping (cm−3)	8 × 1016	−

.

The effect of the N base length L_CH on V_UD is also discussed. With the narrowness of L_CH, the potential of the N+ region influences the potential barrier of the N base as shown in Figure 6a. Although the lower V_UD helps to reduce the V_ON, the BV is weakened at the same time, as shown in Figure 6b.

3.1. Static Characteristics

Based on optimized t_CH and N_CH, the SiC C-MOS and UD-MOS have a similar BV, as shown in Figure 7. The peak electric field in the gate oxide is less than 3 MV/cm, which ensures the long-term reliability of the gate oxide, as shown in the insets of Figure 7.

Moreover, the V_ON of UD-MOS is −1.1 V, while the C-MOS is −2.8 V, as shown in Figure 8a. It should be noted that the integrated unipolar diode makes for lesser hole injection into the drift region when in the reverse conduction condition, as shown in Figure 8b, which effectively avoids the risk of bipolar degradation.

Even though the cell pitch of the UD-MOS is slightly larger than that of the C-MOS, the conduction capability of the UD-MOS is not degraded, because its channel density no longer dominates for high voltage SiC MOSFETs. The R_ON of UD-MOS and C-MOS are 35.48 mΩ·cm² and 35.00 mΩ·cm², respectively (@I_DS = 50 A/cm²), as shown in Figure 9a. The transfer characteristic of the UD-MOS is also not degraded, which shows nearly the same V_TH as the C-MOS, as shown in Figure 9b.

3.2. Dynamic Characteristics

The reverse recovery characteristics of the body diode in the SiC C-MOS and UD-MOS are compared, as shown in Figure 10. Thanks to no extraction of minority carrier during the reverse recovery process, the peak reverse recovery current (I_RRM) and reverse recovery charge (Q_RR) of UD-MOS are 54 A/cm² and 1.04 μC/cm², which are significantly reduced by 76% and 81%, respectively, compared to the C-MOS (I_RRM =176 A/cm² and Q_RR =5 μC/cm²).

Moreover, the dummy gate of the UD-MOS reduces the effective overlapping area between gate and drain terminals, so that the gate-to-drain capacitance (C_GD) is 4.01 pF/cm² (@V_DS = 3600 V), which is reduced by 9.5% compared with the C-MOS. Meanwhile, due to the thick oxide layer between the trench gate and dummy gate as well as a slightly smaller overlapping area, the gate-to-source capacitance (C_GS) of the UD-MOS is 18.1 nF/cm², which is reduced by 52%. Accordingly, thanks to the smaller C_GD and C_GS, the UD-MOS has a lower gate charge (Q_G) of 566 nC/cm² (@V_GS = 0 V–18 V) and gate-to-drain charge (Q_GD) of 109 nC/cm², as shown in Figure 11. Furthermore, considering conduction and dynamic capability, the UD-MOS exhibits a better loss-related figure of merit (FOM, i.e., R_ON × Q_GD [21]) of 3.87 mΩ·μC, which is 8.7% lower than that of the C-MOS.

The switching waveforms of the SiC C-MOS and DP-MOS are as shown in Figure 12. Benefitting from the reduced capacitances, the UD-MOS has lower turn-on loss (E_ON) and turn-off loss (E_OFF) of 3.80 mJ/cm² and 3.36 mJ/cm², which are 34% and 17% lower than that of the C-MOS, respectively.

One feasible process flow of the UD-MOS is presented, including (a) epitaxial growing, P body implantation, N+ source region implantation, trench etch and P+ region implantation, (b) N+ region and N base region implantation, (c) thermal oxidation and polysilicon gate deposition, (d) polysilicon etch, (e) isolated oxidation deposition and (f) metallization, as shown in Figure 13. Finally,

Table 2. Performance Comparison of the SiC C-MOS and UD-MOS.

Parameters	UD-MOS	C-MOS
RON (mΩ·cm2)	35.48	34.99
VON (V)	−1.11	−2.77
BV (V)	8317	8217
VTH (V)	5.2	5.2
IRRM (A/cm2)	54	176
CGS (nF/cm2)	18.1	37.9
CDS (pF/cm2)	149	149
CGD (pF/cm2)	4.01	4.43
QRR (μC/cm2)	1.22	5.01
QG (nC/cm2)	566	970
QGD (nC/cm2)	109	121
RON × QGD (mΩ·μC)	3.87	4.24
EON (mJ/cm2)	3.8	5.71
EOFF (mJ/cm2)	3.36	4.38

compares the main characteristics of the SiC UD-MOS and the C-MOS. The SiC UD-MOS exhibits superior performance due to the unipolar diode.

4. Conclusions

A novel 6500 V SiC trench UD-MOS is proposed with improved reverse conduction and switching characteristics. The grounded dummy gate causes the unipolar diode of the SiC UD-MOS to reduce V_ON to 1.1 V, which avoids the risk of bipolar degradation and reduces the parasitic capacitances with lower switching loss. The proposed UD-MOS provides a promising device prototype in VSC applications for HVDC transmission.