Low Power SAR ADC Design with Digital Background Calibration Algorithm

Abstract

This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage V_cm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm² in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate f_s =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.

1. Introduction

In recent years, various applications extensively use analog-to-digital converters, successive approximation register analog-to-digital converter (SAR ADC) domain in low power and medium-speed systems. SAR ADCs are essential in different types of sensors. For example, to detect all kinds of vital sign data of patients using biomedical device sensors. Environmental monitoring and surveillance use various sensors, such as gas-sensitive, light-sensitive, noise sensitive, and water pollution monitoring sensors. The precision of the ADC directly determines the quality of the sensors. A traditional fully differential capacitive charge-redistribution SAR ADC consists of four fundamental components: sample and holds (S&H) circuits, capacitive digital-to-analog (CDAC) circuit, dynamic comparator, and SAR control logic circuit. In this architecture, the capacitor mismatch is the main reason for deteriorating the whole ADC performance. Ref. [1] adopted a bypass technique which allows the design to search the capacitors with a sub-binary ratio without complexity, combined with a redundancy algorithm. Still, the error tolerance windows becoming asymmetric due to the search steps asymmetric. Ref. [2] designed an innovative input switch using 1.8 V devices in 28 nm technology, which makes it support up to 3.6 V inputs, achieve high precision at the area costs and power consumption. Ref. [3] presented a dynamic element matching (DEM) technique through residue oversampling to reduce capacitor mismatch and noise without calibration. Ref. [4] adopted 4-way interleaved and hybrid architecture achieve high speed, but capacitor mismatch and channel mismatch limited the precision due to absence of calibration. Ref. [5] presented a histogram-based ratio mismatch(HBRM) calibration method for the capacitive bridge DAC to improve conversion nonlinearity and realize a high-speed SAR ADC, it needs additional calibration time. To correct the capacitor mismatch, Ref. [6] proposed a dither-based background calibration technique with a data-weighted averaging method but required extra circuits. Ref. [7] proposed a new circuit applied the negative DAC side to reduce the dielectric relaxation effect and improve ADC performance. Some other ADC adapts the hybrid structure to improve the sampling rate [8,9,10]. Design different switching strategies to reduce quantization error and power consumption [11]. Engineers and researchers do much research and work about digital calibration techniques to improve the capacitor mismatch [12]. Each of these structures has its advantages, mainly depending on the requirements of the application domain.

This SAR ADC is designed based on common-mode voltage V_cm with a tri-level switching method. Compare with the traditional structure, it only uses half of the unit capacitors. It can save a large proportion of switching energy consumption, the most significant bit (MSB) conversion without drawing any energy, and tri-level switch changing from common-mode voltage V_cm to the reference voltage V_ref or physical ground GND in every bit of the decision subsequently. Adopt a digital background calibration with redundancy capacitor array to minimize capacitor mismatch. Improve the ADC’s static performance, such as differential nonlinearity (DNL) and integral nonlinearity (INL). The digital calibration method can make sure it is high speed and does not impact original circuits, and it is compatible with device scaling.

This paper mainly consists of five parts: Section 2 introduces the architecture of charge redistribution SAR ADC based on the common voltage V_cm with the tri-level switching method. Section 3 shows the digital calibration theory and implementation method. Section 4 displays the simulation results of ADC performance. Finally, a brief conclusion is presented in Section 5.

2. ADC Architecture

A unit capacitor C_Rd (C_Rd = C_u) adds to the capacitor arrays for signal sampling completeness. The unit capacitor C_Rd participates in the sampling process and does not participate in the quantization process. The total number of unit capacitors of the full differential N-bit charge redistribution SAR ADC is 2^N*C_u; Figure 1 depicts the structure of binary-weighted error compensation SAR ADC where it inserts three compensative capacitors array C_2C, C_5C, and C_8C, and the weight equal with C₂, C₅, and C₈, respectively. The digital error correction logic circuit is generated by the design compiler to execute the error compensation. The DAC switching method saves a large proportion of switching energy and half of the capacitors than the conventional structure. When the ADC system starts to work, the two capacitor arrays’ bottom plates start sampling the input signal. Then, the full differential dynamic comparator starts the first comparison.

2.1. Switching Method

This design adopts the strategy by using the bottom plates of the capacitor array sampling the input signal to get better linearity. Bottom plate switches changing from common-voltage V_cm to reference voltage V_ref or physical ground GND in every bit of conversion. Moreover, the most significant bit (MSB) can determine without any switching energy consumption; V_cm based tri-level switching method example, as shown in Figure 2 with 3 bits conversion. The stepping size is directly proportional to the capacitor array’s sizing during the binary search with this method. The input signal compares with (±2/4) V_ref according to the first comparison, switch turning up or down, connect with the reference voltage V_ref or physical ground GND in the DAC. For 12-bit SAR ADC, V_cm based tri-level switch structure produces switching energy consumption of 681.83 CV²_ref, saving 87.51% of changing energy consumption than the traditional DAC switch structure.

2.2. SAR Control Logic

The SAR control logic circuit is necessary to control the tri-level switches and digital codes output. At the beginning of conversion, sample and hold circuits sample the input signal, and all Flip-Flops are reset by the global reset signal at the same time. When the clock’s rising edge is coming, the Flip-Flops load the results from the comparator. MSB output isone or zero depending on the MSB switch control signal of the control logic to the DAC. Then the shift register ring counter shifts one when a bit has been decided until least significant bit (LSB). This type of shift register ring counter designed M+4 clock cycles to convert each sample, four clock cycles sampling sufficiently and steadily, and ensure the sampling bandwidth is larger than the Nyquist frequency. M clock cycles determine the MSB to LSB successively, including redundant code. This architecture keeps many advantages: Firstly, it is low power consumption based on V_cm architecture with a tri-level switching method; Besides, since the shift register ring counter and SAR control logic is iterative, it is easily extended to higher resolutions by just extending the shift registers, using this similar method, assign different clock period to an individual bit decision step is possibly and easily. Figure 3 shows the schematic of the SAR control logic and its timing diagram. CLK14 to CLK0 load the digital output codes from the comparator to the output register. After that, the digital output code feedback as control signals for the tri-level switches of lower capacitor array to accomplish the switching procedure. The digital calibration circuit performs 15b redundancy code to 12 b digital output code conversion simultaneously.

3. Calibration Implementation

In the design of charge redistribution SAR ADC uses many capacitors. The process deviation and the parasitic capacitance will inevitably cause the capacitor mismatch. Capacitor mismatch is the main cause of voltage error in conversion, directly affecting the ADC’s performance.

3.1. Capacitor Mismatch

This design considers the impacts of the parasitic capacitance on the top and bottom plates of the capacitor array, the channel capacitance of the MOS switch, and the parasitic capacitance on the comparator input gate in the case of non-ideal layout and wiring. The parasitic capacitance on the top plate of the capacitor array will cause the amplitude attenuation of the input signal, which will reduce the effective power of the input signal. This design adopts a bottom plate sampling strategy to improve the linearity. The parasitic capacitance of the bottom plate on the capacitor array will seriously affect the input signal’s linearity. This paper presents a digital background calibration technique based on capacitance array redundancy, reducing the voltage difference caused by parasitic capacitance and capacitor mismatch, thus improving the ADC’s performance. The calibration algorithm ensures to reduce or even eliminate the maximum voltage error caused by capacitor array mismatch. Figure 4 shows the histogram of the Metal-Oxide-Metal (MOM) unit capacitor mismatch in 2000 times Monte Carlo simulations.

3.2. Calibration Theory

This paper proposed one kind of a redundant research background calibration algorithm based on code-density. It starts to work with ADC operation simultaneously, converting the 15b redundant codes to 12b binary codes. In a redundant SAR ADC with M-step translate to N-bit (in which M > N), the original output bits (B_i’s and B_ic’s) and the actual decision values (D_out’s) are a function of actual capacitor values as given in Equation (1). The swing of input signal shrink with a factor of ɑ due to the redundancy capacitors, α can calculate with Equation (2), in this design, α is equal to 0.876, so the peak-to-peak of the input signal equal to reference voltage multiply the factor α, which is approximate 1.05 V. Overflow occurs when the signal swing is over the range, the digital output codes will be a settlement to the value from 0 to 4095 to keep the function normal and prevent data from spilling up or down. Figure 5 shows an example of the digital background calibration process.

$$D_{out}={\displaystyle \sum }_{\mathrm{i}=0}^{\mathrm{N}-1}\left(B_i\times 2^i\right)+{\displaystyle \sum }_{\mathrm{i}=2,5,8}\left(B_{ic}-0.5\right)\times 2^i$$

(1)

$$\alpha =\frac{{{\displaystyle \sum }}_{i=0}^{N-2}{2}^i·C_u+C_{Rd}}{\left({{\displaystyle \sum }}_{i=0}^{N-2}{2}^i·C_u+C_{Rd}\right)+{{\displaystyle \sum }}_{i=2,5,8}{2}^i·C_{ic}}$$

(2)

Previous research introduces a ditched-based background calibration algorithm to improve precision in exchange for extra power consumption and design complexity. In the non-binary weighted capacitor array design, the redundancy calibration algorithm may be ineffective in correcting dynamic switching errors as the asymmetry error tolerance windows. In this design, the redundancy capacitor array helps improve the conversion rate by symmetry error-tolerance windows, especially at the first few MSBs because of massive voltage change during transitions. The redundancy capacitor array combines with the common voltage V_cm based tri-level switching method, as shown in Figure 2. In the binary-weighted search method, the stepping size is equal to the corresponding capacitor array proportion in the overall capacitor array. Around each decision level, the stepping sizes and the error-tolerance windows are symmetric. Combine the redundant capacitors array digital background calibration algorithm with the tri-level switching method. The complexity of circuit design is reduced, but also achieves symmetric error tolerance windows with ±292 LSB.

4. Simulation Results

To test and verification the static and dynamic performance, ADC operates at a sampling rate of 2 Million Samples Per Second (MSPs) and Nyquist full-scale sine wave input signal. Figure 6 displays the differential nonlinearity (DNL) and integral nonlinearity (INL) before and after the calibration. Before calibration, the maximum DNL is +1.2/−1.1 LSB, and the maximum INL is +13.1/−13 least significant bit (LSB). After calibration, the maximum DNL reduce to +0.7/−0.6 LSB, and the maximum INL reduce to +1.1/−1.0 LSB. Figure 7 shows a 4096-points Fast Fourier Transform (FFT) simulation results of the dynamic performance. Before calibration, the signal-to-noise-and-distortion ratio (SNDR) is 51.33 dB, and the spurious-free dynamic range (SFDR) is 61.50 dB, and the effective number of bits (ENOB) is 8.23 bits. After calibration, the SNDR up to 70.15 dB, SFDR up to 85.63 dB, and ENOB up to 11.36 bits. The total power consumption is as low as 356.4 μW, and a figure-of-merit (FoM) is 67.80 fJ/conv.-step.

The differential nonlinearity and integral nonlinearity with 1000 times Monte Carlo simulations before and after calibration, respectively, as shown in Figure 8. The simulation results show that the digital background calibration algorithm improves the static performance significantly.

The effective number of bits with 1000 times Monte Carlo simulations before and after calibration, respectively, as shown in Figure 9. This indicates that the ENOB normalizes distribution with 8.23 bits mean and 0.43 bits standard deviation before calibration improves to 11.36 bits mean and 0.21 bits standard deviation after calibration. The simulation results show that the digital background calibration algorithm improves dynamic performance significantly.

Figure 10 shows the SNDR and SFDR vary with the input frequency at a constant sampling rate of fs = 2 MS/s. Both the SNDR and SFDR are decreasing slightly with the input frequency increase before and after calibrations. Both SNDR and SFDR improved significantly after calibration.

The breakdown of the power consumption of the SAR ADC test chip is shown in Figure 11. The comparator, capacitor digital-to-analog converter (CDAC), and sample and hold circuits are the main proportion of power consumption. The digital background calibration circuitsonly account for 6% of overall power consumption.

The performance comparison and summary of the prototype ADC display in

Table 1. Performance comparison with other published SAR ADC.

Specifications	Ref. [2]	Ref. [3]	Ref. [4]	This Work
Architecture	SAR	SAR	SAR	SAR
Technology(nm)	28	40	28	40
Supply(V)	1.8	1.0	1.2/1.5	1.2
Sampling Rate(MS/s)	4	40	600	2
Resolution(bit)	12	12	12	12
SNDR(dB)	70.1	63.46	60.7	70.15
SFDR(dB)	84.3	73.72	—	85.63
ENOB(bit)	11.35	10.25	9.79	11.36
DNL(LSB)	+0.2/−0.2	+0.51/−0.49	—	+0.7/−0.6
INL(LSB)	+0.6/−0.6	+1.95/−1.44	—	+1.1/−1.0
Power(mW)	1.73	1.25	26.5	0.3564
FOM(fJ/conv.-step)	165.5	25.7	68	67.80
Active Area(mm2)	0.13	0.04	0.076	0.046

shows that previous research is all 12 bits SAR ADC. Our design has excellent advantages in SNDR, SFDR, ENOB, and power consumption.

The test chip of this SAR ADC is the implementation in standard 1P8M 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology with Metal-Oxide-Metal (MOM) capacitors and 1.2 V core power supply. The active die area is 0.046 mm². The whole test chip micrograph, as shown in Figure 12.

5. Conclusions

This paper proposed a digital background calibration algorithm, combined with the common voltage V_cm based switching method and redundancy capacitors to correct the decision errors due to incomplete setting and capacitor arrays mismatch. Applied to a 12-bit full differential SAR ADC, the test chip implemented in standard 40 nm CMOS technology, at Nyquist full-scale sine wave input and 2 MSPs sampling rate reached SNDR 70.15 dB, SFDR up to 85.63 dB, ENOB is 11.36 bits. DNL and INL are +0.7/−0.6 LSB and +1.2/−1.1 LSB, respectively.