Recent Developments and Perspectives on Optimization Design Methods for Analog Integrated Circuits

Abstract

As the cornerstone of the modern information industry, designing a high-performance circuit is crucial. Due to the influence of external environmental and asymmetric arrangements, non-ideal factors in analog integrated circuits (ICs) cannot be ignored, which makes the design process heavily reliant on human experience, and the design efficiency is low. Recently, scholars have conducted extensive research on optimization design methods for analog ICs by combining artificial intelligence and optimization algorithms. In this article, the developments and perspectives on optimization design methods for analog ICs are reviewed. In traditional design methods, particle swarm optimization (PSO), the genetic algorithm (GA), and reinforcement learning (RL) have been applied with different computer-aided design (CAD) tools. A variety of circuit simulation software have been developed, such as Cadence, Ngspice, Pspice, etc. Due to its high precision, comprehensive functionality, and full-process simulation, Cadence has been widely used in the design of analog ICs. These methods can improve the design efficiency to a certain extent. In the iterative process, running the simulation software to obtain performance metrics can waste a lot of time. Thus, efficient optimization design methods have been proposed to improve the design efficiency by establishing a proxy model of the circuit, which can replace simulation software. Accordingly, three research directions in this field are proposed. In summary, this article can aid scholars in quickly understanding the current status of optimization design methods for analog ICs and provide guidance for future research.

1. Introduction

As the foundation of the modern information industry, analog integrated circuits (ICs) have a crucial impact on the development of science and technology. With the development of analog ICs, the number of transistors in a single chip has increased from a few thousand to billions, which greatly improves the complexity of the design process [1,2,3,4]. Due to the parasitic effects and non-ideal factors in analog ICs, the traditional design methods heavily rely on manual experiments and traverse methods. Through repeated simulations and modifications, acceptable circuits can be obtained, which is time-consuming and inefficient. Thus, it is urgent to improve the level of automation in analog IC design to shorten the design time and reduce costs, making research on automation in analog IC design a crucial topic.

Due to the inherent characteristics of analog ICs, the design automation level is low. Firstly, designers need to find compromises among the performance metrics of analog ICs, resulting in complex optimization designs for analog ICs, and it is difficult to find an optimal solution that can achieve the design requirements. Secondly, the topologies of analog ICs are diverse, with different strengths and limitations, which are suitable for certain performance metrics within a certain range [5]. Thirdly, analog ICs are sensitive to transistor sizes. Each size of the transistors has a significant impact on their performance, requiring careful determination [6]. In addition, analog ICs are susceptible to external factors, such as process variations, temperature changes, and parasitic factors, which can affect circuit performance under extreme conditions [7]. Thus, it is difficult to effectively design an analog IC, and many studies are aimed at achieving circuit design automatically [8].

Traditional optimization design methods for analog ICs are based on the optimization algorithm [9,10,11,12]. The optimization of analog ICs can be viewed as a multivariate optimization problem in high-dimensional space. Circuit performance metrics are taken as the objective function, with some serving as constraints, according to the design requirements, including circuit operating states and other performance requirements. Then, intelligent optimization algorithms such as particle swarm optimization (PSO), the genetic algorithm (GA), and reinforcement learning (RL) are used to find the optimal parameters meeting all constraints through an iterative process. Compared to manual design, it has the great advantage of universal adaptability to various circuit structures and greater flexibility in application.

During the iteration process, traditional optimization methods need to run simulation software continuously, which takes a lot of time. Recently, machine learning methods, including the Gaussian process (GP) [13,14,15], artificial neural networks (ANNs) [16,17,18,19], graph neural networks (GNNs) [20,21,22], etc., have been used to construct circuit surrogate models instead of simulation software due to their strong learning ability and accurate mapping. Surrogate model and optimization methods are combined in effective optimization design methods. Firstly, regression models combining circuit design parameters and performance metrics are trained by obtaining the previous circuit data, which can achieve a high accuracy and replace simulation software. Based on the established machine learning models and optimization function, the optimal design parameters are found with advanced optimization methods. Compared to the traditional optimization design methods, the optimization efficiency can be greatly improved in this method. The disadvantage is that machine learning models strongly depend on the dataset. As the scale of analog ICs increases, the datasets training the models are very large, costing a lot in computing resources.

In summary, the optimization methods for analog ICs’ design are of great significance for the development of manufacturing processes, and they can greatly improve design efficiency. This article reviews the research and progress on optimization design methods for analog ICs in recent years. The overall flowchart is shown in Figure 1. This article summarizes relevant theoretical achievements and technical methods, as well as compares and analyzes the previous research. Finally, the future development trend of intelligent technology for analog ICs is discussed.

2. Traditional Optimization Design Methods for Analog ICs

For traditional optimization design methods, heuristic intelligent optimization algorithms and RL algorithms are widely used. For a given circuit topology, the optimization of design parameters can be seen as a multi-objective optimization problem in high-dimensional space. According to the requirements, one performance metric is taken as the optimization goal, and others are taken as constraints. Based on the established optimization function and simulation software, the design parameters can be continuously adjusted by the optimization algorithm until the optimization function meets the design requirements. The traditional optimization design methods based on heuristic intelligent optimization algorithms and RL algorithms are introduced below.

2.1. Heuristic Optimization Algorithms

The optimization design methods can be converted into multi-objective problems, and the optimization algorithms can be used to achieve the multi-objective optimization. The optimization algorithm is generally a heuristic optimization algorithm. Heuristic optimization algorithms are based on heuristic strategies, starting from the initial solution, improving the quality of the solution through iteration, and using specific knowledge or empirical rules to guide the search direction, in order to efficiently find approximate optimal solutions to complex optimization problems. The advantage of the traditional design methods is that a variety of circuit structures can be handled automatically with the simulation software, which can greatly improve the design efficiency compared to manual design. Due to the advantages of the PSO algorithm, including fast convergence and simplicity, it can quickly find relatively satisfactory solutions and is suitable for scenarios that require rapid iterative optimization in simulated integrated circuit design. The GA, with its strong global search capability, can avoid falling into local optimal solutions and displays strong adaptability. The non-dominated sorting genetic algorithm (NSGA) is specifically designed for multi-objective optimization, enabling the discovery of a set of Pareto optimal solutions. The multi-objective genetic algorithm (MOGA) is applicable to various multi-objective optimization problems and is characterized by its strong versatility and progressive evolution. In contrast, the differential evolution (DE) algorithm encounters difficulties when handling problems with discrete variables and numerous constraints, and its parameter settings are complex. The artificial bee colony (ABC) algorithm is relatively weak in terms of convergence speed and global optimization capability, exhibiting lower efficiency when addressing high-dimensional problems. As a result, the PSO, GA, NSGA, and MOGA algorithms are more frequently adopted in the intelligent optimization design of analog ICs. Pankaj et al. [23] proposed an optimization scheme for the two-stage Miller compensation operational amplifier (TSMCOA) in 0.18 μm process technology. The PSO algorithm is adopted to find the optimal parameters, which takes the voltage gain, unity gain frequency, common mode rejection ratio, power supply rejection ratio, slew rate, phase margin, and power consumption as performance metrics. Compared to manual design, the proposed method is easier and more effective, even if the designer does not have a complete understanding of the given circuit. This method can also be used for optimizing other circuits and can be implanted into any electronic CAD software for design and manufacturing processes. Rashid et al. [24] proposed a design method for a TSMCOA based on the hybrid PSO algorithm and Ngspice software, which can achieve a small area and low power consumption while meeting performance metrics. The flowchart of the proposed hybrid PSO is shown in Figure 2a. By setting the performance metrics as constraints, the optimization objective can be optimized by the proposed PSO algorithm. Dendouga et al. [25] proposed a multi-objective optimization design program based on MOGA, which considers constraints and can handle optimization problems with two or more objectives. The operational amplifier design flow is shown in Figure 2b. This method is used to find the optimal size parameters (length and width) for transistors. Six performance metrics—gain, unity gain bandwidth, phase margin, power consumption, area, and slew rate—are considered, and the MATLAB (2021b) optimization toolbox is used to implement the program. The results indicated that the MOGAS-based method is effective and has a good performance in circuit design and optimization problems. Harsha et al. [26] proposed an integrated MaxFit GA-spice optimization framework to achieve the multi-objective optimization of simulation design automation. In this framework, the optimization design of TSMCOA is demonstrated to optimize open-loop direct current (DC) gain, the phase margin, unity gain bandwidth, rise time, power consumption, and area. Based on the proposed framework, the performance metrics obtaining by LTspice are transferred to the MATLAB environment, and the dynamic performance evaluation of SPICE is performed in each iteration by the GA, which can significantly improve the robustness of simulation design. Wong et al. [27] proposed a single objective optimization method based on the GA and Pspice to find the optimal transistor size for cascaded amplifiers and operational amplifiers (Op-Amps). Using the fitness function, which can be obtained by Pspice, the optimal fitness value can be selected by the GA. Although the circuit size can be optimized effectively, with the increasing complexity of circuit structures, single-objective optimization cannot fully meet the design specifications for analog ICs. Based on the above disadvantages, Das et al. [28] proposed a multi-objective GA framework to optimize the area and power consumption of the TSMCOA. Using the proposed MOGA-SPICE framework, the objectives of the TSMCOA are optimized, and all design specifications can be achieved. The final optimization results are verified by the simulation software. Huang et al. [29] proposed a multi-objective optimization algorithm NSGA-II to optimize the parameters of CMOS voltage reference circuits. The flowchart of NSGA-II is shown in Figure 2c. An initial population generation scheme based on an artificial optimal solution and special fitness function is proposed, which improves the convergence speed and optimization efficiency. Compared with the manual scheme, the line sensitivity (LS), temperature coefficient (TC), and power consumption are increased by 32.18%, 12.5%, and 19.53%, respectively. Combined with PSO and the NSGA, Sasikumar et al. [30] proposed a novel multi-objective optimization method for designing analog IC transistor sizes and bias currents, which can greatly reduce the circuit design time and improve the accuracy of performance parameters.

Dongkyung Nam et al. [31] introduced the application of evolutionary programming (EP) in the optimization design of a voltage reference circuit. Compared with other optimization methods, the proposed method does not require complex circuit analysis formulas, and users only need to select the main objectives and determine the appropriate range of each parameter. In addition, the proposed method can be easily applied to other circuits, and the parameters found by EP within the specified range have a good performance. Similarly, Jesus et al. [32] used EP to optimize low dropout (LDO) voltage regulators. An evolutionary algorithm utilizing LDO units for multi-objective optimization was proposed based on the results of tolerance analysis for the first time. In addition, a simplified search space for circuit components is established through the calculated tolerances, thereby accelerating the speed of the optimization algorithm.

In summary, the traditional optimization design algorithms can replace the manual search to find the optimal design parameters of analog ICs, which can greatly improve the efficiency of analog IC design. According to the circuit design experience, the range of parameters is set. The optimal parameters can be found by a heuristic algorithm such as PSO, GA, etc. The optimized circuits, processes, proposed methods, performance acquisition methods, accuracy, optimal parameters, and convergence of the recent research are shown in

Table 1. Summary of optimization design methods based on heuristic algorithm.

	Circuit	Proposed Method	Convergence	Optimal Parameters	Optimal Results
[24]	TSMCOA (65 nm)	Hybrid PSO	<50	W1-7, Ibias	A = 0.22 μm2
[23]	TSMCOA (0.18 μm)	PSO		W1-7, Ibias	P = 0.184 mW A = 28.52 μm2
[26]	TSMCOA (0.18 μm)	MaxFit GA	<50	W1-8, L1-8, Ibias, Cc	P = 0.166 mW A = 262 μm2
[28]	TSMCOA (0.18 μm)	MOGAS		W1-8, L1-8	P = 0.22 mW A = 150.55 μm2
[27]	Cascaded Amplifier (0.25 μm)	GA (TSOp)	50	W1-4, L1-4	I = 1.634 μA
	Op-Amp (0.25 μm)	GA (TSOp)	50	W1-6, L1-6	I = 5.21 nA
[32]	LDO (0.18 μm)	NSGA-II		WP, Co, RESR, Cc, Ibias	PSRDC = −95.8 dB PSR100KHz = −70.91 dB PSR1MHz = −61.88 dB
[29]	Voltage Reference Circuits (0.18 μm)	NSGA-II	<200	MC, MS1-3, PM0-3, M1-6	LS = 510 ppm/V TC = 6.3 ppm/°C
[30]	TSMCOA (0.18 μm)	PSO and NSGA-II		W1-8, L1-8, CL	P = 2.5 mW

. The results show that the optimization objective of the optimized circuits can be changed according to requirements, and the optimal results can be found by the heuristic algorithm under an acceptable convergence. Compared to the manual design, the design time can be greatly decreased. However, due to the limitations of heuristic algorithms, small-circuit optimization with a small number of design parameters can be optimized. For complex circuits, heuristic algorithms are prone to becoming stuck in local optimal solutions, and the convergence speed slows down. In addition, during the search process, many computing resources are consumed to run the simulations. Therefore, finding a proxy model that can describe analog circuits well has become a current research hotspot.

2.2. RL Optimization Algorithm

Analog IC design is essentially a Markov decision process, which is highly suitable for RL optimization. RL is a trial-and-error learning method based on the interaction between intelligent agents and the environment. The agent perceives the state of the environment and executes actions, evaluates the quality of actions based on the reward signals fed back from the environment, and continuously optimizes the behavior strategy of the agent using strategy improvement mechanisms such as Q-learning or the strategy gradient method. The goal is to maximize long-term cumulative rewards, thereby achieving efficient decision-making and optimization control in complex environments. Heuristic optimization algorithms guide the search process through manually designed rules and fitness functions, while the RL algorithm can learn the optimal action policy by interacting with the environment. Relying on the interaction between the intelligent agent and the environment, action strategies are adjusted continuously through the rewards and feedback from the environment, which has a better search efficiency and convergence speed.

Settaluri et al. [33] proposed an RL optimization framework AtuoCkt to find the optimal parameters for the amplifier that meet the design specifications. However, the proposed algorithm must be retrained with changes in design specifications, which is inefficient. Wei et al. [34] proposed RobustAnalog, a highly robust circuit design framework that can address the issue of high computational and time costs required for automatic simulation design of various changes. The flowchart is shown in Figure 3a. Specifically, circuit optimization under different variations is considered as a set of tasks, and the similarity between tasks is utilized to alleviate competition and achieve efficient multi-task training with samples. In addition, RobustAnalog prunes the design space based on the current performance in each iteration, which can further reduce simulation costs. In this way, RobustAnalog can quickly generate a set of circuit parameters meeting various constraints such as gain, bandwidth, noise, etc. Tang et al. [35] proposed an efficient parameterized circuit optimization method based on the RL algorithm. This method optimizes parameters by alternately training value networks and policy networks, which can greatly accelerate optimization during the training process. Budak et al. [36] proposed a deep neural network (DNN)-Opt framework to address the limitations of RL-based circuit optimization methods. The framework of DNN-Opt is shown in Figure 3b. DNN-Opt is a RL-inspired approach that modifies traditional RL-based optimization methods and adopts a critic–actor framework. In addition, DNN Opt combines the advantages of RL, Bayesian optimization (BO), and population-based technologies, which has a higher optimization effect.

Somayaji et al. [37] proposed a framework based on priority RL for a fast and high-quality design point search of analog ICs. The core idea is to combine design knowledge to optimize value network design, which can reduce data requirements during the process of reward evaluation. In addition, non-uniform sampling techniques are adopted to explore high-quality design points, and value networks can be trained under limited circuit simulation times to achieve efficient data utilization. Zhao et al. [38] proposed a topology synthesis method for analog ICs based on the deep RL algorithm. By defining design rules and the RL environment, an optimal circuit topology structure that meets design requirements can be gradually constructed. Meanwhile, hash table and symbol analysis techniques are adopted to improve the evaluation efficiency and significantly reduce the number of topologies in the structure. Yang et al. [39] proposed a spatial search method for analog IC design that combines the trust region strategy with deep RL. This method achieves fast convergence through a simple feedforward network and supervised learning, while for the first time considering process–voltage–temperature (PVT) conditions in the search process. Experiments on TSMC 5/6 nm process circuits have shown that this method outperforms human designers in terms of performance and has been applied in industrial production. Gao et al. [40] proposed RoSE, a simulation circuit parameter optimization framework that combines BO and RL. By quickly finding the optimal starting point through BO, the search efficiency of the RL algorithm can be significantly improved. Meanwhile, PVT variation characteristics are also introduced to enhance the robustness of the design process. Compared with existing methods, RoSE improves the sampling efficiency by 3.25 to 16 times and performance metrics by 6.8 to 24 times.

Choi et al. [41] proposed a new framework to optimize analog ICs, combining RL and sensitivity analysis with gm/ID to more intuitively explain circuit performance. Three types of differential amplifiers with common-mode feedback circuits are used to verify the proposed method, and the iteration times are reduced by 42.2%, 39.5%, and 37.5%, respectively. Zuo et al. [42] proposed a circuit size optimization tool RLCkt that utilizes RL and circuit simulators to automatically adjust design parameters. In RLCkt, two deep neural networks, actor and critic, are trained and a deep deterministic policy gradient (DDPG) algorithm is employed. In the experiment, a two-stage operational amplifier is used to verify the proposed method. The average error is reduced from 60% to 5.1% in nine simulation steps. Compared with the GA, RLCkt has an average convergence speed that is 94 times faster and a better generalization ability. Lee et al. [43] proposed an automated analog/radiofrequency (RF) circuit design method based on the deep Q-network (DQN) RL algorithm. Using the LTspice circuit simulator and DQN algorithm, the circuit can be optimized by adjusting the learning interval of the algorithm. The time-domain response and frequency characteristics of the first-order filter test under different resistance values indicate that the proposed method can effectively optimize high-frequency circuit blocks. Choi et al. [44] proposed a multi-agent RL framework (MA-opt). The proposed framework is shown in Figure 3d. Multiple actors can be exploited effectively by sharing a memory that affects the loss function of network training Meanwhile, a cooperative near-sampling method is introduced to improve training stability and achieve a higher performance. Bao et al. [45] proposed a framework based on multi-agent RL (MA-RL) for the design optimization of complex analog ICs, whose framework is shown in Figure 3c. The core idea of this method is to utilize multi-agent planning theory and expert design practice to decompose complex ICs into multiple sub-blocks to reduce search space complexity, and to simulate performance trade-offs between sub-blocks through interactions between multiple agents. Specifically, this method uses two multi-agent RL algorithms that combine a delayed dual-depth deterministic policy gradient algorithm and proximal policy optimization techniques to improve training stability and performance. In addition, the influence of reward function definition and state setting on the robustness of the framework is also studied. The experimental results show that the framework achieves the best performance metrics in the design of complex ICs such as gain amplifiers, delay locked loops, successive approximation register analog-to-digital converters (SAR ADCs), etc.

Figure 3. (a) Framework of the proposed RobustAnalog (reprinted from [34], Copyright 2020, with permission from IEEE); (b) framework of DNN-Opt (reprinted from [36], Copyright 2021, with permission from IEEE); (c) schematic diagram of proposed multiagent RL algorithm for complex analog ICs (reprinted from [45], Copyright 2024, with permission from IEEE); (d) framework of MA-opt (reprinted from [44], Copyright 2024, with permission from IEEE).

Figure 3. (a) Framework of the proposed RobustAnalog (reprinted from [34], Copyright 2020, with permission from IEEE); (b) framework of DNN-Opt (reprinted from [36], Copyright 2021, with permission from IEEE); (c) schematic diagram of proposed multiagent RL algorithm for complex analog ICs (reprinted from [45], Copyright 2024, with permission from IEEE); (d) framework of MA-opt (reprinted from [44], Copyright 2024, with permission from IEEE).

In summary, intelligent optimization design methods based on RL can learn the optimal strategy for analog ICs by interacting with the environment. Compared with heuristic algorithms, the search efficiency of RL is greatly improved.

Table 2. Summary of optimization design methods based on RL algorithm.

	Algorithm	Optimization Circuit	Success Rate	Runtime	Simulation Time
[44]	MA-opt	Two-Stage OTA;	10/10;	0.91 h;	<200
		Three-Stage TIA;	10/10;	0.78 h;
		LDO Regulator	10/10	1.14 h
[36]	DNN-opt	Two-Stage OTA;	8/10;	0.54 h;	132
		Three-Stage TIA;	4/10;	0.46 h;
		LDO Regulator	7/10	0.75 h
[33]	AutoCkt	Transimpedance Amplifier;	487/500		30
		Two-Stage OTA	963/1000
[42]	RLCkt	Two-Stage OTA	986/1000	4.5 h	<500
[45]	MA-RL	Gain Boost Amplifier;	9/10;		<1000
		Delay Locked Loop;	9/10;
		SAR ADC	9/10
[38]	DRN-opt	OTA	9/10	3.25 h	800

summarizes the circuit structure, success rate, running time, and simulation times optimized by scholars. Due to the strong adaptability and self-learning ability of the RL algorithm, the circuit environment can be effectively explored, and the circuits can be optimized with a high success rate, short runtime, and small simulation times. In addition, multi-agent RL is adopted to explore a larger circuit environment, and the SAR ADC with numerous parameters is optimized. Although RL methods have a fast convergence speed and greatly reduce the number of simulations, for large-scale circuits, the complex design space can also cause RL search failures. At the same time, the number of simulations can increase exponentially, which can consume many computing resources. In the future research, circuit design experience can be added to simplify the design space or guide the search path of the optimization algorithm, and establishing a surrogate model to replace circuit simulators can greatly reduce the search time.

2.3. Summary and Discussion

Due to numerous parameters and complex design space of analog ICs, design methods that heavily rely on manual experience have low efficiency in analog IC design. The design of analog ICs can be described as a multi-objective constrained optimization problem. Therefore, combining some heuristic algorithms, such as PSO, GA, NSGA-II, etc., to explore the design space of circuits can replace manual design and save on costs. However, the design space of analog ICs is discontinuous, and heuristic intelligent optimization methods are easily trapped in the local optimal solution and unable to find the optimal parameters. Therefore, the RL algorithm is applied in analog IC design. Through continuous interaction with the environment, the optimal strategy can be learned by the RL algorithm. Compared with heuristic algorithms, it has a better convergence speed and optimization effect. However, as the circuit scale expands, the design parameters can increase exponentially, leading to a decrease in the efficiency of the RL algorithm and even causing search failures. In summary, heuristic algorithms or RL algorithms can replace manual design to automatically search for the optimal circuit parameters. However, the traditional optimization design methods require obtaining the performance metrics from circuit simulation software or traditional circuit approximate equations. With the advancement of technology, non-ideal factors in circuits continue to increase, leading to the failure of traditional circuit approximate equations. In addition, simulation software takes a long time to simulate circuits in a single iteration, and much time is consumed during the process of iteratively searching for optimal parameters, which can waste computing resources and decrease the design efficiency. In future research, it is necessary to find methods to simplify the design space or to combine circuit experience to guide the search path of optimization algorithms. To address the issue of a long simulation time during the search process, it is possible to consider obtaining data from the circuit in advance and establishing a proxy model to replace the circuit simulator and improve efficiency.

3. Efficient Optimization Design Methods for Analog ICs

Traditional optimization design methods can replace manual design and greatly improve the efficiency of analog IC design. However, during the iteration process, circuit simulation software is required for continuous running to obtain the performance metrics, resulting in a waste of simulation resources. Therefore, efficient intelligent optimization methods have been proposed to replace circuit simulation software by establishing a proxy model of the circuit, which can reduce the optimization time. Due to their strong learning ability, machine learning methods are commonly used, including GP, ANN, GNN, etc. A regression model describing the relationship between design parameters and performance metrics can be constructed, and the optimal parameters can be found by optimization algorithms. The efficient optimization design method does not require many external program calls and data access operations, making it much faster than traditional optimization design.

3.1. GP Model

The Gaussian process, originating from the theory of stochastic processes in mathematics, is a supervised modeling approach that assumes the training data come from infinite space and follow a Gaussian distribution. GP models are probabilistic models that provide confidence intervals estimated in the form of Gaussian distribution standard deviation for both regression and classification predictions. The core principle is to use the mean and variance to characterize the central tendency and dispersion of data, thereby modeling and analyzing the data. GP models are commonly used in BO, which is widely used for optimization design. GP models can fit nonlinear data and directly output the probability distribution of predicted point values, which can provide good regularization effects without the need for cross-validation. He et al. [46] proposed a novel BO method based on a sparse pseudo-input Gaussian process (SPGP), which can construct a sparse GP model to approximate the traditional GP model. Without sacrificing the modeling accuracy, the computational costs of training and prediction are reduced to O (N) and O (1), respectively. Lyu et al. [47] first proposed a complete BO framework for constrained optimization of analog ICs. In the proposed method, offline GP models are replaced by online GP models, and weighted expected improvement is chosen as the acquisition function to simulate the balance exploration. The experimental results show that this method can achieve better optimization results with fewer simulation iterations. Zhang et al. [48] proposed an improved GP model combined with neural networks. The feature representations are extracted by deep neural networks, and then GPs are defined by the extracted features. Compared with GP models with clearly defined kernel functions, neural network-based GP models can automatically learn kernel functions from data, providing more accurate predictions and accelerating subsequent optimization processes. Yu et al. [49] proposed a modeling method based on the GP model for hierarchical optimization of large-scale simulation systems. The key idea is to extract a partial Pareto frontier model around an optimized block, rather than extracting the complete model. BO is used to update some models while optimizing the entire system. The experimental results show that the proposed method can achieve a cost reduction of three times without sacrificing any performance.

Lee et al. [50] introduced a highly efficient design method for SRAM based on BO and GP models. The flow chart of the proposed SRAM design optimization method is shown in Figure 4a. Through accumulation of the GP model, a low power consumption and high SRAM can be achieved. Automatic layout adjustment can be conducted by the proposed method without needing any manual modification, which can allow for a more accurate and efficient optimization process. Compared to traditional optimization design methods, dynamic power consumption can be reduced by 6.9−17.9%. Toulouse et al. [51] introduced a locally constrained multi-objective BO (LoCoMOBO) method based on GP models. Through the proposed design space divided method, the complexity of GP models can be decreased. The presentation diagram of design space for analog integrated circuits is shown in Figure 4c. Compared with mainstream BO methods, the simplified design space can improve the optimization efficiency. Three practical circuit examples are optimized, and the total running time can be reduced by 43 times compared to state-of-the-art methods. Xu et al. [52] proposed an efficient batch BO algorithm for analog ICs based on multi-point selection criteria. The workflow of the proposed BBGP-sDFO method and illustration are shown in Figure 4d. Adopting a multi-point selection criterion to select multiple points from candidates for parallel evaluation can fully utilize computing resources. The experimental results show that the proposed method can effectively reduce the simulation time while obtaining better optimization results. Compared with multi-objective acquisition function ensemble (MACE) and weighted expectation improved BO (WEIBO), the proposed method can accelerate the optimization process by up to 3× and 27×. Gu et al. [53] proposed a new batch Bayesian and GP based on an enhanced-space derivative-free optimization (DFO) method to solve high-dimensional optimization and expensive simulation cost problems. This method integrates a batch Bayesian query strategy for exploring the global design space and a GP-enhanced subspace DFO method for developing promising regions in low-dimensional subspaces, which can significantly improve simulation efficiency. Compared to state-of-the-art optimization methods, the proposed method has been proven effective in actual simulated circuits, achieving 2.05×−17.65× simulation acceleration and 1.37×−16.11× runtime acceleration. Dong et al. [54] proposed a parallel trust region BO GP (TuRBO) algorithm. The flowchart of the automatic design method for analog ICs based on BO of the parallel trust region is shown in Figure 4b. This algorithm runs in parallel in different trust regions and utilizes a multi-armed bandit algorithm for intelligent sampling to accelerate parameter optimization. Compared with the other optimization algorithm, the optimized circuit performance has been improved by 3.7% to 98.2%.

In summary, the GP is a non-parametric model that uses Gaussian process priors to perform regression analysis on data.

Table 3. Summary of efficient optimization design methods based on GP models.

	Algorithm	Optimization Circuits	Success	FOM	Training Data
[46]	SPGP	Three-Stage Amplifier;	12/12;	27.08;	515;
		Voltage-Controlled Oscillator	12/12	3.78	136
[47]	WEIBOGP	60 GHz Inductor;	12/12;	15.17;	98;
		Power Amplifier;	12/12;	60.29;	82;
		Low-Power Three-Stage Amplifier;	12/12;	27.87;	798;
		Voltage Controlled Oscillator;	12/12	3.81	181
		Charge Pump	12/12	3.95	790
[48]	NNGP	Two-Stage Operational Amplifier;	10/10;	88.17;	86;
		Charge Pump	12/12	3.48	562
[50]	LoCoMOBOGP	Three-Stage Amplifier;		7983;	73;
		Four-Stage Amplifier;		4721;	79;
		Low-Noise Amplifier		44.2	144
[52]	Two steps BOGP	Two-Stage Operational Amplifier;	12/12;	90.44;	26;
		Low-Power Three-Stage Amplifier;	12/12;	29.31;	45;
		Charge Pump Circuit	12/12	3.33	29
[53]	BBGP-sDFO	Voltage-Controlled Oscillator;	10/10;	4.03;	144;
		Charge Pump;	10/10;	4.74;	85;
		Ac-Coupled Instrumentation Amplifier;	10/10;	11.16;	389;
		Operational Transconductance Amplifier	10/10	10.5	340
[54]	TuRBO	Trans-Impedance Amplifier;		0.0052;	374;
		Ring Amplifier;		0.051;	399;
		AC-Coupled Instrumentation Amplifier		0.0072	407

summarizes the success rate, figure of merit (FOM), and simulation times to obtain the training data. For small-scale circuits, the results show that the established models have small training data and high model success rate, which can replace simulation software, and the design efficiency can be improved with corresponding intelligent optimization algorithms. However, the GP is a non-parametric model, and each inference requires matrix inversion of all data points. The time complexity of n sample points is approximately O (n³), and the space complexity is O (n²). As the circuit scale increases and the design parameters increase, the GP consumes a large amount of computational resources and even leads to model failure. On the other hand, the expansion of dimensions makes the search space complex, and it is difficult to find the optimal solution. Therefore, in future research, it is necessary to establish more advanced lightweight models to solve the problem of model costs caused by the increase in dimensions.

3.2. Neural Network Models

A neural network (NN) model is a computational model inspired by the structure of biological neurons and composed of a large number of artificial neurons connected by weights. Each node has a specific output function, called the activation function, and every connection between two nodes represents a weighted value for the signal passing through that connection. The output of the network varies depending on the connection method, weight values, and activation functions of the NN. The principle is to receive data through the input layer, extract data features layer by layer, and transmit information through weighted summation of neurons in the hidden layer and non-linear activation function processing. Finally, the prediction result is given in the output layer. At the same time, the back-propagation algorithm is used to adjust the weights based on the prediction error to achieve approximation and pattern recognition of complex functions. First, the boundary of the design parameters is set based on experience, and then the relationship between the design parameters of the analog ICs and the performance indicators is obtained through simulation using Cadence software, eliminating some points with simulation errors to acquire the database. Here, 80% of the data is selected as training data to train the NN model, while 20% of the data is used as test data to validate the accuracy of the NN model. Thus, through training and validation, the NN has gained the ability to learn the complex mapping between design parameters and performance indicators. The computational mode endows neural networks with powerful learning and nonlinear fitting capabilities, leading many scholars to study the application of NN in modeling analog ICs. Devi et al. [55] established a global NN model for automated design, and the structure of NN models is shown in Figure 5a. The results show that the established model has high accuracy and can replace simulation software, reducing the simulation time. Yang et al. [56] proposed an efficient optimization design method based on the NN model and PSO algorithm. The optimization framework of ANN-PSO is shown in Figure 5b. By establishing the NN models to describe the relationship between design parameters and performance metrics, the PSO algorithm is used to optimize the parameters. Compared to traditional optimization algorithms, the model-based optimization method can greatly improve the design efficiency. Wu et al. [57] proposed a novel analog IC framework with non-smooth terms using proximal projection neural networks (PPNNs) and inertial proximal projection neural networks (IPPNNs). The behavior of neurons is fed back by a loop circuit comprising integrators, gradient estimation, proximal operators, and other basic operational models. In addition, an effective soft threshold operator simulation circuit is furtherly designed by considering the non-smooth term as the norm, and the effect both PPNN and IPPNN has been proved theoretically. Morteza et al. [58] proposed a fully automated analog IC generation framework called AnGeL, which utilizes NN models to assist in designing analog ICs and can perform all circuit design steps from determining circuit topology to optimizing circuit parameters. The topology-combiner model is shown in Figure 5c. The results show that compared with existing technologies, AnGeL reduces the required labeled data by 4.7 times while maintaining the same accuracy. Yang et al. [3] proposed a high-efficiency co-design method for a bandgap reference (BGR) circuit by sub-module optimization. Based on the established NN models and approximate equations, the BGR circuit can be optimized effectively by the PSO algorithm and interior point method.

However, the accuracy of the established machine learning model is decreased and the training data are increased as the analog ICs become complex, which requires a long time in obtaining the data. Li et al. [59] proposed a parallel modeling method by partitioning the search space and establishing multiple ANNs to improve the design efficiency. However, this method requires multiple devices to simulate, with high consumption costs, and does not effectively solve the modeling problem. Budak et al. [60] proposed a new high-performance simulation building block (ESSAB) as an efficient alternative model to address the issues of high costs of machine learning. The proposed method contains a new candidate design ranking method and a new ANN model construction method. Two amplifiers and one comparator are used to verify the proposed method, and the optimized results demonstrate the advantages of ESSAB.

Compared to the common machine learning methods, deep learning has a stronger fitting ability, feature extraction ability, and higher modeling accuracy for larger-scale analog ICs. Therefore, efficient optimization methods based on deep learning are currently being studied. Chen et al. [61] proposed a universal high-efficiency modeling method for analog ICs based on a convolutional neural network (CNN), named CNN-IC. The circuit topology information can be presented by the sparse topology mapping method, and the ‘transistor-circuit module-integrated circuit’ features can be extracted level by level through the CNN. The results show that the established model has a higher model accuracy. Elsiginy et al. [62] proposed a hybrid design optimization method that combines evolutionary algorithms (EAs) with multi-output DNNs to obtain fast and accurate circuit optimizers. This work provides important insights into how to choose the optimizer of the DNN structure, indicating that the Adadelta optimizer is the best approach during the training process of DNNs. Singhal et al. [63] used deep learning algorithms to optimize analog ICs and predicted key design variables (effective channel width, load resistance, bias voltage, etc.) based on given performance metrics (voltage gain, bandwidth, swing ratio, etc.). The effectiveness of the method was verified by numerical simulations of resistive-load common-source amplifiers, active-load common-source amplifiers, and active-load differential amplifiers. Meanwhile, based on a DNN, Zargaran et al. [64] proposed a method for modeling common nonlinear circuit modules in serial and memory links, which prove the DNN can learn and estimate the performance of complex systems, and the modeling accuracy is higher than traditional methods.

In summary, due to its strong learning and nonlinear fitting abilities, the dimensionality disaster problem is solved in the GP model.

Table 4. Summary of efficient optimization design methods based on NN models.

	Algorithm	Circuit Structure	Accuracy	Dataset	Modeling Time
[55]	Gm/Id-ANN	Two-Stage Single-Ended Op-Amp	R2 = 93%	7361
[56]	ANN-PSO	Two-Stage Operational Amplifier	R2 = 99.9%	21,875	63 s
[59]	ANN-GA	Two-Stage Rail-to-Rail Op-Amp;	R2 = 99.5%	632	9 min 44 s
		Fifth-Order CBPF;
		OPA Circuit of the Fifth-Order CBPF
[61]	CNN-IC	Two-Stage Operational Amplifier	R2 = 99.9%	5832	2 min
		BGR Circuits	R2 = 99%	7776	5 min
[62]	DNN-ADC	Pipelined ADC		2048

summarizes the circuit accuracy, dataset, and modeling time of a machine learning model established by scholars. By obtaining circuit data in advance, machine learning models for more complex circuits can be established with a high accuracy. The optimization time can be decreased by obtaining the performance metrics from the constructed models during the iteration process. With the expansion of the circuit scale, deep learning has a higher accuracy than ordinary machine learning models due to the deeper layers and better feature extraction ability. However, as the circuit scale expands, the amount of data for training the model can also increase, which wastes a lot of simulation resources. In addition, the input data structure of the NN model is simple in vector form and does not consider the topology and other characteristics of analog ICs. In future research, a comprehensive global model for analog ICs should be constructed by considering the topology, environmental factors, manufacturing processes, transistor sizes, and other characteristics, and lightweight models with small data should be studied.

3.3. Graph Neural Networks

GNN models are a deep learning method based on graph structures, consisting of graph data structures and neural networks based on graph theory. The principle of the GNN model is grounded in the concepts of message passing and node updating. Through the definition of node aggregation functions and update functions, each node is able to obtain information from neighboring nodes and update its own representation vector. This mechanism facilitates the learning of node relationships and topological feature embedded in graph-structured data, thereby allowing various downstream tasks including node classification, graph classification, and link prediction to be effectively accomplished. Due to their excellent ability to handle unstructured data, GNN models are widely used in network data analysis, recommendation systems, physical modeling, and natural language processing. Analog ICs are composed of many current nodes, which can change the circuit performance by changing the current. Therefore, the current nodes of analog ICs can be set as graph nodes, and the interconnections between nodes of analog ICs can be regarded as graph connections. Thus, GNNs can be constructed to predict circuit performance, and the constructed GNNs can well reflect the topological structure of the circuit, further improving its modeling accuracy. Wang et al. [65] proposed a general model based on graph learning for predicting the performance of different circuits in operational trans-conduct amplifier (OTA) libraries. The training data can be simulated by DC simulation. Using GNNs and attention mechanisms, different structures can be modeled. DC parameters and structural information are utilized in the proposed method to reduce information loss through the readout operation of the attention mechanism, achieving highly accurate predictions of the OTA performance. Wei et al. [66] proposed a machine learning framework based on graph theory for the automation design of analog ICs. The circuit transfer function can be evaluated through graph theory, which avoids time-domain simulation. A graph-based encoding method is developed to represent the circuit topology, and the circuit topology is optimized by evolutionary algorithms. The experimental results show that the proposed method can effectively generate high-quality circuits. Hong et al. [67] proposed an automated circuit classification method based on a GNN for identifying the structural features of analog ICs, and the structure of the established model is shown in Figure 6a. The core idea is to utilize the graph structure feature extraction capability of the GNN to model circuit netlists as graphs, thereby achieving high-precision classification and hardware assurance analysis. The experimental results show that this method exhibits a classification accuracy of 98.3% on the analog ICs, significantly better than the performance of traditional methods based on artificial knowledge and statistical heuristics.

In addition, the GNN can also be used in other advanced circuits. Hung et al. [68] proposed a transfer learning diagnostic framework based on a GNN for rapidly locating delay faults in monolithic 3D ICs, whose flowchart is shown in Figure 6b. The proposed method improves the generalization ability of diagnostics through a GNN. By combining with diagnostic resolution enhancement, algorithms can effectively locate the fault at the device level. The experimental results show that the diagnostic resolution of the framework has been improved by 32.86% in the monolithic 3D benchmark design. Saravanan et al. [69] proposed a noise-adaptive quantum-circuit mapping method based on a GNN and RL to improve the output fidelity of noise medium-scale quantum computers. The core idea is to construct a reliability prediction model for quantum hardware through a GNN and then optimize the mapping strategy by RL. The experimental results show that the output fidelity of the method is significantly better than existing quantum circuit mapping techniques on different practical quantum hardware. Hakhamanishi et al. [70] proposed a pre-training method based on a GNN for modeling analog ICs based on few simulation data, and the diagram is shown in Figure 6c. The core idea is to predict the output DC voltage through supervised learning to assist the GNN in learning general knowledge of circuit component interactions, which can achieve rapid adaptation for new circuit topologies or unknown circuit performance metrics. The experimental results show that the proposed method has a sample efficiency 10 times higher than the random initialization model on new tasks. Liu et al. [71] proposed an automation design method for analog ICs based on a GNN and BO, which can consider the parasitic effect to improve the performance prediction ability and optimization convergence speed. By establishing the GNN model of parasitic parameters, the transistor size can be optimized by BO. The experimental results show that the proposed method improves the R² prediction score by 20% and optimizes the convergence speed by 3.7 times and 2.1 times, respectively. Xie et al. [72] proposed a customized method based on a graph attention network (GAT) for estimating the network length. The topological characteristics can be captured by the GAT, and the key network lengths and path timing can be predicted in advance to improve the quality of design optimization.

Figure 6. (a) Architecture of GNN model for circuit classification (reprinted from [67], Copyright 2021, with permission from IEEE); (b) flowchart of fault diagnosis based on a GNN for analog ICs (reprinted from [68], Copyright 2023, with permission from IEEE); (c) diagram of pre-training method based on a GNN (reprinted from [70], Copyright 2023, with permission from IEEE).

Figure 6. (a) Architecture of GNN model for circuit classification (reprinted from [67], Copyright 2021, with permission from IEEE); (b) flowchart of fault diagnosis based on a GNN for analog ICs (reprinted from [68], Copyright 2023, with permission from IEEE); (c) diagram of pre-training method based on a GNN (reprinted from [70], Copyright 2023, with permission from IEEE).

In summary, the connection relationships between circuit nodes can be learned by a GNN, which can consider the impact of circuit topological information on circuit performance. Compared to the vector input form in the NN models, more circuit information can be considered comprehensively by a GNN. However, as the scale of analog ICs expands, the number of nodes in the circuit can increase dramatically, which will greatly increase the training complexity of the model. In future research, a global model considering the topology connection and size of transistor information should be constructed.

3.4. Summary and Discussion

In traditional optimization design methods, optimization algorithms are used to automatically find the optimal parameters for analog ICs, which can effectively replace manual design. However, the continuous iterative optimization process consumes a lot of simulation time. Therefore, a circuit proxy model is established to replace simulation software in the efficient optimization design methods. Three types of circuit modeling are widely used. The first is to establish a probability-based GP model, a mathematical probability model in the form of Gaussian distribution standard deviation. By continuously adjusting the kernel function and mean function during the iteration process, the probability distribution of the predicted points can be directly output, which has a fast training speed and high accuracy for simple circuit structures. However, the GP is a non-parametric model, and each iteration requires solving the inversion matrix. For complex circuit structures, the spatial complexity of the GP model exponentially increases, making the modeling process difficult. NN models have strong learning and nonlinear fitting abilities. By adjusting the number of neurons and layers, the performance metrics of analog ICs can be predicted, which can avoid the complex inverse process. Compared with the GP model, the NN model has a higher modeling efficiency. In addition, due to the strong feature mining ability and deeper neural layers, deep learning has a higher modeling accuracy for complex analog ICs than NN models. However, the input data of the NN model are in vector form, which cannot reflect the topological structural information for analog ICs. GNNs are composed of graph data structures and neural networks based on graph theory. The nodes of analog ICs are taken as graph nodes, and the connection relationships between nodes are taken as graph edges, which can reflect the topological structural information of the circuit more comprehensively. However, as the circuit scale increases, it leads to a surge in circuit nodes, which increases the complexity of the model. Due to the necessity of solving inverse matrices in GP models when constructing probabilistic models for analog ICs, there are significant computational burdens faced when dealing with large and complex analog ICs, which makes accurate and efficient modeling challenging and leads to significant computational limitations. In contrast, ANN models establish a mapping relationship between inputs and outputs through computations among neurons. Compared to GP models, ANN models not only significantly reduce the computational load but also demonstrate a superior performance in modeling accuracy. However, machine learning models typically require defined parameter ranges based on circuit design experience, which means they can only deliver precise predictions within the given parameter boundaries, while exhibiting relatively poor generalization capabilities for parameters outside that range. To address this issue, a scalable NN model can be employed, constructing a transfer learning model by pre-training a set of initial parameters from similar circuits. This model allows for a certain degree of scalability within the same class of circuits. Additionally, for complex circuits, deep learning methods can be utilized to enhance modeling accuracy and generalization capabilities by extracting circuit features. In summary, the proxy models can effectively replace simulation software for small-scale circuits, which can reduce the optimization time and improve the design efficiency for analog ICs. With the continuous expansion of the circuit scale, the complexity of the model can increase, and the training data increase exponentially. In addition, the circuit performance metrics are influenced by much information, and the current research on modeling methods considers few circuits’ information. In future research, it is necessary to consider various aspects of circuit information, such as the circuit topology, process parameters, and transistor size, to construct a comprehensive global model for analog ICs. At the same time, lightweight agent models should be studied by further extracting the circuit feature information to reduce the simulation costs.

4. Conclusions and Perspectives

Analog ICs are the foundation for the modern information industry. The increasing integration of chips has led to higher design complexity, which makes manual design difficult. Moreover, with the progress of technology, non-ideal factors and parasitic effects in analog ICs can increase, which leads to a high dependence on manual experience and traversal methods in analog IC design. To improve the design efficiency of analog ICs, extensive research on optimization design methods has been conducted by scholars. In the traditional optimization design methods, optimization algorithms, such as heuristic optimization algorithms (PSO, GA, NSGA-II), and RL algorithms are used to replace manual exploration for the design space of analog ICs, which can effectively improve design efficiency. However, the traditional optimization design methods require obtaining performance metrics from circuit simulation software or circuit approximate equations during the iterative process. Non-ideal factors and parasitic effects in the circuit can make the approximate equations inaccurate. In addition, the iterative search for optimal parameters can consume much simulation time and waste computing resources. Thus, efficient optimization design methods have been studied by modeling the circuit to replace the circuit simulator, such as GP models, NN models, and GNN models. By obtaining circuit data to construct a surrogate model for analog ICs, the performance metrics can be predicted instead of a circuit simulator. Then, intelligent optimization algorithms are used to optimize the circuit parameters based on the established surrogate models, which can greatly reduce the optimization during the iteration process. However, the efficient optimization design methods also have certain limitations. Firstly, the circuit information in the constructed models is not comprehensive. GP models construct a probabilistic model for analog ICs. The design parameters are input in vector form in the NN models and only the size information is considered. The topological connection information of the analog ICs can be extracted by GNN models. Only single information in the analog ICs is contained in the established models, which limits the accuracy of models and cannot describe the circuit well. Secondly, as the circuit scale expands, the data required for training the model can increase exponentially, resulting in significant costs of simulation resources and a decrease in overall optimization efficiency. The GP model, as a probabilistic model, demonstrates good adaptability in small dataset environments, effectively capturing the probabilistic distribution characteristics of the data, and is suitable for problems with evident Gaussian distribution features. However, when faced with complex data distributions and high-dimensional data, the modeling capabilities of the GP model have certain limitations, and the accuracy is typically inferior to that of NN models. In contrast, NN models possess robust nonlinear modeling capabilities, enabling them to automatically learn complex features and patterns within the data, making them suitable for large-scale datasets and intricate problems. Nevertheless, NN models require a considerable amount of data for training, which can lead to significant simulation time consumption during the data acquisition process for complex circuits. While NNs exhibit strong predictive capabilities within the limited range of datasets when capturing the complex interactions of analog ICs, their generalization ability is relatively weak when it comes to data outside this range. Although the GP model has stronger generalization capabilities compared to NNs, it is unable to construct analog IC models with complex data distributions and high-dimensional variables, and it falls slightly short in capturing aspects such as process variations and environmental factors.

For the traditional design optimization method, the optimization technology proposed in this paper can be linked with the CAD tools, and the performance indicators can be obtained through the CAD tools, which can directly guide the search process of the optimization algorithm, so as to achieve efficient optimization of the analog integrated circuit design. In terms of efficient optimization design methods, it is possible to integrate the internal circuit simulation data of the company to build a database for training circuit models. Combined with the constructed model and optimization algorithm, the design of analog ICs can be completed efficiently. In order to ensure that the performance of the designed circuit is consistent with the actual test results, the parasitic parameters involved in the tape-out process (such as layout, environmental factors, and process parameters) can be incorporated into the training data of the circuit model, so as to ensure the reliability and performance of the designed circuit in practical applications.

Although all optimization design methods can replace manual design to improve design efficiency, they are only applicable to small-scale circuits and situations with fewer design parameters. Additionally, the boundaries of design parameters and initial search values must be specified based on design experience to achieve better results. For large-scale complex circuits, current optimization design methods do not perform well, as they require long modeling times and are prone to local optima, which may even lead to failure. Therefore, optimization design methods still need to evolve in a more intelligent direction.

Based on the above analysis of the advantages and limitations of each method, three directions for future improvement are proposed in this article.

4.1. Design Specifications Can Be Added in the Search Process

The search efficiency of heuristic optimization and RL algorithms for the complex design space of analog ICs is low, and the optimal solutions easily become stuck in local optima. By transforming the design experience into the circuit design specifications, the established design specifications can be added into the search process of optimization algorithms, which can accelerate the search speed and improve the efficiency of optimization design.

4.2. Comprehensive Global Circuit Model Should Be Trained

Only a few circuits’ information is considered during the training process of the circuit proxy models. The actual design for analog ICs is not only influenced by the transistor size; beyond that, circuit topology connection information, the simulation environment, and technological information can also have a significant impact on circuit performance. In future research, global circuit proxy models considering the comprehensive circuit structure should be built to improve model accuracy.

4.3. Lightweight Circuit Model with Small Training Data Should Be Built

The circuit proxy model can replace simulation software to reduce the waste of simulation resources caused by continuous iteration during the optimization process. However, a large amount of data need to be obtained in advanced to train a high-precision proxy model. As the circuit scale expands, the training data increase exponentially. In future research, the features of analog ICs need to be extracted further, and the design space should be simplified to construct lightweight models with small training data. The feasible measures are as follows: (1) Improving data quality can reduce the dependence on large-scale data to a certain extent, so that limited data can have greater value, thereby reducing the resource consumption of data collection and processing. (2) Physics-informed neural networks (PINNs), as an emerging deep learning technology, present a unified modeling framework driven by both physical equations and data. This directly integrates physical equations into the neural network loss function, ensuring that model predictions strictly adhere to physical laws and reducing the reliance on large-scale labeled data. In light of this, future research could consider constructing PINN models by integrating approximate equations of analog ICs. This supports small-sample learning and lightweight models, maintaining a high level of accuracy even when experimental data are insufficient. Such models would not only inherit the powerful learning capabilities of NNs but also simultaneously account for the impacts of physical mechanisms such as processes and environmental factors, thereby providing a more comprehensive and accurate approach to modeling analog ICs. (3) In the training process, mixed-precision training with different precision data types can reduce the consumption of computing resources under the promise of ensuring the accuracy of the model.

In conclusion, in the future research on intelligent optimization methods for analog ICs, an expert knowledge base can be built based on circuit design experience to assist in the search process of optimization algorithms. At the same time, by comprehensively considering the structural information, parameter information, and parasitic parameters of the circuit, a comprehensive analog IC model is constructed to improve its generalization ability. In addition, it is also an important research direction to combine advanced deep learning technology to excavate the underlying features of circuits, build lightweight models with small data volumes and obvious features, and reduce simulation costs. At present, the intelligent technology of analog ICs is mainly used in the adjustment of the size of circuit transistors. Future research should further expand the application scope of intelligent design and include key links such as circuit layouts and topological connections, so as to realize the intelligent design of the whole process of analog ICs. While EDA technology for digital ICs is well-established, analog ICs have not yet reached the same level of maturity due to their unique technical barriers. Therefore, the optimal design method of analog ICs needs to be continuously improved to improve its generalization and automation level, break through the technical barriers of analog IC EDA design, and promote the overall progress of analog IC design technology.