Chaos Anticontrol and Switching Frequency Impact on MOSFET Junction Temperature and Lifetime

Abstract

Generating chaos from originally non-chaotic systems is a promising issue. Indeed, chaos has been successfully applied in many fields to improve system performance. In this work, a Buck converter is chaotified using a combination of the switching piecewise-constant characteristic and of anticontrol of chaos feedback. For electromagnetic compatibility compliance reasons, this feedback control method is able, at the same time, to achieve low spectral emissions and to maintain a small ripple of the output voltage and the inductance current. This new feedback implies a fast and non-linear switching action of the Buck MOSFET on a period of the ramp generator. Thus, it is essential to analyze its thermal performance. This is why we propose an original analysis of the influence of anticontrol of chaos and switching frequency variation on junction temperature: we investigate the correlation between the lifetime of the power electronic switching component and its thermal stress due to the addition of chaos. It appeared that a reduction in the current ripple did not degrade the MOSFET junction thermal performance, despite the fast switching of the MOSFET. Furthermore, a small degradation in the MOSFET lifetime was indicated for chaotic behavior versus periodic behavior. Thus, this leads to the conclusion that using anticontrol of chaos produces a low accumulated fatigue effect on a Buck converter semiconductor.

1. Introduction

Chaos has been extensively studied by a large scientific community, as an interesting complex dynamic phenomenon. First, chaos was analyzed as a phenomenon that can occur naturally through variations in system parameters [1,2]. For example, a Buck converter can exhibit chaotic behavior with variation in the current reference [3,4], the inductance [5] of the converter, the load [6], the voltage reference [7], or a control parameter [8,9].

Recently, chaos has evolved to a new phase of control (i.e., suppression of chaos), utilizing chaos or the generation of chaos from an originally non-chaotic system. The goal of purposefully causing chaos (a shift from order to chaos), also known as chaotification or anticontrol of chaos, has garnered a lot of interest lately because of its enormous potential in unconventional applications, with opportunities to employ entirely novel and different strategies.

Numerous chaotic and nonlinear events have been seen in optical or physical systems [10,11]. From the conventional tendency of comprehending and analyzing chaos to using it, the study of chaotic dynamics has changed, such as in financial time series [12]. Chaos anticontrol has attracted increasing interest for secure data transmission, especially in image cryptography [13,14,15]. In biology and medicine, chaos is exploited in the modeling of certain pathologies, leading to therapeutic solutions, notably for the control of epileptic seizures [16] and the analysis of chaotic diseases via fractional-order models of Diabetes Mellitus, Human Immunodeficiency Virus, Ebola Virus, and Dengue models [17]. In addition, neuronal and genetic models illustrate the role of chaos in neuromorphic behaviors and genetic regulation [18,19].

In the field of electrical systems, ref. [20] proposed an anti-oscillation (control of chaos) scheme for a fractional-order brushless DC motor system. This approach aims to eliminate chaotic oscillations in systems with unknown dynamics and immeasurable states, ensuring stable operation by effectively suppressing chaotic behavior. Similarly, ref. [21] introduced the modified chaos grasshopper algorithm, an advanced optimization approach. This algorithm was applied to improve the performance of techno-economic energy management strategies in microgrids incorporating fuel cells, batteries, and photovoltaic systems. A chaos learning butterfly optimization technique with enhanced extraction of the photovoltaic model parameter was presented in [22]. Following a numerical evaluation of the second-law characteristics of a solar water heater with a dual-twisted tape turbulator, ref. [23] used nonlinear calibration with chaos control to establish a thermal energy prediction model for varying Reynolds numbers and twist pitch values.

Switch-mode power supplies produce electromagnetic interference (EMI) at their switching frequency and harmonic frequencies. This interference significantly complicates achieving electromagnetic compatibility (EMC), especially when employing pulse-width modulation (PWM) techniques. The modulation of the switching frequency, as presented by [24,25], is a technique aimed at reducing spectral emissions. In 1999, Deane further proposed the innovative idea of using chaos to improve electromagnetic compatibility by diminishing spectral peaks [26]. However, the application of the classical chaos anticontrol method to switch-mode power supplies increases the overall magnitude of output voltage ripple, a result corroborated later by [27]. In contrast, refs. [28,29] introduced a chaotified nonlinear feedback approach capable of achieving low spectral emissions, while maintaining minimal output voltage ripple by employing chaotic attractors with small dimensions. More recently, ref. [30] proposed a chaos-based pulse-width modulation technique that leverages a logistic map to distribute the harmonics of a Boost converter, effectively reducing electromagnetic interference. Building on these advancements, ref. [31] introduced a novel radio frequency transmitter that utilizes a chaotic sequence generator to minimize output signal hysteresis and applies a modulation process to reduce spectral emissions. Additionally, ref. [32] studied a high-frequency isolated quasi Z-source photovoltaic grid-connected micro-inverter employing chaotic frequency modulation technology to effectively suppress inverter spectral emissions.

The anticontrol of chaos feedback necessitates rapid switching actions in converters, which impose thermal stress on power-switching semiconductor devices [33]. Consequently, it becomes critical to analyze their thermal performance to ensure operational safety and prevent failures of power devices [34]. To evaluate the efficiency and reliability of power electronic systems, semiconductor devices are often modeled as ideal switches in fast simulations, as seen in [35]. However, this approach makes it challenging to accurately calculate Metal Oxide Semiconductor Field Effect Transistor (MOSFET) power losses. Establishing an electro-thermal model [36] is essential to account for the impact of junction temperature on the device parameters.

Numerous electro-thermal models have been presented in the scientific literature. For approximating Insulated Gate Bipolar Transistor (IGBT) switching and on-state losses, Ref. [37] employed the lookup table method. Using inputs such as junction temperature and electrical load, a complete and comprehensive electro-thermal model was proposed by [38]. Similarly, the model by [39] incorporates the interactions between junction temperature and the transistor’s voltages and currents. In [40], power losses were averaged across each switching cycle using a high-speed electro-thermal model. Furthermore, Refs. [41,42] developed a realistic converter model, with parameters derived from component datasheets, the printed circuit board layout, as well as cable length and diameter.

To analyze MOSFET thermal behavior, the most prevalent heat transfer model uses several $RC$ Foster [43,44] networks. In [45], Nayak and Pramanick utilized a third-order Foster circuit to accurately fit the MOSFET impedance curve provided in the datasheet. Additionally, Ref. [46] proposed various electro-thermal Foster circuit variants to simulate the performance of an electric vehicle inverter.

Changes in the power device junction temperature affect their reliability and lifetime, according to [47]. The Coffin–Manson law is one of the most widely used models for evaluating failure cycles and estimating the lifetime of switching devices. Inverter lifetime [48] is commonly assessed using the rainflow counting algorithm, which takes as inputs the mean junction temperature and the variation in junction temperature [49,50,51]. In [52], an analysis was presented on the influence of chaos on junction temperature, revealing that a chaotic current behavior reduced the MOSFET’s lifetime by half, compared to a periodic current behavior.

MOSFET on-state resistance $R_{ds}$ is not only junction-temperature-dependent but also a failure precursor indicator. Indeed, an increase in $R_{ds}$ increases the MOSFET degradation. The continued modification of $R_{ds}$ imposes an online monitoring for $R_{ds}$ prognosis, in order to evaluate the device lifetime. Indirect temperature measurement methods investigate the relationship between typical thermal-dependent parameters and MOSFET on-state drain-source resistance. The junction temperature is estimated by measuring temperature-sensitive electrical parameters, such as the on-state drain-source voltage [53] and current, the threshold voltage, peak gate current [54], turn-on collector current transient [55], plateau voltage, turn-off collector-emitter voltage transient [56], voltage across source/emitter parasitic inductances [57], turn-on [58], and turn-off [59] delay times. Furthermore, the use of temperature-sensitive electrical-parameter-based sensors increases the overall circuit complexity.

Compared to many studies in the literature, where anomaly monitoring was conducted entirely through simulation, [60] proposed the Processor-in-the-Loop test: an innovative aging monitoring technique, linked to $R_{ds}$ modification, based on the creation of a virtual dataset representative of the aging phenomenon. The design of an estimator of the $R_{ds}$ was based on Artificial Neural Network regression (a simple and compact IA-based model). A more accurate real-time model was developed, including the on-line modifying of $R_{ds}$. The model predictive control [61] design by the same authors is robust to variations in system parameters, such as load or temperature, incorporating these variations into the optimization problem.

After the chaotification of a Buck converter (in order to reduce spectral emission), the purpose of this article is to analyze the influence of the anticontrol of a chaos controller on the junction temperature and to compare it with a standard feedback (Proportional-Integral PI controller). The anticontrol of chaos feedback (a combination of anticontrol of chaos and a PI standard controller) is capable of simultaneously achieving low spectral emissions, while maintaining minimal ripple for both the output voltage and the inductor current. The results confirm the effectiveness of the chaos anticontrol feedback for achieving low spectral emissions. The quantitative information confirmed that the output voltage power spectrum is reduced by almost half if a chaotified nonlinear feedback is introduced, compared to non-chaotified types. Fast and non-linear MOSFET switchings cause thermal stress. In this study, we propose investigating the correlation between the lifetime of a C2M0080120D MOSFET [62] and its thermal stress due to the anticontrol of chaos and switching frequency variation. A reduction in the current ripple enhances the MOSFET junction thermal performance. A step-by-step process establishes an electro-thermal model of the MOSFET, integrating power losses (which include the conduction, switching, diode conduction, and reverse recovery losses). Finally, the Miner’s model accumulated stress of the MOSFET is quantified, evaluating the number of failure cycles using the Coffin–Manson equation and the thermal cycle number using the rainflow counting algorithm. The accumulated fatigue showed a slight degradation in the MOSFET lifetime with anticontrol of chaos feedback (in comparison to a standard controller), despite the fast switching of the MOSFET. Thus, this leads to the conclusion that using anticontrol of chaos produced a slight degradation in the remaining life of the Buck converter semiconductor.

The main sections of this paper are as follows: Section 2 describes the behavior of a Buck converter with both a standard and anticontrol of chaos controller. In Section 3, the MOSFET power loss calculations and thermal model are detailed. Then, in Section 4, the lifetime model for estimating the damage on a MOSFET is presented. The paper concludes in Section 5.

2. Nonlinear Behavior of a Buck Converter

In this paper, our study is focused on a Buck converter, whose topology is shown in Figure 1. The circuit consists of an inductance L, a diode D, a MOSFET switch (C2M0080120D), a capacitance C, and a load R. The output voltage $V_{out}$ tracks the reference signal $V_{ref}$, ensuring the desired stabilized output voltage.

When the MOSFET is in on-state, the energy is stored in the inductance L and in the capacitance C, and no current flows through the diode D. When the MOSFET is in off-state, the diode now conducts, ensuring a path for the inductor current $i_L$. The Buck converter uses a periodic switching to step down the input voltage $V_{in}$. This is achieved by controlling the power MOSFET using a pulse-width modulated signal. This signal is generated using an error amplifier (i.e., the deviation between the output voltage and a reference voltage), a proportional integral derivative (PID) controller, and the ramp input voltage (characterized by $V_L$ and $V_U$) to adjust the duty cycle of the switch.

Table 1. The main specifications of a Buck converter operated with feedback control.

Specification	Parameter	Symbol	Value	Unit
Buck converter	Input voltage	$V_{in}$	400	V
	Reference voltage	$V_{ref}$	48	V
	Inductance	L	3	mH
	Capacitance	C	4.7	$\mathrm{\mu }$F
	Load	R	3	$\mathrm{\Omega }$
Ramp Input	Upper voltage	$V_U$	8	V
	Low voltage	$V_L$	3	V
	Period	T	100	$\mathrm{\mu }$s
$PID$ controller	Proportional coefficient	P	0.1
	Integral coefficient	I	1200	s−1
	Derivative coefficient	D	0	s
Anticontrol of chaos controller	Amplitude of the rectified sinusoidal wave	c	10	V
	Pulsation of the rectified sinusoidal wave	$\sigma$	50	rad/V

summarizes the main specifications of this application.

Despite the continuous advances in control theory, the PID controller is still the most popular control technique employed in feedback control for regulating the output voltage of Buck converters. The standard structure of the controller is as follows:

$$C_{PI}\left(s\right)=P+I·{\displaystyle \frac{1}{s}}+D·{\displaystyle \frac{N}{1+N\frac{1}{s}}}.$$

(1)

where P, I, D, and N are the proportional, the integral, the derivative, and the filter coefficients. The parameters of the converter are selected to achieve the desired output voltage.

$$u_{PID}\left(t\right)=P·\left(V_{out}\left(t\right)-V_{ref}\left(t\right)\right)+I·{\int }_0^t\left(V_{out}\left(t\right)-V_{ref}\left(t\right)\right)dt+D{\displaystyle \frac{d}{dt}}\left(V_{out}\left(t\right)-V_{ref}\left(t\right)\right).$$

(2)

The inductance current $i_L$ and the MOSFET current of this circuit are generally periodic at the switching frequency $1/T$ (f = 10 kHz), as shown in Figure 2. The simulations were performed with the SimScape toolbox of MATLAB R2020b Simulink and included the buck converter with its control strategy, the power losses, and thermal model. $i_L$ and MOSFET current increased from 15.25 A to 16.75 A when the MOSFET was in on-state. Consequently, the MOSFET mean current was 16 A, with a ripple of 1.5 A. If the MOSFET was in off-state, $i_L$ decreased, meanwhile the MOSFET current was zero.

Figure 3a shows the periodic output voltage $V_{out}$ with a 2.5 V ripple. Its spectrum, shown in Figure 3b, corresponds to the converter governed by the control law of Equation (2). The spectrum consists solely of the fundamental frequency, characterized by a sharp peak at $1/T$, with a magnitude of −25 dB, and its harmonics.

Now, let us introduce the controller with the following control law:

$$u\left(t\right)=u_{PID}\left(t\right)+c·sin\left[\sigma ·\left(V_{out}\left(t\right)-V_{ref}\left(t\right)\right)\right].$$

(3)

Starting from a regular (non-chaotic) system $\dot{x}$ = $f\left(x\right)$, numerous works have been reported on generating continuous time chaotic motion.

• The nonlinear feedback method [13] introduces a nonlinear perturbation $\dot{x}$ = $f\left(x\right)$ + $ϵ$·$h\left(x\right)$, where $ϵ$ is a small control gain and $h\left(x\right)$ is a nonlinear function which introduce chaos. Feedback methods include the nonlinear time delay feedback control method [63], the linear time delay feedback method, and piece-wise linear function feedback.
• The chaotic coupling [64] of a stable system $\dot{x}$ = $f\left(x\right)$ with a chaotic system $\dot{y}$ = $h\left(y\right)$ influences x through the coupling function $g\left(y\right)$, which introduces chaos. The new system is $\dot{x}$ = $f\left(x\right)$ + $g\left(y\right)$.
• Bifurcation parameter tuning introduces a bifurcation parameter $\mu$ into a system $\dot{x}$ = $f(x,\mu )$ and pushes it into the chaotic region with a small variation $\mu$ = $\mu$ + $\mathrm{\Delta }\mu$.
• A chaotic impulse can destabilize a stable system with discrete spikes $\dot{x}$ = $f\left(x\right)$ + ${\sum }_{k=1}^{\infty }$$\delta$$(t-kT)$·$u_k$, where $\delta (t-kT)$ is a Dirac impulse and $u_k$ a chaotic input.
• The noise-introduced chaos [22] system $\dot{x}$ = $f\left(x\right)$ + $\eta \left(t\right)$ adding randomness $\eta \left(t\right)$ (e.g., stochastic noise).

In our case, the nonlinear feedback h(x) is a sine function. This time, the controller (3) includes, in addition to PID, a nonlinear feedback controller, with a multiplication of the $V_{out}$ feedback, introducing the chaos voluntarily. The amplitude and frequency of the resulting control signal dictate the number of switching cycles of the MOSFET. The ramp voltage operates at a constant frequency, while the modulating signals vary (due to the sine), allowing different duty cycles within the ramp period, involving fast switching. Figure 4 shows the ramp wave and the chaos anticontrol feedback, implying controller switching (3). Figure 5 presents the simulation results for inductance current $i_L$ and the MOSFET current obtained with the controller (3). $i_L$ and the MOSFET currents varied irregularly between 15.6 A and 16.4 A. Consequently, the MOSFET mean current was 16 A, with a very small ripple of 0.8 A. The MOSFET switched much more frequently that in the previous case (when the converter operated under the control law of Equation (2)), but no longer periodically. This allowed maintaining a small ripple for the output voltage $V_{out}$.

The output voltage $V_{out}$ is now chaotic, with a 1.8 V ripple, as shown in Figure 6a. Therefore, the influence of the controller (3) on the ripple is not negligible. Figure 6b represents the power spectrum of $V_{out}$ with a peak of −46 dB magnitude at the switching frequency $1/T$.

The various frequencies in $V_{out}$ stem from its highly irregular waveform, caused by the intrinsic nonlinear dynamics. These dynamics are driven by the varying on and off durations of the MOSFET switch within each ramp period T. Generally, the power spectrum represents the frequency components at a height given by the peak amplitude of $V_{out}$ at different frequencies. The link between the ripple and power spectrum magnitude explains the decrease in the peak magnitude from −25 dB to −49 dB. Therefore, the anticontrol of chaos improved the spectral emissions by further reducing the spectral peaks. We observed that the spectrum was no longer composed of a single peak at the switching frequency $1/T$ (or its harmonics). Instead, numerous spectral lines appeared, with a continuous power spectrum characteristic of chaos. Naturally, the reduction in the maximum of the power spectrum was achieved with the presence of chaos, increasing the converter’s switching frequency. As a result, the output voltage $V_{out}$ exhibited improved frequency-domain (spectral) and time-domain (ripple) performance compared to the first case.

Figure 7 and Figure 8 show the periodic and chaotic output voltages $V_{out}$ with f = 20 kHz. The influence of the control law (3) and the switching frequency f reduced the ripple of $V_{out}$ by more than 96%, from 0.8 V to 0.025 V. The chaotification of the feedback decreased the power spectrum of $V_{out}$ to −79 dB, comparable with the −40 dB with a periodic behavior. A further increase in switching frequency at f = 50 kHz led to the same trend: the $V_{out}$ ripple was 0.15 V with a periodic behavior and 7.5 mV with a chaotic behavior. The maximum of the power spectrum was reduced from −60 dB to −98 dB, as shown in Figure 9 and Figure 10.

Table 2. Ripple and maximum of power spectrum results for the study cases.

Behavior	Controller	Switching Frequency	Ripple	Maximum of Power Spectrum
Stable 1T-period	PID	10 kHz	2.5 V	−25 dB
		20 kHz	0.8 V	−44 dB
		50 kHz	0.15 V	−60 dB
Chaotic behavior	Anticontrol of chaos + PID	10 kHz	1.8 V	−45 dB
		20 kHz	0.025 V	−79 dB
		50 kHz	0.015 V	−98 dB

summarizes the $V_{out}$ ripple and power spectrum of the output voltage, using the control laws of Equations (2) and (3) as feedback. The control law of Equation (2) led to a large ripple. Chaotifying the converter with the proposed control law of Equation (3) as feedback ensured a good ripple and caused a spectacular decrease in the power spectrum amplitude. Finally, Table 2 shows that the power contained in the peak harmonics of the output voltage decreased at different frequencies, f = 10 kHz, 20 kHz, and 50 kHz.

3. Power Loss Computation and Thermal Model

The conduction and switching losses of the MOSFET added to the power losses of the diode are the total power losses, as shown in Figure 1.

3.1. MOSFET and Diode Power Loss Computation

The MOSFET’s conduction power loss ($P_{Mcond}$) is calculated as the product of the drain-source current $I_{ds}$ flowing through the MOSFET during conduction and the drain-source voltage $U_{ds}$ across it at each time step, as $P_{Mcond}\left(t\right)=U_{ds}\left(t\right)·I_{ds}\left(t\right)$, where $I_{ds}\left(t\right)=f(U_{ds}\left(t\right),T_j\left(t\right))$ depends on the drain-source current $U_{ds}$ and the junction temperature $T_j$. In order to reproduce this characteristic $I_{ds}$–$U_{ds}$, the Shichman–Hodges model describes the off, linear, and saturation regions of the MOSFET using three distinct equations given below:

$$\left\{\begin{array}{c}{I}_{ds}=0,\mathrm{if}{U}_{gs}<U_{th}\hfill \\ I_{ds}=k·\left[\left(U_{gs}-U_{th}\right)U_{ds}-{\displaystyle \frac{U_{ds}^2}{2}}\right],\mathrm{if}0<U_{ds}<U_{gs}-U_{th}\hfill \\ I_{ds}={\displaystyle \frac{k}{2}}·{\left(U_{gs}-U_{th}\right)}^2(1+\lambda U_{ds}),\mathrm{if}{U}_{gs}-U_{th}<U_{ds}\hfill \end{array}\right.$$

(4)

where $U_{th}$ is the threshold voltage, $U_{gs}$ is the gate-source voltage, k is the transistor gain, and $\lambda$ is the channel length modulation. The drain current $I_{ds}$ of a MOSFET as a function of $U_{ds}$, $U_{gs}$, and $U_{th}$ depends on the MOSFET’s operation region and temperature. The fittype and fit MATLAB functions were used to identify the voltage $U_{ds}$ at two different junction temperatures, 25 °C and 150 °C using the current–voltage characteristics $I_{ds}$–$U_{ds}$. Based on Figure 11a, the following polynomial fitting function was obtained:

$$U_{ds}\left(I_{ds}\right)=a·{I_{ds}}^3+b·{I_{ds}}^2+c·I_{ds}+d,$$

(5)

where a = 2.44 ×${10}^{-5}$, b = −0.001024, c = 0.09757, d = −0.1043 for 25°C; and a = 6.636 × ${10}^{-5}$, b = −0.002202, c = 0.1729, d = −0.0759 for 150 °C. The values of the coefficients a, b, c, and d were calculated taking into account the effect of $U_{th}$, $U_{gs}$ and of temperature. The lookup table method was utilized to approximate both conduction and switching losses for the MOSFET and diode. A 2-D lookup table using junction temperature $T_j$ and drain-source current $I_{ds}$ as breakpoint inputs interpolates the drain-source voltage $U_{ds}$ for any given $I_{ds}$ and $T_j$ values, based on Equation (5). Then, the conduction power loss $P_{Mcond}$ is the product of $U_{ds}$ and $I_{ds}$. During a transition, a refined model of switching loss energy includes the gate drive effect and parasitic capacitances:

$$E_{sw}={\displaystyle \frac{1}{2}}{U}_{ds}{I}_{ds}(t_r+t_f)={\displaystyle \frac{1}{2}}{U}_{ds}{I}_{ds}\left({\displaystyle \frac{Q_g}{I_g}}+{\displaystyle \frac{Q_{gd}}{I_g}}\right)$$

(6)

where $t_r$ and $t_f$ are the rise and fall times, $Q_g$ (depending on $U_{gs}$) is the total gate and $Q_{gd}$ is Miller charges (depending mostly on $C_{gd}$ and $U_{ds}$), and $I_g$ is the gate drive current. A higher $I_g$, the ratio between the gate-source voltage and gate resistance, reduces switching losses. The gate resistance ($R_g$ includes internal and external resistance) affects switching losses by influencing the speed of the gate voltage transition. A larger $R_g$ causes slower switching, leading to increased power dissipation in the MOSFET rather than the gate resistor. Since switching losses occur during transitions, increasing $R_g$ increases the transition times and, therefore, switching losses. The impact of junction temperature on switching losses can be approximated by

$$E_{sw}\left(T_j\right)=E_{sw,25 °\mathrm{C}}\times (1+k_T(T_j-25 °\mathrm{C}))$$

(7)

where $k_T$ is the temperature coefficient of the switching losses. Thus, slower transitions and a higher resistance and junction temperature increase $E_{sw}$. The C2M0080120D datasheet provides the dependence of switching energy losses on temperature (showing significant variation in junction temperature at a drain-source current of 20 A and a drain-source voltage of 800 V), current (exhibiting substantial variation in drain-source current), and voltage (for drain-source voltage values of 600 V and 800 V). The lookup table interpolates these known values to estimate the switching energy losses at different data points.

Figure 11b presents the switching loss energy when the device turns-on and when the device turns-off. The fitting function for the datasheet points, as represented in the figure, is as follows:

$$E_{sw}\left(I_{ds}\right)=e·I_{ds}^2+f·I_{ds}+g,$$

(8)

where e = 0.6553, f = 8.452, and g = 75.04 for the on-state of the MOSFET; and e = 0.4597, f = −9.768, and g = 72.87 for the off-state of the MOSFET. The values of the coefficients were calculated taking into account the effect of the junction temperature, $R_g$ and of $U_{ds}$. Unfortunately, most datasheets only show typical values, at two different temperatures (25 °C and 150 °C), for the current–voltage characteristics $I_{ds}$–$U_{ds}$, the switching loss energies $E_{sw-on}$ and $E_{sw-off}$, and the diode characteristic $I_f$–$U_f$. Since the characteristics have a strong temperature, voltage, and current dependence, measuring them under actual use conditions is necessary. The lookup table interpolates these known values in order to generate the switching energy losses at different data points.

The switching loss energies $E_{sw}$ when the MOSFET turns on or off depend on $I_{ds}$, $U_{ds}$ and $T_j$. Based on Equation (8), a 3-D lookup table having $T_j$, $I_{ds}$, and $U_{ds}$ as inputs interpolates $E_{sw}$ at any $I_{ds}$, $U_{ds}$, and $T_j$. Then, the loss energies $E_{sw}$ are used to estimate switching power losses $P_{Msw}$ as the product of the loss energies and the switching frequency.

The conduction power loss of a diode is analogous to that of a MOSFET, calculated as the product of the forward saturation voltage $U_f$ and the forward saturation current $I_f$: $P_{Dcond}\left(t\right)=U_f\left(t\right)·I_f\left(t\right)$, where $U_f\left(t\right)=f(I_f\left(t\right),T_j\left(t\right))$. Figure 12 presents a comparison between the datasheet points of the diode characteristic and the fitted curve, achieved with the following polynomial fitting function:

$$I_f\left(U_f\right)=h·{U_f}^3+i·{U_f}^2+j·U_f+k,$$

(9)

where h = 0.4481, i = −1.187, j = −0.1057, and k = 0.6399 for 25 °C, and h = 0.3296, i = 0.708, j = −4.211, and k = 2.078 for 150 °C. In order to estimate the conduction power loss $P_{Dcond}$, a 2-D lookup table interpolates the forward saturation voltage $U_f$ (the output of 2-D lookup table) for any forward saturation current $I_f$ and junction temperature $T_j$ values (the breakpoint inputs of 2-D lookup table).

The diode contributes to the switching energy $E_{rr}$ due to the reverse recovery charge $Q_{rr}$ during the turning off of the MOSFET. In [36], the following relation is used for $Q_{rr}$:

$$Q_{rr}={I_{rr}}^2·{\displaystyle \frac{S+1}{2·\frac{d{i}_f}{dt}}},$$

(10)

where $I_{rr}$ is the peak reserve recovery current, S is the snappiness factor, and $d{i}_f/dt$ is the turn-off switching rate. The snappiness factor S is 4.928, calculated from the datasheet information as $Q_{rr}$(25 °C) = 152 nC and $d{i}_f$/$dt$ = 1950 A/$\mathrm{\mu }$s. In order to calculate the reverse recovery charge $Q_{rr}$ at $T_j$ = 125 °C, $d{i}_f$/dt is 1090 A/$\mathrm{\mu }$s as in [36], resulting in a value of 271.93 nC. $Q_{rr}$ depends on $T_j$, as follows:

$$Q_{rr}\left(T_j\right)=Q_{rr}(25 °\mathrm{C})+{\displaystyle \frac{Q_{\mathit{rr}}(125 °\mathrm{C})-Q_{\mathit{rr}}(25 °\mathrm{C})}{125 °\mathrm{C}-25 °\mathrm{C}}}·(T_j-25 °\mathrm{C}).$$

(11)

A 3-D lookup table, using $T_j$, the forward saturation current $I_f$, and the forward saturation voltage $U_f$ as breakpoint inputs, calculates $E_{rr}$ through interpolation (as the product of $Q_{rr}$ and the diode forward saturation voltage $U_f$). The diode’s switching power loss, $P_{rr}$, is then determined as the product of the loss energies $E_{rr}$ and the switching frequency f.

3.2. Thermal Model

The MOSFET junction temperature $T_j$ is estimated using a linear model given by $T_j\left(t\right)=Z_{th-jc}\left(t\right)·P_{out}\left(t\right)+T_a\left(t\right)$, where $Z_{th-jc}$ is the thermal impedance, $T_a\left(t\right)$ is the ambient temperature and $P_{out}$ represents the total power loss, which is the sum of all power losses ($P_{Mcond}$, $P_{Msw}$, $P_{Dcond}$ and $P_{rr}$). The thermal impedance $Z_{th-jc}$ is graphically provided in the datasheet of SiC C2M0080120D MOSFET (Figure 13a). By implementing curve-fitting identification of $Z_{th-jc}$, the Foster thermal network (a resistor and capacitor thermal network as shown in Figure 13b) is derived. The parameters of the Foster model are $R_1$ = 0.2525 K/W, $R_2$ = 0.18024 K/W, $R_3$ = 0.0342 K/W, $R_4$ = 0.1976 K/W, $C_1$ = 0.42068 Ws/K, $C_2$ = 0.05191 Ws/K, $C_3$ = 0.001285 Ws/K, and $C_4$ = 0.006952 Ws/K. The total power losses $P_{out}$ are processed through the Foster network, resulting in the junction temperature $T_j$.

Figure 14a illustrates a stable 1T limit cycle for the junction temperature $T_j$ using the control laws of Equation (2) as feedback with a switching frequency f = 10 kHz. $T_j$ has a periodic waveform with variations from 64.9 °C to 65.11 °C. Therefore, the mean junction temperature was near to $T_{jm1}$ = 65.005 °C, and the junction temperature variation was $\mathrm{\Delta }{T}_{j1}$ = 0.21 °C. Anticontrol of the chaos controller (3) forced a chaotic behavior for the junction temperature $T_j$, as in Figure 14b. The mean junction temperature was near to $T_{jm2}$ = 65.21 °C with variations from 64.78 °C to 65.65 °C; meanwhile, the variation in temperature was $\mathrm{\Delta }{T}_{j2}$ = 0.87 °C. The stable and chaotic behaviors of junction temperature $T_j$ at others frequencies f = 20 kHz and 50 kHz are presented on Figure 15 and Figure 16 with the following results: $T_{jm3}$ = 67.26 °C and $\mathrm{\Delta }{T}_{j3}$ = 0.115 °C are depicted from Figure 15a for a stable behavior of $T_j$ and a switching frequency f of 20 kHz; at the same switching frequency, $T_{jm4}$ = 63.25 °C and $\mathrm{\Delta }{T}_{j4}$ = 0.6 °C for the chaotic behavior of the junction temperature (Figure 15b); at the switching frequency f = 50 kHz, Figure 16a shows a periodic waveform of temperature $T_j$ with $T_{jm5}$ = 67.865 °C and $\mathrm{\Delta }{T}_{j5}$ = 0.05 °C; Figure 16b shows $T_{jm6}$ = 58.91 °C and $\mathrm{\Delta }{T}_{j6}$ = 0.3 °C for a chaotic behavior of $T_j$.

Figure 14, Figure 15 and Figure 16 show how different controllers of the Buck converter (at different frequencies) impacted the junction temperature evolutions (the stable period-1T and chaotic behaviors), however with an insignificant impact on the mean junction temperatures and their variations. This is explained by the presence of the same mean current as for the on-state MOSFET.

Figure 17 shows the distribution of power losses among the semiconductor MOSFET for periodic and chaotic operating points at different switching frequencies. MOSFETs incur losses every time they switch, so a higher switching frequency leads directly to higher losses. In this way, a higher switching frequency causes higher MOSFET and diode switching losses $P_{Msw}$, $P_{Dsw}$ (represented in blue and yellow bars). Even with the MOSFET switching only one time on the T period with controller (2) and many times with controller (3), the MOSFET and diode conduction losses $P_{Mcond}$, $P_{Dcond}$ were nearly the same in all cases: they were not affected by the frequency or dynamical behaviors (periodic or chaotic), depending on the duty cycle. A very slight influence on the power values can be observed with the transition from the periodic to the chaotic regime (represented in red and green bars).

4. Remaining Life Estimation

A thermal cycle counting algorithm was applied to the junction temperature in order to predict the remaining life of the power MOSFET. The most widely used algorithm is rainflow counting: it converts the time series of the junction temperature into a number of cycles, thereby facilitating lifetime prediction. In Figure 18a, the rainflow histogram presents a value of $N_{c1}$ thermal cycles of 3000 × ${10}^{+5}$ due to the $T_j$ periodicity. However, if the time series of the junction temperature is irregular or chaotic, the result of the rainflow counting algorithm is a set of organized cycles $N_{c2}$ with a maximum of 120 × ${10}^5$, as in Figure 18b.

Figure 19 and Figure 20 present the thermal cycles of the stable and chaotic behaviors of junction temperature $T_j$ at other frequencies f = 20 kHz and 50 kHz.

These results were used to derive the MOSFET accumulated fatigue Q using the Miner’s rule. This is expressed as

$$Q=\sum _{i=1}^n{\displaystyle \frac{N_c}{N_f}}.$$

(12)

where $N_c$ represents the number of cycles calculated using the rainflow counting algorithm, and $N_f$ is the number of cycles to failure. For the estimation of the device failure cycles, the Coffin–Manson equation was employed. It can be written as

$$N_f=A·\mathrm{\Delta }{T_j}^{\delta }·e^{E_a/\left(k{T}_{jm}\right)},$$

(13)

where $E_a$ is the activation energy, A and $\delta$ are experimental coefficients, and k is the Boltzmann constant (8.617 × 10⁻⁵ eV/K).

An accelerated power cycling test was designed and experimentally executed to collect failure data. In a power cycling test, the device underwent repeated heating by conducting a predetermined current during the on-state, followed by a cooling period in the off-state, as illustrated in Figure 21a. Figure 21b includes a load current source, a measurement current source, and a gate voltage source. The device-heating load current was on for the ton duration and off during the cooling time toff. The experimental test involved long cycle times, where the MOSFET was switched on for 4 s and off for 12 s. A constant Ids was applied to maintain the junction temperature at 125 °C. A 100 mA measurement current was applied continuously to obtain the junction temperature. The gate voltage source controlled the device under test: 20 V were constantly applied to the gate. The heating and cooling process simulated real-world operational conditions, such as those found in electric vehicles. The periods of acceleration were followed by steady-speed cruising. The continuous cycles of heating and cooling induced the thermal stress that arises at the interface between materials with different coefficients of thermal expansion. For instance, stress can develop between silicon and aluminum layers due to their differing expansion behaviors under temperature variations, thus causing degradation. Consequently, power cycling imposes simultaneous electrical, thermal, and mechanical stress on the semiconductor die.

The Coffin–Manson model considers the lifetime estimation and relies solely on $\mathrm{\Delta }{T}_j$ and $T_j$ means, which are the main stress factors of the power device. The Coffin–Manson–Arrhenius, Lorris–Landzberg, Bayerer, Simplified Bayerer, CIPS08, and Schenermann models take into account electrical stress as dependent on the frequency f, on-time of one cycle $t_{on}$, voltage V (sometimes included in the constant coefficient), current per bond feet I, bond wire diameter D, and wire bond aspect ratio $ar$ of power cycle testing. It was observed that the device performance degradation varied from one unit to another due to minor discrepancies in manufacturing parameters. To evaluate the qualitative behavior of the C2M0080120D MOSFET, multiple devices were subjected to identical power cycling conditions.

However, due to inherent variations in the MOSFET’s characteristics $I_{ds}$–$U_{ds}$ (Figure 22), differences in the mean and swing junction temperatures were observed across the tested devices. The junction temperatures recorded during three experimental tests were as follows: for the first test, $T_{jmt1}$ = 127 °C, $\mathrm{\Delta }{T}_{jt1}$ = 16 °C; the temperatures of the second test were $T_{jmt2}$ = 126.5 °C, $\mathrm{\Delta }{T}_{jt2}$ = 14.5 °C; and the last test’s temperatures were $T_{jmt3}$ = 114.2 °C, $\mathrm{\Delta }{T}_{jt3}$ = 12.5 °C. Failure of the device under test was recorded after $N_{ft1}$ = 8640 cycles, $N_{ft2}$ = 12,270 cycles, and $N_{ft3}$ = 25,400 cycles.

These results were used to derive the experimental coefficients A and $\delta$, as well as the activation energy $E_a$. The logarithm function was applied to the Coffin–Manson equation, as in [52], using only three sets of experimental test data. Consequently, the development $\delta$ can be represented by

$$\delta ={\displaystyle \frac{\left(\frac{1}{T_{jmt1}}-\frac{1}{T_{jmt2}}\right)·log\frac{N_{ft2}}{N_{ft3}}-\left(\frac{1}{T_{jmt2}}-\frac{1}{T_{jmt3}}\right)·log\frac{N_{ft1}}{N_{ft2}}}{\left(\frac{1}{T_{jmt1}}-\frac{1}{T_{jmt2}}\right)·log\frac{\mathrm{\Delta }{T}_{jt2}}{\mathrm{\Delta }{T}_{jt3}}-\left(\frac{1}{T_{jmt2}}-\frac{1}{T_{jmt3}}\right)·log\frac{\mathrm{\Delta }{T}_{jt1}}{\mathrm{\Delta }{T}_{jt2}}}}.$$

(14)

Hence, the thermal activation energy can be calculated from

$$E_a=k·{\displaystyle \frac{log\frac{N_{ft1}}{N_{ft2}}-\delta ·log\frac{\mathrm{\Delta }{T}_{jt1}}{\mathrm{\Delta }{T}_{jt2}}}{\frac{1}{T_{jmt1}}-\frac{1}{T_{jmt2}}}}.$$

(15)

The last coefficient can be written as

$$A={\displaystyle \frac{N_{ft1}}{\mathrm{\Delta }{T_{jt1}}^{\delta }·e^{E_a/\left(k{T}_{jmt1}\right)}}}.$$

(16)

According to relations (14)–(16), the following numerical values were obtained: $\delta$ = −4.4887, $E_a$ = 0.0667, and A = 2.8823 ×${10}^{+8}$ for a C2M0080120D MOSFET, as in [52]. With these coefficients and according to relation (13), the number of cycles to failure was for the stable period-1T behavior $N_{f1}$ = 3.9064 × ${10}^{12}$ cycles calculated for $T_{jm1}$ = 65.05 °C and a extremely small $\mathrm{\Delta }{T}_{j1}$ = 0.21 °C; for the chaotic behavior, according to $T_{jm2}$ = 65.21 °C and $\mathrm{\Delta }{T}_{j2}$ = 0.87 °C, $N_{f2}$ was found to be 1.2548 × ${10}^9$. The degradation in the C2M0080120D MOSFET device at other frequencies is summed up in

Table 3. Accumulated fatigue results for the study cases.

Behavior	Switching Frequency	Mean of ${\mathit{T}}_{\mathit{j}}$	Variation $\mathit{\Delta }{\mathit{T}}_{\mathit{j}}$	Number of Cycles ${\mathit{N}}_{\mathit{f}}$	Accumulated Fatigue
Periodic behavior	10 kHz	65.005 °C	0.21 °C	3.9064 × 1012	7.68 × 10−3%
	20 kHz	67.26 °C	0.115 °C	1.3996 × 1013	4.28 × 10−3%
	50 kHz	67.865 °C	0.05 °C	1.9315 × 1015	6.99 × 10−5%
Chaotic behavior	10 kHz	65.21 °C	0.87 °C	1.2548  × 109	4.78 × 10−1%
	20 kHz	63.25 °C	0.6 °C	2.8520 × 1010	4.2 × ${10}^{-2}$%
	50 kHz	58.91 °C	0.3 °C	6.6014 × ${10}^{11}$	2.18 × ${10}^{-3}$%

.

The accumulated fatigue was insignificant for a stable period of the junction temperature $T_j$, indicating a small impact on the remaining life of the MOSFET. The power losses were 10 times higher in the chaotic case than in the periodic regime. This power ratio resulted in a temperature variation six times higher in the chaotic case; it also generated a fatigue accumulation 100 times greater. However, only a small amount of damage was observed when the anticontrol of chaos feedback was applied. The repercussions of the chaotic temperature were small for the MOSFET thermal stress and reliability performance. The accumulated fatigue results show that the low- and high-frequency thermal cycles contributed in the same way to the aging of the Buck converter’s semiconductor. Thus, this leads to the conclusion that using anticontrol of chaos produced a very low accumulated fatigue effect of the Buck converter’s semiconductor. The accumulated fatigue results show that the low- and high-frequency thermal cycles contributed in the same way to the aging of the Buck converter’s semiconductor.

5. Conclusions

The target of this paper was to investigate the effects of the voluntary introduction of chaos into a Buck converter on the remaining life of power electronic switching components and their thermal stress. Indeed, a combination of anticontrol of chaos feedback with a standard PID controller introduced chaos into the circuit. The resulting effects involved complex dynamical behaviors, with a multitude of opportunities for special properties: maintaining a small ripple of the output voltage or even reducing it, and keeping a small swing current amplitude of the MOSFET and decreasing spectral emissions. Indeed, applying chaos anticontrol to switch-mode power supplies improved the performance, both in the frequency-domain and in the time-domaine. The results indicate that chaos had no impact on the mean junction temperature, but the temperature variation was six times higher in the chaotic case. Then, counting the thermal stress cycles allowed highlighting that the accumulated fatigue showed an insignificant degradation of the MOSFET lifetime with anticontrol of chaos feedback (in comparison to a standard controller), despite the fast switching of the MOSFET. Thus, this leads to the conclusion that using anticontrol of chaos produced a slight degradation in the remaining life of the semiconductor. Finally, future research demands, opportunities, and perspectives are identified here: to study the influence of anti-control of chaos on the reliability of capacitor and passive components, to integrate non-constant operating conditions such as ambient temperature. Online monitoring, along with prognostics and health management (PHM), are critical areas that require thorough analysis and development.