1. Introduction
Graphene (G) has an absolute advantage in the preparation of high-frequency devices due to its ultra-high electron mobility, but the intrinsic graphene has no band gap, which limits its application in logic devices [
1,
2]. The transition metal chalcogenides (TMDs) represented by molybdenum disulfide (MoS
2) make up for the defect of zero band gap of graphene. The field-effect transistors (FETs) prepared by them show superior switching modulation characteristics, so they have great advantages in low-power devices [
3,
4,
5,
6,
7]. However, the intrinsic carrier mobility of two-dimensional TMDs is usually low, much lower than the electron mobility in crystalline silicon [
8,
9], which greatly limits their application in semiconductor electronic devices. Of course, there are more and more methods to improve the carrier mobility of TMDs.
As another important discovery after graphene and transition metal sulfide, black phosphorus (BP), as the only other known monotypic van der Waals crystal, has broad application prospects in nano optoelectronic devices [
10,
11,
12,
13,
14,
15,
16,
17,
18,
19]. In 2014, a FET with nanometer thickness two-dimensional BP as channel material was successfully prepared by the research group of Zhang et al. [
20]. The test results show that the on/off current ratio of the BP transistor could reach 10
5 when the thickness of the two-dimensional BP film is less than 7.5 nm, and the highest electron mobility maybe reaches ~1000 cm
2/Vs when the thickness of BP film is greater than 10 nm, which is somewhat better than that of molybdenum disulfide (~200 cm
2/Vs). BP has become another important member of the two-dimensional nanomaterial family following graphene and molybdenum disulfide [
21,
22,
23,
24,
25]. In the research of BP materials and their devices, the band structure of BP crystals was found to change with the thickness of the material itself, i.e., the band gap decreases with increasing thickness [
22,
26]. Saptarshi et al. derived the band gap of BP samples with different layers (less than 30 layers) [
27] by computer theoretical simulation. By measuring the transport characteristics of BP FETs with different thicknesses, they confirmed this conclusion experimentally. Liang et al. report the evolution of the band gap calculated by different methods from 1 layer to ∞ layers, and show the sheet conductivity as a function of gate voltage for devices with different thicknesses (10 nm, 8 nm, and 5 nm) [
22]. However, for BP thickness larger than 30 layers or higher (over 20 nm), the precise effect of material thickness on device characteristics or functional relationship between electrical characteristics (output characteristics, transfer characteristics, mobility, etc.) and thickness have not been systematically studied.
Here, the effects of BP materials with thicknesses ranging from ~10 to ~100 layers on the transport properties of BP-FETs were precisely investigated. Five BP-FET devices with different BP thicknesses (~50 nm, ~40 nm, ~30 nm, ~20 nm, and ~6 nm) were prepared by mechanical exfoliation technology, and their electrical properties were tested in detail. The influence of BP material thickness on device output and transfer characteristics were systematically analyzed. Using plasma etching technology to etch the material thickness of 50 nm to 30 nm again confirmed the effect of thickness on device performance.
3. Results
Figure 2a shows the output characteristics (
Ids-
Vds) of about 50 nm, 40 nm, 30 nm, and 20 nm BP FET devices. The source drain voltage scanning range is from −100 mV to 100 mV, and the gate voltage (
Vg) is 0 V.
Figure 2b shows the
Ids-
Vds characteristics of about 6 nm BP FET, but the
Vds scanning range is from −50 mV to 50 mV. This range is mainly due to the thin material and the need to prevent the device from being damaged. The good linear relationship between
Ids and
Vds (all fit lines are very good straight lines) proves that a good contact is formed between the BP and the electrode. It can be clearly seen that at a fixed
Vds, the value of
Ids increases gradually with the increase of the material thickness. Namely, the greater the thickness of the material, the greater the
Ids. However, the
Ids changes only a few times for a thickness changing from 20 nm to 50 nm, but from 6 nm to 20 nm, the
Ids does change by several orders of magnitude.
Figure 2c shows the exact change rule of
Ids with BP material thickness under different
Vds. Interestingly, the laws of several curves are completely consistent, so it is certain that there is a certain relationship between the
Ids of the BP FET device and the BP thickness. Using 1stOpt (First Optimization, 7D-Soft High Technology Inc.), a simulation software that can easily fit the experimental data, we fitted the experimental data (log
Ids) shown in
Figure 2c with Boltzmann model, and the fitted curves can be obtained. The change rule of log
Ids and BP thickness
l can be described by the following semi empirical formula given by software,
where
A,
B,
lo, and
C are fitting coefficients, their values have very weak changes with BP thickness, as shown in
Table 1. The fitting results show that the experimental data of log
Ids-
l in
Figure 2c fitted by Formula (1) and the coefficients in
Table 1 give an
Radj2 of over 0.998, which reflects a very perfect fit (usually
Radj2 = 1 indicates complete agreement and
Radj2 = 0 indicates complete failure) [
29]. That is, Equation (1) can completely describe log
Ids-
l. As the material thickness increases,
A and
C slightly increase, while
B and
lo slightly decrease. However, only the coefficient
A exhibits a pattern of increasing with the thickness of the material, for
B,
C, and
lo, the influence of thickness can be almost ignored when the BP thickness is greater than about 20 nm. For example, when BP thickness from 20 nm to 50 nm,
B simply fluctuates between −3.990 and −3.989;
lo also fluctuates within a range (shown in
Table 1 and
Figure 3b,c). Next, we analyze the impact of
l on
Ids in detail.
Figure 2d shows that the kink point of the slope of the fitting curve (the maximum value of the first order differential) appears near
lo. The value of
lo is 21.7 nm. Above
lo, the slope of the curve starts to decrease slowly, but gradually becomes faster. When
l reaches a certain value
lright, the speed of the slope decreases reaches the fastest. Thereafter, the speed of decrease gradually becomes slower. If
l continues to increase, when it approaches 50 nm, the speed of the slope decrease of the curve reaches almost 0, and then the fitting curve gradually flattens, which means that the degree of influence of thickness on device characteristics can be ignored.
Figure 2e again proves the above conclusion that when the
l is greater than 21.7 nm, the minimum value of the slope of the dlog
Ids/d
l-
l occurs at the BP thickness of 26.7 nm (negative, but its absolute value is the maximum). Namely,
lright is 26.7 nm. That is, when the thickness is greater than 26.7 nm, the effect of thickness on device characteristics gradually starts to become less pronounced.
Below
lo, although we did not measure the transport characteristics of FETs with BP thickness up to 6 nm, it seems possible to predict from
Figure 2d that when the channel material thickness is less than
lleft (kink point), the effect of
l on
Ids seems to become progressively less pronounced as the
l decreases. The region where the degree of the effect of thickness on
Ids is most pronounced should be around
lleft (16.3 nm) because the change of slope of the curve is the fastest near
lleft, as shown in
Figure 2e. From 6 nm to 16.3 nm, the speed of the slope increse of log
Ids-
l is gradually increasing with the increase of the thickness, reaching the maximum at 16.3 nm, after which it gradually becomes smaller and is 0 at 21.7 nm.
The extent of the effect of BP thickness on device performance at different thickness ranges can be obtained from
Figure 2e. The speed of slope varies from the maximum (at
lleft) to the minimum (at
lright), but the thickness spans only 10.4 nm. From 6 nm to 16.3 nm, the speed varies from a non-zero value to a maximum value, although the span of
l is only 10.3 nm, but the span of speed is only half of the interval of 16.3 nm to 26.7 nm. From 26.7 nm to 50 nm, speed varies from the minimum to 0, where
l spans 23.3 nm and speed spans half of the interval 16.3 nm to 26.7 nm. Alternatively, when the thickness of the BP material is between 16.3 and 26.7 nm, the BP thickness should have a significant effect on device performance, even greater than the effect of thickness on device characteristics when the thickness is between 20 nm and 6 nm (or 26.7–50 nm), although the thickness of the material also has a significant effect on device characteristics when the thickness of the material is thin (20 nm to 6 nm). Of course,
Figure 2e shows more clearly that when the thickness reaches or exceeds 50 nm, the
l has almost no effect on
Ids. In addition, when the thickness is between 6 nm and 7 nm, it seems that the degree of influence of thin layer thickness on the output characteristics of the device is changed more significantly, shown in
Figure 2f. According to previous literature reports [
30,
31], we believe that other factors may be involved in influencing the performance of device with thin BP thickness. By linear fitting
Figure 2a,b, from their slopes the total resistance of devices with BP thickness of about 50 nm, 40 nm, and 30 nm are extracted as about 1.52 kΩ, 2.18 kΩ, and 5.4 kΩ, respectively. It seems to decrease linearly with the increase of thickness. However, the resistance of about 20 nm and 6 nm BP devices are nonlinear increased to 420.2 kΩ and 12,733.9 kΩ. That is, when the device material thickness changes from ~30 nm to ~20 nm, the resistance of the device increases by a factor of nearly 78; while the material thickness changes from ~20 nm to ~6 nm thickness, its resistance increases by a factor of 30. This corroborates the results in
Figure 2 that the thickness of the BP material is more influential on the device performance when the thickness range is between ~16.3 nm and ~26.7 nm. The specific relationship between the resistance of devices and the thickness of channel materials is shown in
Figure 3a. This super nonlinearity may be due to the fact that when the material thickness is reduced to a certain value, the band gap of the material increases, resulting in a sudden increase in resistance. In addition, using 1stOpt we fitted the log
R vs. BP thickness
l in
Figure 3a, and found that the function of the relationship between fitted log
R and
l is also the above Formula (1), and the fitting parameters
A,
B,
C, and
lo are 3.22190, 3.987341, 4.34556, and 21.79109, respectively. The coefficients are almost identical to those in
Table 1, except for the
A coefficient in Equation (1). However, after a closer look at Equation (1), it is found that the coefficient
A is a constant determined independent of thickness. Therefore, both log
Ids and log
R vs.
l should be mainly determined by the second term on the right side of Equation (1), so the Equation (1) can also describe the relationship between log
R and
l. From this experiment, we can predict that when the band gap starts to change with the thickness, the corresponding value of thickness should be
lo, ~21.7 nm. Namely, when the BP thickness is less than 21.7 nm, the energy band of BP material will increase significantly with the thickness thinning, and when the BP thickness is greater than it, the modulation relationship between the energy band of BP material and the thickness will gradually weaken. This conclusion is similar to that of
Figure 2d. The exact relationship of the four fitted coefficients in
Table 1 with thickness is shown in
Figure 3b and c, it seems to confirm that only the
A coefficient is determined with thickness, while the other coefficients vary little or not at large material thicknesses (for ~20 nm).
Figure 4 shows the transfer characteristic (
Ids-
Vg) curves of BP FET devices with thickness of about 50 nm, 40 nm, 30 nm, 20 nm, and 6 nm, respectively. The
Vds is 100 mV. It is obvious that the larger the thickness, the less the applied electric field can regulate the device. For the device with BP of ~50 nm, the current only changes from a maximum value of 75 mA to a minimum value of 60 mA at −40 V to 40 V electric control voltage, a change of 1.25 times. The same is true for a 40 nm thick device. This weak dependence on the gate voltage (
Vgs) due to strong Thomas–Fermi charge screening in thick BP flakes. In addition, if the FET device has a thick BP material (greater than 20 nm), no
Ioff is seen in the measured voltage range, namely, the device material exhibits a very clear p-type because no minimum value of current (flatband condition voltage,
VFB) is seen [
32]. In the inset of
Figure 4b, we found that the dominant carrier type in BP will change from naturally p-type to n-doping in FET with thinner BP flakes at
VFB. The
VFB are about −4.5 V and 2.2 V for FET with the BP thicknesses of 6 nm and 20 nm, respectively. It seems that for natural p-type BP materials, the greater the thickness, the greater the
VFB, i.e., the greater the
Vg required to shift the polar type of the material. Furthermore, the
Ioff was observed in devices with 6 nm and 20 nm thickness material, the
Ion/
Ioff is ~10
3.
At different gate voltages (
Vg) the
Ids-
Vds curves of BP FET devices with about 50 nm, 40 nm, 30 nm 20 nm, and 6 nm BP are shown in
Figure 5, where the source drain voltage (
Vds) scanning range is from −100 mV to 100 mV. It can be seen that the
Ids of the BP-FET device is directly related to the thickness of the material. The thicker the material is, the greater the source drain current under the same
Vg. However, the thicker the material is, the weaker the modulation effect of the electric field will be, which can be seen from
Figure 5a, at different
Vg, several curves basically overlap. In addition, when the thickness of the material is reduced to about 20 nm, under the
Vg modulation of 40 V, the source leakage current has been reduced by 5000 times compared to BP-FET with the 30 nm material.
However, the modulation effect of the electric field is enhanced, and the on/off current ratio (the ratio of the on-state current to the off-state current) of the device reaches ~10
3. In addition, from the transfer characteristic curve, it can be seen that when the negative gate voltage is greater, its conductivity is better, so majority carriers are holes. When the BP thickness is about 20 nm and 6 nm, the transfer characteristic curve of the device indicates that the type of carriers involved in conducting in the BP crystal has shown a certain bipolar type (as shown in the
Figure 4b), which is similar to the BP FET of the thin layer materials (below 10 nm) [
8]. From the inset of
Figure 4b, the thinner the material is, the smaller the modulation voltage required for the carrier polar transition. According to the transfer characteristic curve of FET, the carrier mobility can be calculated according to the following formula [
31].
where
L/
W is the ratio of length and width of the device channel. In our prepared BP-FET, the ratio is 1.2,
Ci =
ɛoɛi/
d is the capacitance per unit area,
ɛo = 8.854 × 10
−12 fm
−1 is the dielectric constant in vacuum,
ɛi = 3.9 is the relative dielectric constant of silicon dioxide, and
d is the thickness of the insulating layer, that is, the thickness of silicon dioxide. It is 285 nm. We can calculate that the values of the device mobility with BP thickness of about 50 nm, 40 nm, 30 nm, 20 nm, and 6 nm are about 336.4 cm
2/Vs, 252.5 cm
2/Vs, 214.4 cm
2/Vs, 187.5 cm
2/Vs, and 52.5 cm
2/Vs. The exact relationship between mobility and BP thickness is shown in
Figure 3d. The carrier mobility increases with the increase of material thickness, and from 20 nm to 50 nm, it can be approximately regarded as proportional to the thickness. However, the most significant increase in device mobility was observed when the BP thickness is increased from 6 nm to 20 nm. The reason for the rapid increase can also be attributed to the fact that when the BP thickness is less than 21.7 nm, the band gap of BP is modulated by the thickness, thus affecting the mobility.
In order to verify the above conclusions, we used plasma etching technology to etch the BP device with a thickness of 50 nm. Under specific power and current, after controlling the etching rate for 30 s, a BP-FET with a thickness of about 30 nm was obtained.
Figure 6a shows its output characteristics. In the three
Ids-
Vg curves, the source drain voltage scanning range is from −100 mV to 100 mV, and the gate voltages are set at 30 V, 0 V, and −30 V, respectively.
Figure 6b shows the transfer characteristics. The
Vg scanning range is from −30 V to 30 V, and the source drain voltage is set at 100 mV. Compared with the output characteristics of the BP FET in
Figure 5c, the current of the etched BP FET is close to that of the 30 nm BP FET and greatly reduced compared with that of the 50 nm BP FET, which confirms that in the electrical characteristics of the BP FET is directly related to the BP thickness. Under the same
Vg, the greater the BP thickness, the greater the source drain current. However, the
I-
V curve in
Figure 6a has kink points. The reason for this phenomenon is that the plasma etching method often introduces different levels of structural damage and impurity elements, causing damage to the lattice structure of the sample materials. From the transfer characteristics in
Figure 6b, it can be concluded that the thickness of the material will affect the modulation of the electric field. By comparing the transfer characteristic curve of the BP FET with 30 nm BP in
Figure 4a, it can be seen that the electric field modulation effect is more obvious in the device after plasma etching. Since the device after plasma etching has better conductivity when the negative gate voltage is higher, most carriers are holes, which is consistent with the above conclusion.