Enhanced RF Power Conversion for Sensor Networks and Embedded Sensors

Abstract

Wireless power transfer using beamforming technology has recently gained significant attention for sensor networks and embedded systems. This technology uses array antennas and mid-range RF power (15–20 dBm) rectifiers for efficient power delivery to sensors. Despite its potential, research on mid-range RF power CMOS rectifiers remains limited. Addressing this gap, we propose a high-efficiency pMOS-based rectifier employing a body-biasing technique—a proven method for enhancing device performance—specifically designed for wideband and mid-range RF power RF applications. Conventional rectifiers often depend on precise input impedance matching to achieve high power conversion efficiency (PCE), which restricts bandwidth and limits practicality in dynamic environments. To overcome these challenges, the proposed design integrates a modified matching network, combined with dynamic body-biasing, which lowers the pMOS threshold voltage and minimizes power losses. Simulations reveal a peak PCE of 60.5%, with efficiency exceeding 50% across a broad frequency range up to 2.5 GHz—significantly outperforming traditional designs. Unlike conventional impedance-matching solutions, this rectifier maintains robust performance under input mismatches, making it well-suited for beamforming-based WPT systems. This study highlights the potential of integrating body-biasing with advanced matching networks for efficient wideband rectifiers.

1. Introduction

Wideband rectifiers are essential for high-frequency power applications, including wireless power transfer, the Internet of Things (IoT), and radio frequency (RF) energy harvesting [1,2,3]. For optimal performance, these rectifiers must achieve high power conversion efficiency (PCE) over a broad frequency range while managing significant input power ($P_{in}$). However, conventional rectifier designs often rely on precise impedance matching [4,5], which limits bandwidth and reduces efficiency in dynamic environments. This constraint makes them less suitable for emerging mid-range RF power and wideband applications.

In addition, dual-band rectifier topologies have also been of interest in the sense that they enable energy harvesting from multiple frequency bands with higher overall power conversion efficiency and compact circuit footprint [6]. Continuing with the enhancements, this paper introduces a new CMOS rectifier which incorporates a reconfigurable impedance matching network along with body-biasing techniques to enhance efficiency and widen the operating frequency range. While extensive research has focused on low-power CMOS rectifiers [7,8,9], the development of mid-range RF power CMOS rectifiers remains relatively unexplored.

Much research has focused on improving the efficiency of CMOS rectifiers for wireless power transfer (WPT) applications through the minimization of threshold voltage losses and impedance mismatch. Ref. [10] introduced a CMOS rectifier with an adaptive body-biasing method to dynamically reduce the transistor threshold voltage (Vth) when the PMOS is ON, thereby increasing the conduction current and power conversion efficiency (PCE). The device exhibited a peak PCE of 78.2% at −27.5 dBm input power, with improved efficiency at low powers. Its operation, however, degraded at high input powers due to leakage current through parasitic diodes, requiring additional mechanisms to inhibit reverse current flow.

The authors of [5] presented a self-tuning impedance matching (STIM) technique to combat impedance variations in rectifiers. Their rectifier, which was conceived at 2.4 GHz, reached more than 50% PCE over an extended input power interval of 2.5–25.5 dBm, surpassing conventional designs. The main drawback was increased circuit complexity and additional components, which could cause insertion losses in practice. Ref. [11] introduced a dynamic threshold cancellation (DTC) technique, integrating a negative voltage converter and an active rectifier to reduce threshold voltage losses and inhibit reverse leakage currents. Their CMOS rectifier, fabricated in a 130 nm process, achieved a great PCE of 90% at 0.45 V input voltage and is suitable for ultra-low-power applications. The design was optimized, however, for low-frequency operation (800 Hz–51.2 kHz), limiting its application to high-frequency RF energy harvesting.

These works emphasize the importance of body-biasing, adaptive impedance matching, and dynamic threshold cancellation for CMOS rectifier performance improvement. The existing solutions, however, continue to experience problems such as efficiency degradation at high powers, circuit complexity, and frequency limitations. To address this gap, this study proposes a high-efficiency pMOS-based rectifier utilizing a dynamic body-biasing technique to enhance conduction efficiency and minimize power losses. Unlike conventional impedance-matching approaches, the proposed design integrates a modified matching network that enables robust operation even under input mismatch conditions. Simulation results demonstrate a peak PCE of 60.5%, with efficiency exceeding 50% across a wide frequency range up to 2.5 GHz. These findings highlight the potential of body-biasing and advanced matching techniques for next-generation wideband rectifiers, particularly in beam-forming wireless power transfer systems.

2. Overview of the Proposed Method

This section explores the development of a modified matching and body-biasing CMOS rectifier utilizing pMOS transistors. Our earlier research focused on designing a wideband inductor-less nMOS native rectifier [12]. Even for the earlier research on an inductor-less nMOS native rectifier, the chip size active area was 0.44 mm², which is still considered large because of the inductor’s replacement with a capacitor. In CMOS technology, pMOS transistors are commonly used to emulate diode behavior, and their performance can be enhanced by supplying voltage to the body terminal. Traditionally, this voltage is supplied via the output terminal [13], which serves as the highest voltage node. In our other work [14], the body terminal of each pMOS transistor was connected to its respective drain terminal. The problem with [14] is that the inductance value needed is too large and will consume a huge proportion of the chip active area. All of the above works in CMOS technology suffers from bandwidth limitations, despite the increasing bandwidth demands of rectifiers in beamforming-based WPT systems.

To address this bandwidth issue, this study examines the impact of using an inductor as a transmission line to implement a modified matching technique, combined with the body-biasing approach [14], to design a wideband rectifier. This study has a considerable chip size, where even with using one inductor, this study’s chip active area is 0.48 mm² that is almost in similar size to the previous inductor-less work [12]. In addition, this study also managed to reduce the size of the inductor to 26% of the inductance value needed in [14] and to achieve the higher FoM of 198.587 with the 2.3 GHz range of wideband with a more than 50% PCE, which is wider and better. For comparison, three configurations are analyzed: the inductor-less nMOS native rectifier from the prior work (Case A), the pMOS rectifier with body-biasing via the output voltage (Case B), and the proposed design (Case C). These configurations are depicted in Figure 1a–c, while Figure 1d compares their power conversion efficiency (PCE). The results indicate that the proposed design reaches a peak PCE of 60.5% at 0.7 GHz and sustains over 50% efficiency up to 2.5 GHz.

3. Principle and Design Method

Figure 2 illustrates the impact of the transistor sizing on the reflection coefficient $\left|S_{11}\right|$. The proposed design (Case C) achieves a lower $\left|S_{11}\right|$ compared to Cases A and B across various W/L ratios, indicating better impedance matching. This improvement is attributed to the optimized matching network, which effectively reduces the input impedance variations and enhances the power transfer efficiency. In the RF rectifier design, achieving a lower $\left|S_{11}\right|$ is crucial for minimizing the power losses due to reflection, thereby improving the overall power conversion efficiency (PCE). Compared to traditional inductor-less designs, our modified matching approach provides a more stable impedance profile, leading to superior performance under varying input conditions. Figure 3 provides the relationship between transistor width and PCE for different rectifier topologies. The new design always offers a higher PCE for every ${\displaystyle \frac{W}{L}}$ ratio, with the best point where efficiency is the highest. This is due to the influence of the ${\displaystyle \frac{W}{L}}$ ratio on the transistor transconductance ($g_m$), which influences the conduction losses as well as the switching behavior. An increase in the ${\displaystyle \frac{W}{L}}$ ratio increases gm, decreasing Ron and enhancing the current conduction. However, at a certain stage, the oversized transistor contributes to higher parasitic capacitances, degrading high-frequency operation. The compromise proves the imperative of prudent transistor sizing in designing an RF rectifier. The outcome is in accordance with the previous literature on CMOS rectifiers that states that a tradeoff between the efficiency of conduction and parasitic loss is accountable for providing a high PCE.

In the proposed schematic shown in Figure 1c, transistors M1 and M2 are utilized for impedance matching, supporting the main rectifier structure formed by transistors M3 and M4 in a Dickson (voltage doubler) configuration, which serves the purpose of raising the voltage at the rectifier output. This setup is particularly beneficial in RF energy harvesting and wireless power transfer applications, as it allows the circuit to deliver a higher DC output voltage from the input RF signal. The operation of the voltage doubler relies on the alternative charging and discharging cycle of the transistors, where M3 is in conduction in the positive half-cycle to store charge, and M4 is in conduction in the negative half-cycle to transfer the stored charge to the output. Figure 4 also examines the impact of transistor sizing on the PCE by taking a close-up of M3 and M4, the core of the voltage doubler. The novel design (Case C) outperforms Cases A and B, demonstrating the efficacy of the body-biasing technique at improving the conduction efficiency. The body-biasing technique reduces the threshold voltage ($V_{th}$) of the transistors, reducing the power loss during rectification. As a result, the suggested rectifier achieves better efficiency for a wide variety of ${\displaystyle \frac{W}{L}}$ ratios. The trend here is consistent with the prior research on body-biasing for RF rectifiers, in which threshold voltage adjustment plays a significant role in PCE optimization.

This improvement is attributed to the effect of the ${\displaystyle \frac{W}{L}}$ ratio on the transistors’ transconductance ($g_m$). As the ${\displaystyle \frac{W}{L}}$ ratio increases, the on-resistance ($R_{on}$) in the saturation region, which is inversely proportional to $g_m$ ($R_{on}={\displaystyle \frac{1}{g_m}}$), decreases. A higher $g_m$ value leads to a lower $R_{on}$, enhancing the overall efficiency of the proposed design.

Figure 5 illustrates the PCE as a function of the input power at various load resistances. The new design continues to maintain the PCE above 50% over a broad range of input power with better performance compared to Cases A and B. At low input power, Case A exhibits competitive efficiency with reduced structural complexity. However, as the input power level rises, the advantage of the improved matching network and body-biasing technique in Case C is even clearer and allows it to be very efficient even under 20 dBm input power. This is a critical advantage for high-power RF energy harvesting systems, where rectifiers need to operate efficiently under various input levels. Compared with other CMOS rectifier circuits, our proposed solution has an improved figure of merit (FoM) through a broader range of efficient operation and smaller chip area.

To further evaluate the robustness of the proposed design, we analyzed the impact of temperature and process variations on PCE. Figure 6 indicates that PCE decreases with an increase in temperature, demonstrating the degradation in performance due to increased thermal effects. The impact is worse at higher input power levels (20 dBm) compared to 15 dBm, where the efficiency drops consistently across the −40 °C to 120 °C temperature range. The simulation also considers the impact of different process corners, i.e., typical/typical, fast/fast, slow/slow, fast/slow, and slow/fast variations. The PCE is maximum for the fast/fast process, while the minimum efficiency is obtained for the slow/slow process, demonstrating the significance of manufacturing variations on the performance of the rectifier. Furthermore, at low input powers, PCE is more susceptible to process variation, which means design consideration must be careful in order to realize stable efficiency over different environmental and fabrication conditions.

4. Implementation and Simulation

The proposed rectifier layout was implemented using 180 nm CMOS technology (PDK is by TSMC, Taiwan), occupying an active area of 0.6 mm × 0.8 mm, as illustrated in Figure 7a. Post-layout simulation of the $\left|S_{11}\right|$ parameter was also performed, with the results shown in Figure 7b. The rectifier exhibited excellent $\left|S_{11}\right|$ performance, maintaining values below −8 dB across the frequency range of 0.1 to 2.5 GHz for input power levels of 16, 18, and 20 dBm under optimal load resistance conditions.

To evaluate its performance, simulations were carried out with three different load resistances. Figure 8a shows the post-layout simulation power conversion efficiencies (PCE) versus input power for varying load resistances. The highest PCE, exceeding 50%, was achieved at 700 MHz for an input power range of 16–20 dBm with an optimal load resistance of 1.15 KΩ, reaching its peak at 20 dBm. Figure 8b illustrates the post-layout simulation PCE versus frequency with the optimal load resistance, with a maximum PCE of 60.5% observed at 0.7 GHz for an input power of 20 dBm. Having already fabricated and implemented two CMOS rectifier designs ([12,14]), and since this design also adheres to the same design rules (DRC, LVS, and parasitic extraction), the expected deviation between the presented results and measured values should be within 5%.

Table 1. Comparison of proposed CMOS rectifier.

Ref.	${\mathit{f}}_0$ (GHz)	PCE (%)	${\mathit{P}}_{\mathit{i}\mathit{n}}$ (dBm)	${\mathit{R}}_{\mathit{L}}$ (Ω)	CMOS Technology	Area {Active Area} (mm2)	Figure of Merit (FoM) (Hz/mm2)
[15]	0.915	25	0	1 M	180 nm	5.29	-
[16]	0.9	31.8	18	2 K	65 nm	0.4095	-
[17]	0.915	34.4	1.3	10 K	180 nm	0.4	-
[18]	2.4	46	25.5	24	28 nm	0.705	-
[19]	2.4–3.5	46.8 (peak)	22	1 K	180 nm	0.4218	122.048
						{0.2106}
This work	0.2–2.5	>50	20	1.15 K	180 nm	0.7007	198.587
	0.7	60.5 (peak)				{0.48}

FoM = ${\displaystyle \frac{{\eta }_{max}\times FBW}{Area\left(\mathrm{m}{\mathrm{m}}^2\right)}}\times f_o$ [19], center frequency ($f_o$) = ${\displaystyle \frac{f_H+f_L}{2}}$, $f_H$ and $f_L$ are high and low frequencies respectively, fractional bandwidth (FBW) = ${\displaystyle \frac{f_H-f_L}{f_o}}$.

presents a performance comparison between the proposed rectifier and other designs, highlighting its ability to maintain a PCE of over 50% across a wide frequency range from 0.2 GHz to 2.5 GHz. With a peak PCE of 60.5% achieved at 0.7 GHz and 20 dBm input power, the proposed rectifier surpasses the performance of other designs in handling input power effectively.

5. Discussion

The optimized matching network and dynamic body-biasing based new pMOS-based rectifier shows high improvements in power conversion efficiency (PCE) for wideband radio-frequency (RF) energy harvesting and wireless power transfer systems. The body-biasing improves the conduction efficiency of the transistor by reducing the threshold voltage, which causes reduced power loss and a larger operating frequency range. Unlike conventional rectifiers that depend on precise impedance matching to optimize their performance, this topology exhibits robustness under input mismatched conditions, making it highly suitable for beam-forming wireless power transfer (WPT) systems.

One of the strong advantages of the proposed method is that it maintains a high PCE even in mismatched conditions of input. Traditional rectifiers, whose performance depends on narrowband impedance-matching circuits, suffer losses when input conditions deviate from their optimum design values. Utilizing a custom-tailored matching network, our rectifier ensures stable PCE across an extensive frequency bandwidth with minimal loss through reflection. The results indicate that the proposed design achieves the highest PCE of 60.5% at 0.7 GHz and has over 50% efficiency up to 2.5 GHz, which is better than conventional impedance-matching-based designs. This property is particularly desirable in dynamic RF environments where frequency variations are common.

The impact of transistor on-resistance ($R_{on}$) on the PCE is also critical. The value of $R_{on}$ controls the impedance matching condition, and at frequencies where $R_{on}$ is close to 50 Ω, the rectifier achieves better matching and higher efficiency. Conversely, at frequencies where $R_{on}$ deviates significantly from 50 Ω, the matching degrades, leading to a drop in the PCE. The proposed design effectively minimizes $R_{on}$ through body-biasing and optimized transistor width-to-length (${\displaystyle \frac{W}{L}}$) ratios, ensuring improved efficiency across a broader frequency range. Compared to conventional rectifiers that rely on fixed impedance-matching networks, this approach provides greater adaptability and robustness.

While the proposed matching technique enhances wideband performance, there are sacrifices in terms of conventional impedance-matching techniques. Conventional matching networks are optimum for narrowband rectifiers, with improved peak PCE at a given frequency but reduced efficiency when frequency drifts occur. The proposed method, however, sacrifices minor peak PCE for broader frequency operation. This makes it ideal for use in applications that require uniform performance across varying input conditions but less than ideal for heavily optimized narrowband applications.

The other limitation is that while the design realizes high PCE at input power levels of between 15 dBm and 20 dBm, with very low power levels (<0 dBm) its performance can be undermined by the drop in threshold voltage across the CMOS transistors. Conventional diode-connected rectifiers can yield better efficiency in ultra-low-power operations. Similarly, at input power levels greater than 25 dBm, self-heating and reliability problems can undermine the operation of the rectifier.

Scalability to yet higher CMOS process nodes is yet another consideration. Advanced nodes have lower threshold voltages and better transistor mobility, which would make the PCE even more efficient. Experimental validation of the proposed rectifier via prototyping and experimentation is an important area of research for future investigation. While this study primarily focused on circuit-level optimization, we acknowledge that environmental factors such as reflection medium, distance, and multipath effects in wireless power transfer (WPT) scenarios can impact efficiency. Future experimental work will explore these system-level interactions to provide a more comprehensive validation of the proposed rectifier design. Additionally, future studies will investigate the influence of varying transmission distances and different reflection surfaces on received power levels, enabling a broader understanding of real-world deployment challenges.

In summary, the new rectifier offers high efficiency, wideband operation, and input mismatch insensitivity, and is therefore an extremely promising candidate for future RF energy harvesting and WPT applications. While conventional impedance-matching techniques can still be employed for optimal-case narrowband designs, this paper highlights the benefits of hybridizing body-biasing and compensated matching techniques for enhanced performance in different RF environments. Future work will involve experimental validation and extending the design to the higher power levels and frequencies.

6. Conclusions

This study introduces a wideband pMOS rectifier with modified matching and body-biasing, designed using 0.18 μm CMOS technology. Simulations indicate that the proposed approach achieves a peak PCE of 60.5% at 700 MHz with an input power of 20 dBm. To the best of the authors’ knowledge, this is the first implementation of a rectifier combining modified matching and body-biasing to enhance the efficiency of a mid-range RF power CMOS rectifier.

The advantages of the new approach are primarily its robustness to input mismatch conditions and its ability to maintain efficiency under a wide band of frequencies. Compared to the conventional impedance-matching rectifiers, which are extremely sensitive to frequency variations and input conditions, the new configuration also shows consistent PCE behavior under dynamic operating conditions. Furthermore, analysis of transistor on-resistance ($R_{on}$) and body-biasing effects highlights the importance of optimal circuit design for enhanced conduction efficiency. While this effort has focused on circuit-level optimizations, subsequent research will attempt to experimentally validate the design through prototyping and extend its relevance to higher power levels and diverse RF environments.