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Article

UAV Mission Computer Operation Mode Optimization Focusing on Computational Energy Efficiency and System Responsiveness

by
Oleksandr Liubimov
1,2,*,†,
Ihor Turkin
2,†,
Valeriy Cheranovskiy
3,† and
Lina Volobuieva
2,†
1
EKTOS-UKRAINE LLC, 1 Academika Proskury Str., 61070 Kharkiv, Ukraine
2
Department of Software Engineering, National Aerospace University “Kharkiv Aviation Institute”, 61070 Kharkiv, Ukraine
3
Scientific Research Institute “Problems of Physical Modeling of Aircraft Flight Modes”, National Aerospace University “Kharkiv Aviation Institute”, 61070 Kharkiv, Ukraine
*
Author to whom correspondence should be addressed.
Current address: 17 Vadima Man’ka Str., 61070 Kharkiv, Ukraine.
Computation 2024, 12(12), 235; https://doi.org/10.3390/computation12120235
Submission received: 18 September 2024 / Revised: 11 November 2024 / Accepted: 18 November 2024 / Published: 27 November 2024

Abstract

:
The rising popularity of UAVs and other autonomous control systems coupled with real-time operating systems has increased the complexity of developing systems with the proper robustness, performance, and reactivity. The growing demand for more sophisticated computational tasks, proportionally larger payloads, battery limitations, and smaller take-off mass requires higher energy efficiency for all avionics and mission computers. This paper aims to develop a technique for experimentally studying the indicators of reactivity and energy consumption in a computing platform for unmanned aerial vehicles (UAVs). The paper provides an experimental assessment of the ‘Boryviter 0.1’ computing platform, which is implemented on the ATSAMV71 microprocessor and operates under the open-source FreeRTOS operating system. The results are the basis for developing algorithms and energy-efficient design strategies for the mission computer to solve the optimization problem. This paper provides experimental results of measurements of the energy consumed by the microcontroller and estimates of the reduction in system energy consumption due to additional time costs for suspending and resuming the computer’s operation. The results show that the ‘Boryviter 0.1’ computing platform can be used as a UAV mission computer for typical flight control tasks requiring real-time computing under the influence of external factors. As a further work direction, we plan to investigate the proposed energy-saving algorithms within the planned NASA F’Prime software flight framework. Such an investigation, which should use the mission computer’s actual flight computation load, will help to qualify the obtained energy-saving methods and their implementation results.

1. Introduction

Today, unmanned aerial vehicles (UAVs) are widely used in many areas of human activity and play an essential role in scientific, industrial, search and rescue, surveillance, cinematography, and other tasks [1]. The use of UAVs makes it possible to carry out dangerous missions without risking the health and life of the operators. At the beginning of Russia’s aggression in Ukraine, it became clear that effective use of UAVs on the battlefield was almost the only possibility for the Ukrainian armed forces to oppose Russia’s massive military machine. Analyzing this confrontation, the Center of Excellence for Integrated Air and Missile Defense, in its report [2], emphasized the need to adapt NATO’s military doctrines, concepts, and tactics to the new realities of using UAVs, UGVs (unmanned ground vehicles), UWVs (unmanned water vehicles/vessels), and countermeasure systems.
Several works [3,4] have provided overviews of UAV research and highlighted the latest trends and achievements. The authors of these reviews consider UAVs’ general hardware and software architecture and describe their applications. In [5], an overview and classification of UAVs is provided. This review also describes the capabilities and characteristics of UAVs weighing from 2 to 11,600 kg and with operating times up to 40 h.
The UAV market is actively developing. According to Fortune Business Insights [6], the CAGR of the expected global UAV market is 16.3% for the period 2023–2030, and the majority of the market is accounted for by UAVs of small and tactical devices (Figure 1). For such UAVs, the requirements for the on-board computer must correspond to the increased complexity of the system [7,8,9,10].
Every UAV that takes off has a mission to generate value for the operator of a UAV. A UAV consists of reliable, powerful, yet power-efficient avionics (Figure 2) with the required capabilities to carry out its mission. The orchestration of the mission is accomplished by a central computer, which is called the mission computer. The typical tasks of the mission computer are to control the entire avionics, compute the UAV’s route, ensure communication to the ground station (if required), and control the onboard payload.
This article concentrates on the mission computer alone, as this is the most complex yet flexible and configurable part of modern UAV avionics.
The background of the research in this paper is the growing need for real-time mission computers that are powerful and responsive yet power-efficient and cost-efficient.
Investigating the tradeoff between system reactivity and the use of energy-saving modes of the computing platform is a vital consideration in many situations, not only for UAVs but also in all real-time systems with autonomous power supplies. These include embedded systems in industrial applications, Internet of Things (IoT) devices, implanted medical devices, emergency notification systems, etc. During operation of the computing platform, this compromise is achieved through software-implemented algorithms that allow for adaptive control of computer operating modes depending on current conditions and requirements for the reactivity and energy consumption of the system. To solve the question of the expediency of spending on the development of new algorithms and software, experimental study is needed in order to build a mathematical model that comprehensively characterizes the reactivity and energy consumption of the computer.
The purpose of this paper is to develop a technique for experimental study of the indicators of reactivity and energy consumption of computing platforms for UAVs. All work in the paper is carried out using the authors’ ‘Boryviter 0.1’ mission computer.
The rest of the paper is structured as follows:
  • Section 2—‘Domain Overview’ introduces the reader to the mission computers that are the objects of this study, provides an overview of the usage challenges involved in real-time operation systems (RTOS), and describes tools and needs of energy-saving solutions for embedded mission computers.
  • Section 3—‘Materials And Methods’ describes the platform for conducting the study experiment, defines a system model in the manner of a power state machine, and describes the exact method for measuring the reactivity and power consumption of different modes of operation.
  • Section 4—‘Results’ provides the obtained experiment results.
  • Section 5—‘Discussion’ describes and presents the obtained results applied to the proposed system model.
  • Section 6—‘Conclusion’ concludes the article by describing the novelty of the research and its further development.

2. Domain Overview

This chapter provides an extensive overview of the technology, design, and efficiency considerations for mission computers in unmanned aerial vehicles (UAVs).
The contemporary approach to developing avionics and mission computers consists of the following key steps:
  • Select an appropriate ready-to-use avionics platform (including a mission computer).
  • Use a microcontroller-specific vendor toolchain.
  • Ensure that a real-time operation system is in place and can be easily adapted to the selected computation platform.
  • Design and validate the requirements for the flight mission business logic (i.e., what exactly the UAV needs to do).
The above items do not guarantee that the selected platform, microcontroller, operating system, and other components will allow the integrator to achieve the required results to fulfill the mission objectives. In the rest of this chapter, we provide an in-depth review of the technologies, techniques, parts, and problems mentioned in the UAV avionics design process.

2.1. UAV Avionics and Mission Computers

Typical UAV avionics (on-board electronics) consist of several key parts (Figure 3):
  • Mission computer (often called an on-board computer or flight controller board).
  • Navigation and orientation system (GNSS and GPS).
  • Sensor board and sensors.
  • Remote control and telemetry system (communications unit).
  • Energy and propulsion system (driving unit).
  • Payload (sometimes called an off-board module).
A mission computer is a specialized computer system integrated into the avionics of a UAV, or more generally into a complex technical device that requires autonomous control and high reliability [12]. Computational power, reactivity, energy efficiency, peripheral support, and real-time performance are all important considerations when choosing a mission computer. The reality of mission computer buildup and development shows that most commercial off-the-shelf (COTS) products [13] are built on a specific series of microcontrollers or microprocessors (main processors) known to the development team or the vendor. This expertise significantly advances software quality, expedites time-to-market, and enhances flight heritage.
Microcontroller units (MCUs) utilized in UAVs and nanosatellites generally exhibit substantial similarities, except when considering radiation-hardened or radiation-tolerant microcontrollers [14]. These specific microcontrollers are beyond the affordability of commercial electronics, and consequently are not be evaluated in this article. As a result, the spectrum of available components for utilization and the associated toolchain for RTOS and development tools is considerably broadened.
The similarity of the requirements for the construction of UAV and nanosatellite onboard systems makes it expedient to use a standard technology stack [15] to address both application areas being part of aerospace engineering. A description of the highly integrated onboard computing products used for CubeSat missions (a class of nanosatellites) is provided in [16]. The most energy-saving solutions are based on ARM Cortex-Mx (where x is 0 to 7), LEON3FT, and Atmel ARM 9.
Electronic component manufacturers are constantly updating their available offerings, allowing UAV developers to achieve better results (appropriate productivity with low power consumption) when solving complex tasks. Popular MCU series with brand-new families that can be used in UAV onboard systems include the SAMx Series (Atmel/Microchip) [17], PIC32 (Microchip), STM32 Series (STMicroelectronics), and iMX.RT series (NXP). The characteristics of the most popular series of 32-bit microcontrollers for implementing UAV mission computers are listed in Table 1. The precise selection of the components examined here was determined by balancing performance, available memory, and the availability of energy-saving modes.

2.2. Problems and Researches in the Field of Mission Computers

Ensuring the ability to fly autonomously requires efficient sensor operation along with appropriate flight control and mission software. There has been a great deal of research into the use of AI for these tasks, such as computer vision for object recognition and tracking [18,19,20], reinforcement learning for mission control [21], sensor fusion, and more. The success of missions in general along with the particular effectiveness of applying machine learning (ML) models critically depends on the reactivity of the onboard system to ensure the prompt acquisition of data and the execution speed of the relevant program blocks.
Another area of research involves the energy efficiency of onboard systems [15,22], which directly affects the maximum duration of UAV flight as well as the maximum weight reduction of the powertrain and its energy source. Any calculations, from the business logic that performs the business tasks (payload) and overall mission control (such as engine control) to system ones such as diagnosing the state of the computer and connected sensors and actuators, require software running on the central processor or microcontrollers. The availability of microcontrollers does not play a part in the last role, which consists of selecting electronic components for mission computers. Research involving experimental comparisons of the effectiveness of solutions based on various technology stacks is currently being conducted, including the use of low-cost solutions and open-source software. Thus, the authors of [23] described the creation of a hexacopter and a quadcopter built on different flight controllers and software. They provided experimental results using low-budget components and free open-source products. The authors of [15] provided the results of a stack layer comparison, including the use of open real-time operating systems (RTOS) such as FreeRTOS, ROS, and Linux with real-time extensions, open middleware such as cFS (core Flight System) by NASA and F’ Prime by JPL/NASA [24], and image sharing firmware.
Assessment of electrical power consumption in microcontrollers requires the use of mathematical models to delineate the relationship between energy consumption and the operational parameters of the target computing platform. Typically, these models are expressed as mathematical functions that correlate energy consumption with characteristics measured or estimated at a specific level of abstraction in conjunction with the fundamental hardware architecture. The power consumption model can be used as input data during development and for adaptive control of mission computer operating modes during application. Depending on the specific target application, the power model must meet different multi-domain and multi-criteria requirements and be designed accordingly. Power analysis during design uses the power model offline to limit the design parameter space of the target computing platform, allowing for evaluation of energy, power, performance, and other quality indicators at an early stage of development. Conversely, monitoring consumed electrical power during operation allows for adaptive control of operating modes in real-time by comparing actual energy consumption estimates and a predesigned energy consumption model.
It is important to mention that complex mission computers contain many peripheral in-circuit devices such as external RAM, ROM, peripheral interface drivers, ADCs, DACs, IMUs, etc. Proper peripheral control of these extra devices via correct microcontroller power modes ensures overall energy efficiency on the part of the mission computer. The rule of thumb is that the microcontroller and the rest of the digital peripherals consume equal amounts of energy.
Looking into modern development approaches to embedded software development, it is easy enough to see that bare-metal programming is becoming less and less used, whereas RTOS-based programming is dominating. Using RTOS ensures interoperability and reuse of software components and permits modern system architecture approaches such as microservices, containerization [25], and for larger microcontrollers, virtualization. This article focuses on optimizing the power consumption of microcontrollers governed by RTOS without assessing the remaining peripherals of the mission controller.

2.3. Real-Time Systems and Typical Scheduling Algorithms

Real-time systems must guarantee task execution within specified deadlines and time constraints while ensuring energy-efficient computations. For mission computers, such tasks could be motor control, ground station communication, sensor fusion tasks, orientation, aircraft and operator safety handling, and navigation. The mission computer needs to handle all these typical tasks with different demands in terms of real-time criticality.
All possible tasks performed by a microcontroller can be classified as follows, determined by the nature of event occurrence:
  • By execution reason: periodic and sporadic tasks.
  • By constraint nature: tasks with hard or soft deadlines.
The execution schedule of a real-time system is correct if all time constraints are met.
For periodic tasks, the schedule is a table that indicates which task should be executed at which point in time. A minimum possible event occurrence period is determined for sporadic tasks, allowing them to be artificially classified as periodic. This schedule must be compiled for a time interval equal to all tasks’ hyperperiods (the least common multiple of periods) to guarantee their execution without violating time constraints.
The classic work by Liu and Layland [26] proposed two main scheduling concepts for priority-based real-time systems:
  • Rate-monotonic scheduling (RMS): Static priority assignment in reverse order of known task periods.
  • Earliest Deadline First (EDF): Dynamic priority scheduling, where the highest priority is assigned to the task with the nearest execution deadline.
RMS-based schedulers work on timer interrupts, with tasks simply being called from the interrupt handler at the right moments. This class of algorithms has advantage of exceptional simplicity and predictability, as confirmed by a large number of test results and experiments. Disadvantages include:
  • Inflexibility, as the scheduler does not actually react to external world events and works exclusively on timer interrupts;
  • Difficulty in scheduling sporadic tasks based on the minimum possible period of external events;
  • Very large size of the schedule table with appropriate ratios between task periods.
EDF-based schedulers define the task with the earliest absolute execution deadline as the highest priority. However, in practical real-time systems the relative deadline for task execution may not always equal its period. Hence, the above assumption greatly limits the usefulness of available scheduling test results based on EDF usage. Analysis of the exact scheduling possibility for EDF scheduling with arbitrary relative terms requires calculating processor requirements for a task set at each absolute term in order to check whether there is an overflow at a given time interval. This interval is limited by a certain value, which guarantees that a failure point can be found if the task set is not schedulable. Significant efforts to perform schedulability checking according to EDF in real systems limit the possibilities of applying EDF in real-time. As a result, the EDF algorithm is not widely used as a fixed priority algorithm in commercial real-time systems [27]. Weakly hard or firm hard real-time systems started to see use 2001 [28] as a a way to better characterize real-time task constraints. The concept is based on task differentiation, assuming that not all task-time constraints must be satisfied. In general, this approach uses a model (m, k) based on the assumption that at least m instances out of any k consecutive instances (jobs) of a task must meet time constraints; in other words, one-time or even repeated violation of time constraints by a single task is not always a failure if the number of such violations does not exceed a predetermined number. This is explained by the existing redundancy of systems, and is applied to soft real-time tasks and hard or firm real-time tasks.
The concept of weakened systems has been further developed in many works, for example in [29,30]. The concept is based on the following task model in the form of a tuple:
τ i = C i , D i , T i , m i , K i
where C i is the maximum time required for the task and T i is the minimum time interval for the arrival of the task. If it is a periodic task, then T i is its period; if it is sporadic, then it is the minimum period of interruption occurrence, where D i is the time constraint for task execution ( D i T i ) with
m i , K i , m i < K i ,
as the weakened constraints of real-time tasks. In a sequence of K i jobs for this task, deadlines can be violated no more than m i mi times. If this task belongs to the hard real-time class, then
m i = 0 , K i = 1 .
The scheduler algorithm in a weakly hard real-time system includes the following steps:
  • If all scheduled time constraints of all jobs for all tasks can be met using EDF, then use EDF and finish; otherwise, proceed to Step 2.
  • Sort the jobs of all tasks according to the criterion of the number of time constraints of jobs that are still allowed to be violated for the planning time interval. Class “0” will include all tasks that do not allow any misses, while Class “1” will include those that can violate the time constraint once. For example, if ( m i ; K i ) for a task is equal to (2, 4), then it is allowed to violate the time constraint of two jobs out of four consecutive jobs; thus, the task can fall into classes (0, 1, 2) depending on the number of jobs already missed.
  • Use EDF first for class 0, then for class 1, etc.
Many modern publications are devoted to technologies for evaluating microcontroller performance indicators and measuring the time costs of typical algorithms on both widely used mass-produced platforms and original developments.
In [31], the authors performed a comparison of the performance indicators of the Raspberry Pi4, BeagleBone AI, and TWR-K70F120M platforms as well as the execution time of algorithms on these platforms under the condition of multithreaded implementation of a specific set of executable tasks. The leading indicators for real-time systems were the task execution time, worst-case execution time, waiting time, and response delays. To achieve the goal, a multithreaded test program was developed with special computationally intensive sorting operations, matrix operations, and the wolfCrypt lightweight crypto library. The test program was written in ANSI C and designed for embedded systems, real-time systems, and resource-constrained environments.
The article in [25] provides results that compare the computational performance of the Pi Pico open STEM-like hardware project from Raspberry on the RP2040 processor [32] with the author’s solution, consisting of the “Falco SBC/CDHM” computing platform based on the ATSAMV71 microcontroller (microchip) [17] with improved performance. The possibility of using microservice architecture and the effectiveness of the proposed new platform were experimentally verified by measuring the processor time required to execute three typical algorithms of different algorithmic complexity and initial data with different dimensions.
A common drawback of the considered works is lack of evaluation of the energy efficiency of computing platforms. An integral feature of real-time systems is redundancy, including of time resources, to guarantee the fulfillment of time constraints under any conditions. In real projects such redundancy exists at the hardware and software–algorithmic levels. It is essential to answer the question of how energy-efficient the platform’s behavior is during the time interval when all current tasks have already been completed and there is no need to do anything until a new interrupt comes (either externally from connected devices or internally from the system timer). The ideal situation would be for the platform to consume nothing during this time; however, this is impossible. The reverse side of this problem is to determine the indicators of deterioration in the reactivity of the computing system, as the processor and other components of the computing platform must first fully restore the normal operating mode after an external event before starting to do something useful.

2.4. Methods of Energy Consumption Management

The survey in [33] provides the following classification of methods for ensuring the energy efficiency of microcontrollers in embedded systems:
  • Dynamic voltage and frequency scaling (DVFS) methods and power-aware scheduling;
  • Use of low-power consumption modes, called Power Mode Management (PMM) or Dynamic Power Management (DPM);
  • Micro-architectural techniques for energy conservation in individual components such as memory, where the computational context is stored in memory during total or partial processor shutdown;
  • Use of non-traditional computers such as DSP or GPU FPGA. This method is suitable for computationally intensive tasks where traditional general-purpose processors perform worse (mW/MIPS).
In [34], the authors explored the possibility of energy savings in wireless sensor networks through DVFS in low-energy microcontrollers. The quantitative metric for evaluating energy efficiency was the normalized power, i.e., the ratio of consumed electrical power to performance (mW/MIPS). Using the normalized power allows for more accurate characterization of the microcontroller’s energy efficiency, as it considers the both consumed electrical power and the performance as expressed in millions of instructions per second (MIPS). The lower the value of the normalized power, the less energy the microcontroller will consume.
Overall, the above article provides a reasonable basis for further research into DVFS in wireless sensor networks; however, some aspects require more thorough elaboration. Drawbacks include the difficulty of generalizing the obtained results to other platforms and architectures, lack of evaluation of overhead costs for transitions between DVFS modes, and a limited number of measurements for different voltage/frequency combinations.
The publication in [35] comprehensively investigated the relationships between three components:
  • Real-time constraints;
  • Constraints on the energy consumption of the computer;
  • Software methods for ensuring fault tolerance.
The authors discussed the interdependencies between the probability of permanent failures in frequency and supply voltage, the probability of temporary failures in task execution time, and the dependence of the consumed electrical power on the computer’s chosen fault tolerance policies and operating parameters. They proposed a joint model for analyzing scheduling and failures that highlights formal interactions between fault tolerance mechanisms and temporal properties. Their article suggests several vital directions for future research in the field of fault-tolerant real-time systems:
  • Development of scheduling algorithms that take the probability of failures into account to minimize the active time of tasks and their total failure probability while maintaining schedulability.
  • Analyzing the impact of various fault tolerance strategies (re-execution, checkpoints, N-modular redundancy (NMR)) on scheduling. In particular, it is important to integrate different approaches and their optimization in order to improve schedulability and compliance with requirements for failure probability.
  • Application of the mixed criticality concept to make systems compatible with industry standards and quantify the probability of transition to high-criticality mode.
  • Analysis of the tradeoffs between energy consumption management (DVFS), thermal effects, resistance to various types of failures, and real-time requirements.
  • Improving system software reliability, such as scheduler and failure detection mechanisms.
  • Use of probabilistic information about execution time to calculate a more accurate estimates of failure probability.
  • Consideration of other failure models, such as (k, n), approximate computations, and malicious failures.
The article in [36] analyzes the reliability of embedded real-time satellite systems operating in harsh space environments. Two types of errors characteristic of systems operating in harsh temperature and/or radiation conditions are considered:
  • “Soft-error” or “soft fault”: A single-event upset (SEU), i.e., temporary distortion of a bit value in memory or processor register caused by external factors that does not lead to permanent hardware damage.
  • “Hard-error” or “hard fault”: Permanent damage to a hardware component caused by wear or degradation of materials due to prolonged operation, for example, radiation exposure. Such errors are classified as single-event latchups (SEL).
Real-time system constraints are taken into account by using a periodic task model to assess the system load during redundant backup execution of tasks to detect soft errors and their subsequent elimination by the requirements of functional safety standards such as DO-178B, IEC-61508 [37], and ISO-26262 [38]. Increasing resistance to single soft errors and permanent hard errors is achieved by solving an optimization problem.
The article in [39] developed and analyzed methods for reducing energy consumption in ultra-low-power embedded systems using dynamic voltage and frequency scaling (DVFS). The authors analyzed energy consumption while performing computationally intensive operations such as the Fast Fourier Transform (FFT), Cyclic Redundancy Check (CRC32), and calculation of the MD5 and SHA256 hash functions. According to the results of experimental testing on the ARM Cortex-M0+ microcontroller, they confirmed that the application of DVFS can provide electrical energy savings from 27.74% to 47.74%. Disadvantages include a lack of comparison with other energy-saving methods and a limited set of test operations (FFT, CRC, hash functions), which may not represent other load types. The problems of transient processes during dynamic voltage changes and related time delays remain unexplored.
The problem of evaluating the effectiveness of system planning and energy savings in embedded real-time systems with low computational resources was considered in [40]. In real-time operating systems (RTOS), the characteristics of the implemented scheduling policy play an essential role in both scheduling and energy consumption. Ideally, the scheduling policy should guarantee adherence to task schedules and ensure low energy costs during execution, thereby saving energy by through better use of the available free time. The scheduling policy proposed by the authors was based on fixed priority scheduling (RMS), which provides low overhead and simple implementation. According to this scheme, a simple priority vector indicates that the current task is ready for execution. However, the scheduling results are usually lower than those achieved by dynamic priority scheduling, which prioritizes tasks according to which tasks are assigned during execution.
In [41], a microcontroller using the FreeRTOS operating system managed a limited energy budget using hardware and software tools. FreeRTOS executes the idle task with the lowest priority when all other tasks transition to a blocked state (waiting for an event, resource, or the next timer-driven run). Therefore, the idle task can be put into energy-saving mode when the processor is idle. This mechanism is helpful in certain scenarios; however, if the clock frequency is too high, the processor will waste energy and time while entering and exiting standby mode. Thus, saving energy using this mechanism may not be beneficial. To improve the corresponding energy-saving mechanism, a tickless idle technique was introduced in [42]. This technique uses a time-tracking mechanism to turn off the source of periodic ticks for a certain period, which puts the processor into deep sleep mode until an external interrupt or a higher-priority core interrupt occurs.
In [43], a solution was proposed that optimizes the energy efficiency of the operating system scheduler of a microcontroller based on LM3S3748. The proposal uses an “idle” system flow, which puts the microcontroller into a sleep or deep sleep mode after its work is completed. The article provides quantitative experimental results of measurements of the energy consumed by the microcontroller and estimates of the reduction in system reactivity due to the additional time costs for suspending and resuming the microcontroller’s operation. A disadvantage of the article is lack of generalization of the results in the form of a general technology for optimizing the energy efficiency of the microcontroller operation.
In [44], the authors provided an overview of the main energy-saving algorithms. DVFS (Dynamic Voltage and Frequency Scaling) dynamically changes the processor voltage and frequency, while DPM (Dynamic Power Management) provides dynamic power management based on switching the processor into low-power consumption modes. This review highlights the main problems associated with the reactivity of real-time systems when applying energy-saving methods, and emphasizes the complexity of balancing energy efficiency and maintaining the required level of reactivity in real-time systems.
The reactivity time indicators provided in the above article can be divided into two classes. The first class includes delays that are determined mainly by the hardware component:
  • Wake-up delays characterize the time required for full recovery of the processor from sleep mode. They can be measured by determining the time interval from the moment of the interrupt request to the first useful command in the interrupt handler.
  • Break-even time is an integral characteristic. The processor must spend the minimum amount of time in low-power consumption mode to compensate for the energy and time costs of transitioning to this mode and back. Break-even time is the sum of the wake-up and transition delays, which characterize the time costs necessary for the processor to transition from active state to sleep mode.
The second class includes delays that are determined only by software algorithms:
  • Procrastination delays: Certain algorithms deliberately postpone the execution of tasks to increase the duration of the idle period and more efficiently use low power consumption modes. These delays are carefully calculated so as not to violate the time constraints of tasks.
  • Scheduling delays: The time required to make decisions about changing the power consumption mode and rescheduling tasks.
  • Delays associated with calculating optimal moments for transitioning to sleep mode and waking up: Certain algorithms perform complex calculations to determine these moments, which can introduce additional delays.
  • Early completion delays: These delays create additional space for energy saving, but require dynamic rescheduling.
Considering the delays in the first class is critical for practical application of energy-saving modes in real-time systems, as they directly affect the system’s ability to adhere to time constraints while simultaneously reducing energy consumption. Therefore, only these delays are the subject of further consideration in this paper.

2.5. Overview of Existing Methods for Evaluating the Performance and Energy Efficiency of Embedded Systems

Optimizing system indicators begins with measuring and analyzing the system parameters. While there are many tools for measuring and evaluating performance and energy efficiency for modern household PCs, the number of such tools for embedded computing is limited, and very little known to embedded system developers.
The authors of [45] investigated the computational performance and energy efficiency of various microprocessors used as mission computers in nanosatellites during the typical tasks of determining and controlling the nanosatellite’s orientation. The authors’ primary motivation for developing a new specialized benchmark (software for measurement and comparison) instead of using known benchmarks was the shortcomings of the current benchmarks.
In short, the following benchmarks were analyzed:
  • Benchmarks such as EEMBC [46], ParMiBench [47], BEEBS [48], and EmsBench [49] do not contain a sufficient number of operations with the matrices, quaternions, and calculations typical of satellite orientation control algorithms.
  • While most existing benchmarks are focused on performance evaluation, the energy efficiency of calculations is critically important for satellite systems due to their strict power constraints.
  • Requirements for large memory volumes or use of external files can be problematic for embedded systems with limited memory resources, as some benchmarks require access to the file system.
  • There is a lack of open-source code and excessive requirement for paid subscriptions; for example, EEMBC benchmarks require a paid subscription to access test loads.
The authors tested their developed benchmark on three platforms often used in nanosatellites: Arduino Uno, Texas Instruments MSP430, and STM32 Nucleo. The amount of consumed electrical energy was used as a key metric to compare different platforms. As a test set of tasks, the authors used typical operations and algorithms for determining orientation and controlling nanosatellites, such as operations with matrices of arbitrary dimensions and quaternion calculations.

3. Materials and Methods

3.1. Planning the Experiment

The hardware platform discussed in the following chapters falls within the first class and partially in the second, being specifically designed for unmanned aerial vehicles with a takeoff weight range of 20 to 150 kg according to the NATO standard 4671 “Unmanned Aerial Vehicles Systems Airworthiness Requirements” (USAR) [50]. According to this standard, we consider MTOW of Class II (“UAVs with MTOW between 150 and 600 kg”). All experimental research was carried out on our computer platform named ‘Boryviter 0.1’ (Figure 4), which is described in detail in the work [25] and on the presentation page [51]. The platform is built based on a 32-bit Atmel ATSAMV71 microcontroller (Figure 5), which belongs to the ARM Cortex M7 microcontroller family [17] and operates under the control of the FreeRTOS open-source real-time operating system (RTOS).
The chosen ATSAMV71 microcontroller has three low power-saving modes: Sleep, Wait, and Backup.
In ‘Sleep’ mode, the processor core stops, while all other functions, that is, DMA and peripheral digital automates, can continue to work. Sleep mode best balances the power consumption of external events and the response time.
In ‘Wait’ mode, all clocks and functions are stopped, but some peripherals can be configured to wake the system according to predefined conditions. This “sleepwalking” feature performs a partial asynchronous wakeup, allowing the processor to exit sleep mode only when needed. In “Backup” mode, only 32-bit low-power real-time timer (RTT), real-time clock (RTC), and wake-up logic work. In this mode the device can meet the most stringent key-off requirements when the system or device is powered off. However, the microprocessor continues to operate with some activity level, storing one kB of SRAM. The system clock has been designed to support different clock frequencies for selected peripherals to optimize power consumption. In addition, the CPU and bus clocks can be changed without affecting the USB, U(S)ART, AFE, and timer counter operations.
Backup mode achieves the lowest possible power consumption. This mode is quite suitable for applications where recurring and periodic tasks need to be executed and the microcontroller can sleep the rest of the time. While this is a good instrument for low-reliability or slow control systems, it does not fit very well with the real-time tasks of the mission control computer. It is essential to mention that the core state after return from backup mode is “reset”, which means that the specific software design patterns need to be used in order to construct an appropriate usage regime for this mode.
In our work, we used some effective measurement techniques from [52] to measure time costs for service operations such as interrupt handling and thread-switching delays for virtual machines, which in this article has been adapted for a microcontroller and RTOS setup. Given that FreeRTOS operates with the tasks concept, while the interrupt handling exists within a parallel computation context which is largely independent of the scheduler operation, we adopted the aforementioned architectural approach for our experimental needs.

3.2. Limitations and Assumptions

The following limitations and assumptions apply:
  • The supply voltage of the microcontroller is nominal and equal to 3.3 V. This is the most reliable supply voltage for the electronics components of the mission computer and provides the best resistance against one-time failures and electromagnetic interference (EMI). There is a power consumption dependence over the supply voltage; however, this is outside the scope of this research.
  • The priorities of the performed tasks are assigned according to the classical theory of Lew and Leyland, called RMS (rate-monotonic scheduling). In this case, each task τ i is periodic and characterized by two numbers:
    τ i = C i , T i
    where C i is the maximum time required for the task execution and T i is the repetition period of the task.
  • For a set of N tasks to be performed,
    T = { i = 1 N τ i }
    is always formed in such a way that they meet the sufficient condition of scheduling tasks of hard real-time systems formulated by Liu and Leyland [26]:
    i = 1 N T i C i N ( 2 1 N 1 ) .
  • The limit on the size of the system tick, which determines the frequency of interruptions from the system timer, is obtained from the FreeRTOS documentation, taking into account the limitations of the MPLAB X IDE development environment for the Atmel ATSAMV71 microcontroller:
    T { 1 ms , 4 ms } .
  • The limits on the microcontroller clock frequency are determined based on the technical documentation for the ATSAMV71 microcontroller and hardware clock configuration of the ‘Boryviter 0.1’ mission computer, and form the following set:
    f { 30 MHz , 100 MHz , 300 MHz } .

3.3. Experiment Plan

We can define the ATSAMV71 microcontroller as a power-state machine with several operating modes: an active mode enabling software to make its main calculations, and several low-power modes that turn off different CPU peripherals and components (Figure 6). Dependencies on the clock frequency over the electrical power consumed by the microcontroller in possible power states and the time spent on transitions between them must be obtained based on the results of experiments. Such experiments were conducted, with the results detailed later in this article.
We can divide all of the necessary experimental dependencies and structure them into the following three classes:
  • Dependence of energy consumption on frequency. The dependencies of the consumed electric power on the processor clock frequency N ( f ) must be determined separately for each operating mode m. The set of possible modes includes active mode and three power saving modes:
    m { A c t i v e , S l e e p , W a i t , B a c k u p } .
  • Time spent by the operating system to perform functions related to rescheduling and dispatching tasks. These events can originate from forced software requests for rescheduling, system timer interrupts due to the next system tick, or external unplanned interrupt triggering OS synchronization facility (Mutexes, Semaphores, Event Groups, and Queues). The following definitions correspond to the different events identified for the experiment:
    (a)
    Forced software re-scheduling. The FreeRTOS taskYIELD() function is the basic function of cooperative dispatching. It immediately causes rescheduling, forcing the scheduler to check whether another task is ready for execution. If such a task exists and has a priority higher that or equal to the current one, then a context switch to this task is performed. Unlike external or system tick interrupts, taskYIELD() does not rely on hardware interrupts. Instead, it is a software mechanism in which the running task voluntarily yields execution, allowing other tasks to run. As a result, the taskYIELD() function represents a cooperative approach to multitasking wherein tasks manage their own execution time. At the same time, external interrupts and system tick interrupts are part of a preemptive system where the OS can forcefully manage task execution based on real-time events and regular scheduling needs. The time required to perform the function is denoted by L a t Y ( f ) .
    (b)
    System timer interrupt. The processor time spent processing interruptions from the system timer I R Q T i m e r depends on the clock frequency of the computing platform. It characterizes the operating system’s overhead for working in the preemptive multitasking mode. System tick interrupts occur regularly, triggering the OS to perform tasks such as updating the system time, managing the scheduling process, and potentially preempting the current task if necessary. The time required to perform the function is denoted by L a t T ( f ) .
    (c)
    External or peripheral interrupt. The time of the system and call of the interrupt service routine (ISR) is the time from the moment of the occurrence of the external or peripheral interrupt to the time of execution of the first command of the interrupt handler. The time required to perform the function is indicated by L a t e x t ( f ) . When an external interrupt occurs, the Interrupt Service Routine (ISR) handler or the first-level interrupt handler (FLIH) is triggered immediately. This mechanism forces the OS to temporarily stop the current process, handle the interrupt, then return to the interrupted task or switch to a different task based on priority. It is essential to mention that freeRTOS is a very low-footprint RTOS, and in reality the context of the ISR handler and the rest of the RTOS context are not very closely coupled; in other words, the IRQ handling is akin to a regular blocking function with an asynchronous call and primitive calculation context preservation that heavily leans on ARM Cortex M core capabilities.
  • The time spent entering and leaving the low-power mode (LPM). The time required to enter and leave a low-power mode defines how much energy can be saved and how much the system reactivity will be decreased. According to the power state-machine definition, two transitions shall be assessed:
    (a)
    Entering. As entering an LPM requires a specific amount of instructions, its time needs to be properly measured. Only specific processor peripherals are shut off depending on the exact LPM. No memory preservation actions are required.
    (b)
    Leaving. Exiting an LPM requires more sophisticated actions; as some LPM modes shut off the internal frequency generator or switch it to the low-power one, a specific stabilization time is required before any processor instruction can be executed.
Thus, the independent factors of the experiment are the clock frequency and the operating mode, while the data that need to be obtained via experiment are the energy consumption, the processor time spent on interrupt processing from the system timer, and the delay in the execution of the first instruction of the interrupt processing procedure. A complete factor experiment is planned, in which the factors take the following values:
f { 30 MHz , 100 MHz , 300 MHz } , m { A c t i v e , S l e e p , W a i t , B a c k u p } .

3.4. Measurement Technique

Typically, all power-saving measurements in modern microcontrollers require quite a comprehensive setup, as they require precise energy measurement, synchronized time-slice measurements, and an external disturbance generator.
The research bench for our experiments (Figure 7, Figure 8, Figure 9 and Figure 10) was built with the following equipment:
  • A square wave generator (GOOD WILL INSTRUMENT EURO B.V., Veldhoven, The Netherlands), Model: GW Instek GFG-8219A, that generates external interrupt signals with a given period.
  • A high-precision power supply unit and power meter (Tektronix UK Ltd., Oldbury, Bershire, UK), Model: Keithley 2281S-20-6, that measures the electric energy consumed. It guarantees the accuracy of the measurements to a measurement error no worse than 15 ms for the time interval and not exceeding 0.0001 W for the electric power.
  • A multi-channel storage oscilloscope (Teledyne Technologies, Chestnut Ridge, NY, USA), Model: LeCroy WavePro 7200A, that the measures the time interval between two events: an externally generated interrupt signal from the square wave generator and the first command of the interrupt handler, which is a change in the state of a predefined port (Port 1) to its opposite. Because the command to change the port is atomic, i.e., is executed in one computing cycle in the RISC architecture, the time to change the state of the port can be considered insignificant.
  • The hand-modified ‘Boryviter 0.1’ mission computer, where the oscilloscope is connected to the two GPIO outputs (via flying wires) and to the signal generator.
We had to design a more complicated measurement connection diagram for the second part of the measurements (entering the low-power modes). The key idea was to use a shunt resistor that was already soldered onto the mission computer together with an operational amplifier to ensure that the proper scale and linearity of the current consumption could be captured on the oscilloscope. With this addition, the connection diagram for the second test bench includes:
  • The high-precision power supply unit and power meter (Keithley 2281S-20-6) used to measure the electric power consumption;
  • A multi-channel oscilloscope by Siglent, (SIGLENT Technologies Germany GmbH, Ausburg, Germany), Model: Siglent SDS1204X-E, that measures the trigger event between the processor command “go to low-power mode” and the current consumption response of the microcontroller;
  • The modified ‘Boryviter 0.1’ mission computer, where the oscilloscope is connected to the output of the power monitor’s operational amplifier to ensure proper signal linearity and low noise.
The designs used to obtain the measurements followed the connection diagrams shown below.
For the three classes of dependencies defined above, the following measurement techniques were used:
  • To obtain the dependencies of the energy consumption on the frequency in the available modes of operation of the microcontroller in the stationary mode of operation, it is sufficient to set one of the four operating modes (Active, Sleep, Wait, Backup) and record the electrical power consumed by the Keithley 2281S-20-6 power measurement unit.
  • The time spent by the operating system performing functions related to the rescheduling and dispatching tasks was measured in the following way.
    First, to estimate the preemptive dispatching time, we measured the execution time of the simple predefined calculation algorithm with the known execution time for each CPU frequency. For reliable results, a set of 1000 measurements was executed. It was expected that some iterations of the known algorithm would take longer due to the overhead required for handling external interrupts and interrupts from the system timer. Supposing that the frequency of the external interrupt differs from the frequency of the system timer by 1.5–2 times and that the execution time of one iteration is 20–30 percent of the value of the system tick, we obtain the dependence of the execution time on the iteration number shown in Figure 11. If we suppose that the frequencies of interruptions (external and from the system timer) differ by 1.5–2 times, it is very easy to distinguish their influence on the general graph; in this case, it is sufficient to count the number of measurements that are obtained on the corresponding shelves.
    We distributed the results of the actual execution time measurements of each iteration onto four shelves depending on whether the cycle was interrupted by processing interruptions. The shelves corresponded to the following situations:
    • No interruptions occurred;
    • An interrupt from the system timer occurred;
    • An external interrupt occurred;
    • The iteration was interrupted twice, by the system timer and externally.
    The following algorithm was performed for each CPU frequency to estimate the cooperative dispatch time.
    The program first accumulates an array of data about the execution time of the mutex ‘take’ operation. The FreeRTOS is configured to have only one single task, which blocks and releases the mutex and then records the time required to perform these two operations in the array.
    In the second stage, several tasks are created, which block the mutex in a loop, records the time and task number in the logEntries shared array, releases the mutex, and then calls the system function taskYIELD() to transfer control to other tasks. These tasks work in parallel, creating conditions for estimating the overhead of switching between tasks. A hardware timer measures the time of operations with a resolution equal to 66.66 ns. The logEntries array stores the execution time of the operations and the task number, which enables analysis of the results after the program is executed.
    Conditional transition between stages: The second stage begins after completing the first, ensuring the correctness of the accumulated data.
  • Time spent entering and leaving low-power modes (LPMs). According to the processor datasheet, the ‘Wait’, ‘Sleep’, and ‘Backup’ modes require a specific microcontroller shutdown technique that in return requires a waiting loop to ensure that all peripherals are safely turned off. However, as the ‘deepest’ power saving mode, ’ Backup’ mode can be exited only if a processor resets. To measure this, it is necessary to apply external devices, because when the processor is turned off and the peripheral shutoff process has been initiated it is impossible to obtain information on when exactly the core stopped working. The time for transitions ([1], [3], [5]) in Figure 6 can only be determined using an external oscilloscope, as the program is not executed in the energy-saving mode. In this case, the actual time of entering low-power mode can be assessed by the drop in the supply current consumption registered by the oscilloscope:
    • Step 1: The test software toggles the output GPIO port state, allowing the connected oscilloscope to be triggered.
    • Step 2: The second channel of the connected oscilloscope, which is connected to the operational amplifier, registers the drop in current consumption based on the trigger event of entering the LPM.
    • Step 3: The time required to enter an LPM is obtained by calculating the time difference between the trigger event in Step 1 and the current drop event in Step 2.
    The exit time measurement technique for transitions ([2], [4], [6]) in Figure 6 is also rather difficult. Still, by having an external interrupt essentially wake the processor up, it is straightforward enough to measure the time difference between the external interrupt signal from the signal generator and the output pin toggle of the microcontroller.
    However, because the deepest “Backup” power saving mode can only be exited during a processor reset, for this specific case the test software was modified to make the specific pin toggle the first operation from the start of the software. The exit from the LPM depends heavily on the particular LPM and how it implements the microcontroller’s peripheral shutdowns. The “Sleep” and “Wait” modes are relatively straightforward to measure, as both allow for return to the computational context before the LPM; however, the “Backup” mode is less trivial. Exiting the “Backup” mode requires a RESET vector entrance, which means that the microcontroller software starts from scratch. This behavior requires a more complex software architecture for implementation, and typically requires an external NVRAM that can be used as context memory.
    Thus, we used two different test software scenarios to measure the exits from the different LPM modes. For both scenarios, an external interrupt from the signal generator was used. This signal triggered the connected oscilloscope to capture the GPIO pin toggle as the first operation after the microcontroller became ready to execute the following command on the program counter (PC):
    • Scenario 1—Sleep and Wait modes:
      -
      Step 1. The wakeup source is configured to react on the external interrupt from the GPIO pin connected to the signal generator.
      -
      Step 2. The external signal generator is set to generate square pulses of 10 Hz.
      -
      Step 3. The interrupt handler is set up in such a way that the first operation is the appointed GPIO pin toggle.
      -
      Step 4. The time difference between the rising edge of the square pulse from the signal generator and the rising edge at the output GPIO pin can be considered the wakeup time.
    • Scenario 2—Backup mode:
      -
      Step 1. The wakeup source is configured to react on the external interrupt from the GPIO pin connected to the signal generator.
      -
      Step 2. The external signal generator is set to generate square pulses of 10 Hz.
      -
      Step 3. As the microcontroller undergoes a reset vector, the GPIO pin toggle is set as the very first operation in the main() function, immediately after the GPIO configuration. As the test software did not contain any major variables, the time for initialization of the “.bss” section can be neglected.
      -
      Step 4. The time difference between the rising edge of the square pulse from the signal generator and the rising edge at the output GPIO pin can be considered the wakeup time.

4. Results

4.1. Dependence of Energy Consumption on the Operating Frequency

The platform’s power consumption depends linearly on the frequency at a fixed supply voltage (Figure 12). The constant, which is independent of the frequency of the processor energy consumption, is approximately 130 mW. The slope coefficients of the linear dependencies of the energy consumption on the frequency are shown in the figure. Using the low-power modes of the processor saves up to 60% of energy. This advantage is most noticeable when the processor is running at maximum frequency.

4.2. Time Spent by the Operating System to Perform Functions Related to the Rescheduling and Dispatching Tasks

The measurement technique is described in detail in Section 3.3, ’Time spent by the operating system to perform functions related to rescheduling and dispatching tasks.’ The summary in Table 2 characterizes the main reactivity indicators of the operating system on the ‘Boryviter 0.1’ platform. In addition to reactivity indicators, the table contains the results of measuring operations with a nonblocking mutex (’take’, ’give’).
Due to the specifics of the ARM Cortex-M computing architecture, which has two independent instruction counters consisting of a full Program Counter (PC) and an “emulated” Link Register (LR), the computer demonstrates sufficiently high reactivity indicators. FreeRTOS effectively supports the ARM Cortex-M architecture, as it does not distinguish between interrupt handling and normal functions. It has been experimentally confirmed that with cooperative dispatching, the execution time of the function taskYield() does not depend on the number of tasks in the system, as the FreeRTOS OS implements the round-robin dispatching mechanism for queued tasks.

4.3. Time Spent Entering and Leaving the Low-Power Modes (LPMs)

A typical oscillogram of the decrease in power consumption over time after execution of the command to enter the “Wait” LPM is shown in Figure 13.
The following Figure 14 illustrates the measurement view of the delay in execution of the first command of the interrupt handler after receiving an external interrupt when the processor was in “Sleep” LPM.
Table 3 summarizes the results of the measurements of the integral indicators that characterize the practicality of using the LPM modes for saving energy.
There are two main characteristics; the wake-up delays characterize the time required for the processor to fully exit sleep mode, while the break-even times are the summed delays for wake-up and transition to LPM, where the latter characterizes time required for the processor to transition from “Active” mode to “Sleep” mode.

5. Discussion

The data presented above confirm the possibility of experimentally determining the following quantitative indicators characterizing the operation of the computing platform under the conditions of time and energy constraints that exist in the onboard avionics of a UAV:
  • Dependence of the power consumption on the clock frequency for both active mode and low-power modes.
  • Overhead costs of the operating system to support multitasking, namely, delays in the execution of the scheduler and dispatcher operations of the operating system for the implementation of cooperative and preemptive dispatching.
  • Break-even and wake-up times when using low-power modes.
Practical application. Below, we discuss the possibilities for practical application of the results obtained in this article. We consider the scenario when there is a need for the following requirements in the hardware and software design stages of a UAV mission computer:
  • Ensuring that the mission computer functions in an energy-efficient way, i.e., spending the minimum possible electrical energy on its operation.
  • Guaranteeing that the required amount of computational work will be completed within the established time frame.
  • Ensuring that the reaction time to external events will not exceed the established threshold required by the end-application (mission) limits.
Then, in the list of possible design solutions, one or both of the following must be selected:
  • Set the clock frequency of the processor so as to be sufficient to guarantee the specified limits.
  • Apply a software solution to enable one of the existing low-power modes.
Of course, the use of software algorithms to manage power-saving modes has undoubted advantages in terms of flexibility. Nevertheless, the possibility of determining the processor’s clock frequency is sufficient for practical use, and should not be neglected.
We do not consider “Backup” mode here, as it requires a complete processor restart, is characterized by sufficiently large payback time requirements, and requires a completely different software architecture to be applied.
Algorithm design. The results obtained in this article make it possible to design algorithms and energy-saving mechanisms for the UAV mission computer as a solution to an optimization problem. The optimization criterion is the minimum power consumption of the mission computer in various power-saving modes:
P ( η ) = m i n ( P L F ( η ) , P S l e e p ( η ) , P W a i t ( η ) )
where η = i = 1 N T i D i is the relative cost in terms of processor time that is sufficient to ensure real-time constraints and P L F ( η ) , P S l e e p ( η ) , P W a i t ( η ) is the energy consumption required for operation of the mission computer when applying the low-frequency mode (LF) or software-defined transitions to “Sleep” and “Wait” modes with a return to active mode upon external/internal interruption.
Then, when using each of the low-power modes, the average power consumption will not be greater than during continuous operation of the processor at the maximum frequency. The relative part of the energy savings ( μ ) for the three energy-saving modes of depends on the processor load factor η , and in the case of an ideal mission computer is calculated as μ = 1 η .
The linear dependencies of the consumed electric power for the real computer modes on the frequency can be summarized in the form of the following equation:
N m ( f ) = N 0 + a m f
where the m modes take the following values: m { A c t i v e , S l e e p , W a i t } . As a result, we obtain N 0 = 120 mWt , a A c t i v e = 1.07 mWt MHz , a S l e e p = 0.46 mWt MHz , a W a i t = 0.20 mWt MHz from Section 4.1 (see Figure 11).
Thus, to answer the question of how much energy we can save, the relative part of the energy savings can be calculated for a real computer using the following equations:
μ L F ( η ) = a A c t i v e f m a x ( 1 η ) N 0 + a A c t i v e f m a x ,
μ S l e e p ( η ) = f m a x ( 1 η ) ( a A c t i v e a S l e e p ) N 0 + a A c t i v e f m a x ,
μ W a i t ( η ) = f m a x ( 1 η ) ( a A c t i v e a W a i t ) N 0 + a A c t i v e f m a x .
Figure 15 illustrates the results of calculating energy savings using energy-saving modes. Limiting the processor’s clock frequency in the design stage is most beneficial if the system has excessive computing power. Flexible software-controlled methods for switching between “Sleep” and “Wait” modes do not provide such benefits. However, they have the key advantage of adapting to specific onboard situations. The estimates of system reactivity in different modes of operation and operating system overheads for multitasking support obtained in this article make it possible to consider overheads for operating system operations.

6. Conclusions

The main goal of this work was to develop and test an experimental search technique to find a compromise between the required reactivity of the real-time system of the mission computer of a UAV and its electrical energy consumption.
The technique was approved using the authors’ ‘Boryviter 0.1’ computing platform, which was implemented on the ATSAMV71 microprocessor operating under the control of the FreeRTOS open operating system. This dual-purpose platform is intended for use in UAVs and CubeSat-class nanosatellites. The technique is based on the system model. The system model is a power-state machine that comprehensively characterizes the relationship between energy consumption and reactivity. We define three types of models that are needed to fill this system model, which depend on the clock frequency:
  • The electrical energy consumed in the active and power-saving modes of the onboard computer.
  • The time spent by the operating system to perform functions related to rescheduling and dispatching tasks; we have considered all three possible cases when the OS performs rescheduling and dispatching: cooperative dispatching, crowding out dispatching after an interrupt from the system timer, and external interrupts.
  • The time spent to entering energy-saving mode and return to active mode after an external event (interruption) that requires the system to wake up.
Then, we determined the measurement techniques for obtaining the dependencies mentioned above. As the results of this work, we have presented a generalization of the experimental results and quantitative estimates of the measured characteristics for the ‘Boryviter 0.1’ computing platform.
We consider the following to be the scientific novelty of this work:
  • The task of finding a compromise between the reactivity and power consumption of the onboard computer is formulated through a representation in the form of a system model consisting of a power state machine.
  • The developed technique for measuring the time spent to push dispatching after an interruption from the system timer and to process an external interruption allows these costs to be quickly and accurately determined.
  • The proposed time measurement technique for cooperative dispatching is fast and accurate; in addition, it is scalable, allowing the system’s behavior to be determined with an arbitrary number of tasks.
As a practical result, this article substantiates the conclusion that using a real-time operating system (FreeRTOS) in the authors’ ‘Boryviter 0.1’ computing platform, fully meets the task of quickly adapting the computing context to changing external factors (e.g., interrupt-driven UAV avionics signals) and the required volume of calculations.
A limitation of our work is a certain idealization of measurement modes when the influence of external factors was considered separately. For practical application, it is necessary to check the adequacy of the obtained mathematical dependencies in the case of a more realistic picture of the existence of many practical tasks inherent in a typical set of calculations when using UAVs. Such practical and real-time deviations could be connected to avionics faults, external signals arrival frequency, etc.
In addition to checking the adequacy of the mathematical models obtained in this article, we plan to investigate our computing platform’s reactivity and energy consumption if the component-oriented framework F´ (F Prime) from NASA is used to develop onboard software. We plan to use this to allow us to quickly develop and deploy UAV and satellite mission computer software. Potentially, it could also be used in software for other avionics parts. This framework is available in open access for re-use, although it has a relatively high entry threshold. In addition, it provides mechanisms for component-oriented development, making it easier to solve common problems.

Author Contributions

Conceptualization, O.L. and I.T.; methodology, O.L.; software, O.L.; validation, L.V. and O.L.; formal analysis, O.L. and V.C.; investigation, O.L.; resources, L.V.; data curation, I.T.; writing—original draft preparation, L.V.; writing—review and editing, O.L. and I.T.; visualization, L.V.; supervision, I.T. and V.C. All authors have read and agreed to the published version of the manuscript.

Funding

This research was carried out within the frame and budget of the national Ukrainian grant project NRFU.2023.04/0143—“Experimental development and validation of the on-board computer of a dual-purpose unmanned aerial vehicle”.

Data Availability Statement

All archived datasets analyzed and generated during the study, as well as the source code for the experiments, can be obtained upon request.

Acknowledgments

The authors acknowledge the help of the engineering company EKTOS-UKRAINE LLC for their support in borrowing hardware platforms and helping with the setup and fine-tuning of the toolchain. Visit https://ektos.net/ for more details.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. Global UAV market share by UAV class (2022). Source: Fortune Business Insights [6].
Figure 1. Global UAV market share by UAV class (2022). Source: Fortune Business Insights [6].
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Figure 2. A typical build-up of a UAV (avionics, batteries, servos, IMUs.
Figure 2. A typical build-up of a UAV (avionics, batteries, servos, IMUs.
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Figure 3. Typical UAV avionics structure [11].
Figure 3. Typical UAV avionics structure [11].
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Figure 4. The ‘Boryviter 0.1’ (eng. Falco) mission computer, developed by Falco Engineering (https://www.falco.engineering/).
Figure 4. The ‘Boryviter 0.1’ (eng. Falco) mission computer, developed by Falco Engineering (https://www.falco.engineering/).
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Figure 5. A ‘Boryviter 0.1’ ATSAMV71Q21 microcontroller.
Figure 5. A ‘Boryviter 0.1’ ATSAMV71Q21 microcontroller.
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Figure 6. Power state machine of the ATSAMV71 microcontroller. The initial state is Active mode. Transitions ([1], [3], [5]) characterize the time needed to enter the energy-saving and low-power modes, while transitions ([2], [4], [6]) are the time required to restore active mode after an external interruption.
Figure 6. Power state machine of the ATSAMV71 microcontroller. The initial state is Active mode. Transitions ([1], [3], [5]) characterize the time needed to enter the energy-saving and low-power modes, while transitions ([2], [4], [6]) are the time required to restore active mode after an external interruption.
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Figure 7. Connection of the ‘Boryviter 0.1’ (eng. Falco) mission computer to the laptop used for measurements.
Figure 7. Connection of the ‘Boryviter 0.1’ (eng. Falco) mission computer to the laptop used for measurements.
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Figure 8. Measurement equipment used for the experiment.
Figure 8. Measurement equipment used for the experiment.
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Figure 9. Test bench connection diagram for time measurements of transitions ([1], [3], [5]) from the power state machine.
Figure 9. Test bench connection diagram for time measurements of transitions ([1], [3], [5]) from the power state machine.
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Figure 10. Test bench connection diagram for time measurements of the transitions ([2], [4], [6]) from the power state machine.
Figure 10. Test bench connection diagram for time measurements of the transitions ([2], [4], [6]) from the power state machine.
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Figure 11. Example of the obtained dependence of the actual execution time on the iteration number.
Figure 11. Example of the obtained dependence of the actual execution time on the iteration number.
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Figure 12. Dependence of the power consumption of the platform on the frequency in different operating modes of the computer and a fixed supply voltage.
Figure 12. Dependence of the power consumption of the platform on the frequency in different operating modes of the computer and a fixed supply voltage.
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Figure 13. Entering “Wait” mode @ 100 MHz. Current consumption curve. Rough duration = 150 ± 10 uS. C1 (yellow) is a command for entering LPM and C2 (pink) is the current consumption of the microcontroller.
Figure 13. Entering “Wait” mode @ 100 MHz. Current consumption curve. Rough duration = 150 ± 10 uS. C1 (yellow) is a command for entering LPM and C2 (pink) is the current consumption of the microcontroller.
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Figure 14. Leaving LPM timing measurements for “Sleep” mode @ 30 MHz. C1—External signal generator pulse, C2—GPIO pin toggle after wakeup, C3—mathematical sum of the time between the rising edges of the corresponding pulses = wakeup time.
Figure 14. Leaving LPM timing measurements for “Sleep” mode @ 30 MHz. C1—External signal generator pulse, C2—GPIO pin toggle after wakeup, C3—mathematical sum of the time between the rising edges of the corresponding pulses = wakeup time.
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Figure 15. Optimistic assessment of the possibility of energy savings due to software control of computer operating modes.
Figure 15. Optimistic assessment of the possibility of energy savings due to software control of computer operating modes.
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Table 1. Key characteristics and low-power modes (LPM) of popular series of 32-bit microcontrollers (F—available onboard Flash memory; R—available onboard RAM).
Table 1. Key characteristics and low-power modes (LPM) of popular series of 32-bit microcontrollers (F—available onboard Flash memory; R—available onboard RAM).
MCU FamilyMemoriesTemperatureVoltageLow Power Modes
ATSAMV7x (Cortex-M7)F = 2 Mb, R = 384 Kb−40/+1251.8–3.6 VdcSleep, Wait, Backup
PIC32CZ (MIPS)F = 2 Mb, R = 512 Kb−40/+1052.5–3.6 VdcSleep, Wait, Backup
PIC32MX (MIPS)F = 512 Kb, R = 128 Kb−40/+1052.3–3.6 VdcSleep, Idle
STM32H7 (Cortex-M7)F = 1 Mb, R = 564 Kb−40/+1251.62–3.6 VdcSleep, Stop, Standby
STM32F7 (Cortex-M7)F = 2 Mb, R = 512 Kb−40/+1051.7–3.6 VdcSleep, Stop, Standby
iMX.RT1024 (Cortex-M7)F = 4 Mb, R = 256 Kb−40/+1053.0–3.6 VdcLPR (24 MHz), Sleep
Table 2. Summary table of the time spent by the operating system to perform functions related to the rescheduling and dispatching tasks.
Table 2. Summary table of the time spent by the operating system to perform functions related to the rescheduling and dispatching tasks.
Frequency, MHztaskYield() Latency t = Lat Y ( f ) , uSSystem Tick Interrupt Latency t = Lat T ( f ) , uSExternal Interrupt Latency t = Lat e xt ( f ) , uSCapturing and Releasing Non-Blocking Mutexes Latency, uS
307.274.026.427.73
1002.161.231.952.34
3000.720.470.650.78
Table 3. Wake-up delays and break-even times (uncertainty no more than 10%).
Table 3. Wake-up delays and break-even times (uncertainty no more than 10%).
ModeSleep, uSWait, uSBackup, uS
FrequencyWake-Up DelaysBreak-Even TimeWake-Up DelaysBreak-Even TimeWake-Up DelaysBreak-Even Time
30 MHz5451800195050006500
100 MHz1.7311228138850006500
300 MHz0.62110525550006500
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Liubimov, O.; Turkin, I.; Cheranovskiy, V.; Volobuieva, L. UAV Mission Computer Operation Mode Optimization Focusing on Computational Energy Efficiency and System Responsiveness. Computation 2024, 12, 235. https://doi.org/10.3390/computation12120235

AMA Style

Liubimov O, Turkin I, Cheranovskiy V, Volobuieva L. UAV Mission Computer Operation Mode Optimization Focusing on Computational Energy Efficiency and System Responsiveness. Computation. 2024; 12(12):235. https://doi.org/10.3390/computation12120235

Chicago/Turabian Style

Liubimov, Oleksandr, Ihor Turkin, Valeriy Cheranovskiy, and Lina Volobuieva. 2024. "UAV Mission Computer Operation Mode Optimization Focusing on Computational Energy Efficiency and System Responsiveness" Computation 12, no. 12: 235. https://doi.org/10.3390/computation12120235

APA Style

Liubimov, O., Turkin, I., Cheranovskiy, V., & Volobuieva, L. (2024). UAV Mission Computer Operation Mode Optimization Focusing on Computational Energy Efficiency and System Responsiveness. Computation, 12(12), 235. https://doi.org/10.3390/computation12120235

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