SnO Nanosheet Transistor with Remarkably High Hole Effective Mobility and More than Six Orders of Magnitude On-Current/Off-Current

Abstract

Using novel SiO₂ surface passivation and ultraviolet (UV) light anneal, a 12 nm thick SnO p-type FET (pFET) shows hole effective mobilities (µ_eff) of more than 100 cm²/V·s and 31.1 cm²/V·s at hole densities (Q_h) of 1 × 10¹¹ and 5 × 10¹² cm⁻², respectively. To further improve the on-current/off-current (I_ON/I_OFF), an ultra-thin 7 nm thick SnO nanosheet pFET shows a record-breaking I_ON/I_OFF of 6.9 × 10⁶ and remarkable µ_eff values of ~70 cm²/V·s and 20.7 cm²/V·s at Q_h of 1 × 10¹¹ cm⁻² and 5 × 10¹² cm⁻², respectively. This is the first report of an oxide semiconductor transistor achieving a hole effective mobility µ_eff that reaches 20% of that in single-crystal Si pFETs at an ultra-thin body thickness of 7 nm. In sharp contrast, the control SnO nanosheet pFET without surface passivation or UV anneal exhibits a small I_ON/I_OFF of 1.8 × 10⁴ and a µ_eff of only 6.1 cm²/V·s at 5 × 10¹² cm⁻² Q_h. The enhanced SnO pFET performance is attributed to reduced defects and improved quality in the SnO channel, as confirmed by decreased charges related to sub-threshold swing (SS) and threshold voltage (Vth) shift. Such a large improvement is further supported by the increased Sn²⁺ after passivation and UV anneal, as evidenced by X-ray photoelectron spectroscopy (XPS) analysis. The I_ON/I_OFF ratio exceeding six orders of magnitude, remarkably high hole µ_eff, and excellent two-month stability demonstrate that this pFET is a strong candidate for integration with SnON nFETs in next-generation ultra-high-definition displays and monolithic three-dimensional integrated circuits (3D ICs).

1. Introduction

Oxide semiconductors possess unique carrier transport characteristics [1]. The SnO₂ n-type field-effect transistor (nFET) has achieved a superb high field-effect mobility (µ_FE) [2] close to the single-crystal Si nanosheet nFET and phonon-scattering-limited two-dimensional (2D) MoS₂ nFETs [3,4]. However, p-type FETs (pFETs) are indispensable in forming low-DC-power Complementary Metal–Oxide–Semiconductor (CMOS) logic integrated circuits (ICs). The development of p-channel oxide TFTs remains challenging, as hole transport is highly sensitive to film quality and can be easily degraded by structural defects [5]. Materials such as tin monoxide (SnO), copper oxide (Cu₂O), and nickel oxide (NiO) have emerged as promising p-type channel candidates due to their intrinsic hole conduction properties and compatibility with low-temperature processing. Recent advancements have focused on enhancing hole mobility through interface engineering, bilayer structures, and the incorporation of high-κ dielectrics. In particular, SnO-based pFETs have demonstrated notable improvements in hole mobility and thermal stability, enabled by advanced deposition techniques and optimized interface quality. For example, low-temperature processing has facilitated the integration of SnO pFETs into flexible electronic platforms [6]. Che et al. obtained a µ_FE of 6.13–7.24 cm²/V·s without using high-temperature post-anneal and improved sub-threshold swing characteristics by reducing surface defect states using backchannel passivation with an Al₂O₃ film [7]. Cu₂O has also attracted interest for its inherent p-type conductivity and suitability for transparent electronics. Innovations in deposition techniques, such as aerosol-assisted chemical vapor deposition (AACVD), have enabled the fabrication of high-quality Cu₂O thin films [8]. NiO, known for its wide bandgap and chemical stability, has been explored as another viable p-type semiconductor. Liu et al. reported a remarkable 60-fold enhancement in hole mobility from 0.07 to 4.4 cm²/V·s, primarily attributed to the high areal capacitance of the Al₂O₃ dielectric and the high-quality NiO_x/Al₂O₃ interface, compared to conventional SiO₂-based dielectrics [9]. Among the various oxide semiconductors, SnO has garnered significant attention due to its small hole effective mass [10,11,12,13,14,15,16], which originates from the strong orbital overlap between Sn 5s and O 2p states near the valence band edge [13,14]. Nevertheless, the development of high-performance SnO pFETs is hindered by oxide defects and the co-existence of n-type SnO_2−x [13]. In addition, SnO faces practical challenges such as sensitivity to moisture, stoichiometry control, and unavoidable oxygen vacancies, which may form nonstoichiometric phases such as Sn₂O₃ or Sn₃O₄ [15].

In this work, the record-breaking performance of an oxide-semiconductor pFET is reported, where the SnO pFET achieves a record-breaking on-current/off-current (I_ON/I_OFF) of 6.9 × 10⁶. Such a high I_ON/I_OFF is mandatory for low-DC-power ICs. Furthermore, the device exhibits remarkably high effective mobilities (µ_eff) of ~70 cm²/V·s and 20.7 cm²/V·s at hole densities (Q_h) of 1 × 10¹¹ cm⁻² and 5 × 10¹² cm⁻², respectively. This record high performance among oxide semiconductor pFETs is attributed to the successful passivation of SnO surface defects and ultraviolet (UV) light anneal [16,17]. The passivation layer not only protects the SnO channel from moisture degradation, but also minimizes defect states, resulting in improved carrier transport. This excellent SnO pFET can be further integrated with the record-high-mobility SnON nFET [2] on the back end of ICs, forming low-DC-power CMOS logic ICs and being useful for monolithic three-dimensional (M3D) ICs.

2. Materials and Methods

Four-inch p+ Si substrates were used. Then, 50 nm thick TiN was deposited and used as the gate electrode. The TiN was sputtered using a DC plasma source of 800 W, with an Ar flow rate of 100 sccm and a N₂ flow rate of 5 sccm. Electron beam evaporation was employed to deposit a 45 nm thick HfO₂ film and 6 nm thick SiO₂ as the gate dielectric, with the deposition rate controlled at 0.2 Å/s. After deposition, the device underwent thermal anneal in a N₂ environment at 400 °C for 1 h. After anneal, 7 nm thick SnO was sputtered using a DC plasma source at 25 W, with an Ar flow rate of 24 sccm, an O₂ flow rate of 8 sccm, a chamber pressure of 7.6 mTorr, and a deposition rate of 0.1 Å/s. The device was annealed using rapid thermal anneal (RTA) at 200 °C in a N₂ environment for 30 s. Next, 30 nm thick Ni was deposited on the SnO and served as the source and drain electrodes. Additionally, passivation layers consisting of a 5 nm thick SiO₂ film, a 10 nm thick HfO₂ film, and a 3 nm thick SiO₂ film were deposited. The device had a channel length of 50 μm and a channel width of 500 μm. Finally, UV anneal was performed with 254 nm at a 79 mW/cm² power and 185 nm at an 11 mW/cm² power for 10 min. First-principles quantum mechanical calculations were conducted to study the electronic properties of SnO using Quantum-espresso, with both the generalized gradient approximation (GGA) and local-density approximations plus the Hubbard potential U (LDA + U) method.

3. Results

SnO has a lead oxide structure and crystallizes in the tetragonal P4/nmm space group. The structure is 2D and consists of one SnO sheet oriented in the (0, 0, 1) direction. In the SnO unit cell, each Sn²⁺ is bonded in a four-coordinate geometry to four equivalent O²⁻ atoms. Each O²⁻ is bonded to four equivalent Sn²⁺ atoms to form a mixture of corner- and edge-sharing OSn₄ tetrahedra. First-principles quantum mechanical calculations using Quantum-espresso are used to study the band structure of SnO (Figure 1) and calculate the effective mass of the hole (m_h*). SnO bandgaps of 0.62 eV and 0.18 m₀ and an effective mass of the hole (m_h*) at Γ points are obtained, as shown in

Table 1. Comparison table of p-type metal–oxide–semiconductors.

P-Type	Eg	Hole Effective Mass (mh*)
SnO	0.62 eV (Indirect)	0.18 m0
Cu2O [13]	2.1 eV (Direct)	0.65 m0
NiO [18]	3.6 eV (Indirect)	0.45 m0

.

Figure 2a represents oxygen vacancy formation or the dangling bonds in the SnO structure during film processing caused by a low oxygen partial pressure while using a metallic Sn target. Moreover, insufficient oxygen during deposition or anneal can prevent the complete oxidation of Sn, leaving excess Sn atoms that may occupy interstitial sites, as shown in Figure 2b. Figure 2c,d show that with SiO₂ passivation, the oxygen dangling bonds of SiO₂ at the SnO/SiO₂ interface could potentially interact with oxygen-deficient sites in SnO. In Figure 2d, a SiO_x transition layer forms at the interface between SiO₂ and SnO. This SiO_x originates from the low-temperature-deposited SiO₂ side, either due to oxygen diffusion or the partial reduction of SiO₂ during processing. The interface contains various charges, as follows: oxide-trapped charges deep in SiO₂, fixed-oxide charges near the interface, and interface-trapped charges at the SiO_x/SnO boundary. These charges can affect device behavior by shifting the threshold voltage and degrading carrier mobility. Such dielectric and interface charges have been well studied in metal/SiO₂/Si MOS capacitors, which cause Coulomb scattering and FET mobility degradation in 2D material FETs.

Figure 3a,b show a schematic structural diagram and a transmission electron microscope (TEM) cross-sectional image of the passivated SnO device, respectively. From the TEM, the thickness of SnO is 7 nm, the bottom interfacial SiO₂ is 6 nm, and the top passivated SiO₂/HfO₂/SiO₂ layers are 5, 10, and 3 nm, respectively. The TEM image in Figure 3b was taken after anneal. Interface roughness can increase hole scattering, especially at a high charge density or effective field [19]. Interface charges at both the top and bottom SnO interfaces result in mobility degradation and a poor sub-threshold performance. To lower interface charge scattering, a 6 nm thick SiO₂ layer is deposited in between the channel SnO and the gate dielectric HfO₂ to reduce remote phonon scattering from the high-κ gate dielectric. After the deposition of HfO₂ and SiO₂, the device undergoes thermal anneal in a N₂ environment at 400 °C for 1 h before SnO channel deposition. Thermal anneal at 400 °C in N₂ improves the electrical quality of the HfO₂ and SiO₂ dielectrics, reduces interface trap states, and enhances mobility. To further lower top interface charge scattering, SiO₂ passivation is also applied.

Figure 4 shows the capacitance density versus voltage (C-V) and current density versus voltage (J-V) characteristics of the Ni/6 nm SiO₂/45 nm HfO₂/TaN metal–insulator–metal (MIM) structure, which was made using the same mask as the SnO pFET. The capacitance density reaches 260 nF/cm², which gives an overall high dielectric constant (high-κ) value of 15.0. The gate leakage current is only 4 × 10⁻⁶ A/cm², attributed to the high-κ gate dielectric. The gate leakage current of metal-gate/high-κ/SnO is significantly higher than that in standard metal-gate/high-κ/single-crystal Si Complementary Metal–Oxide–Semiconductor (CMOS) FETs [20]. This is because the former is made at a limited temperature of 400 °C for backend-of-line (BEOL) processes while the latter is fabricated at 1000 °C. The limited thermal budget causes defects and trap-assisted leakage in the high-κ gate dielectric. To further decrease gate leakage current under low-temperature processing conditions, atomic layer deposition (ALD) can be employed; however, this involves a relatively long process time.

The FET’s µ_FE and µ_eff are obtained under a small drain voltage (V_d) [21], as follows:

$${\mu }_{FE}={\displaystyle \frac{L}{W}}{\displaystyle \frac{1}{C_{OX}{V}_d}}{\displaystyle \frac{{dI}_d}{{dV}_g}}{\mid }_{small V_d}={\displaystyle \frac{L}{W}}{\displaystyle \frac{1}{C_{OX}{V}_d}}{g}_m{\mid }_{small V_{d }},$$

(1)

$${\mu }_{eff}={\displaystyle \frac{L}{W}}{\displaystyle \frac{g_d}{\mathrm{q}{N}_{inv}}}{\mid }_{small V_d}={\displaystyle \frac{L}{W}}{\displaystyle \frac{g_d}{C_{OX}{(V}_{gs}-V_{th})}},$$

(2)

where L and W are the channel length and width, C_ox is the gate capacitance per unit area, gm is the transconductance, q_Ninv is the total induced Q_h in the channel, and g_d is the drain conductance, respectively. Here, µ_eff is essential for transistor modeling and crucial for IC design.

Figure 5a,b present the drain current versus V_d (|I_d| − V_d) characteristics of nanosheet FETs, with 10 and 12 nm thick SnO channels, respectively. Both transistors show an increase in |I_d| with an increasingly negative gate voltage (V_g), which indicates the pFET’s behavior. A good transistor pinch off is observed at a positive V_g. Additionally, the output |I_d| is higher for the thicker SnO channel, suggesting enhanced hole conduction in the thicker SnO pFET. In Figure 5, the drain current continues to increase in the saturation regime. This increasing trend is not due to the gate leakage current, which is significantly lower than the drain current. Instead, it is attributed to the thicker SnO channel, which cannot be fully depleted by the gate electric field. To further reduce the gate leakage current under low-temperature processing conditions, ALD is a useful technique, although it involves a relatively long processing time.

Figure 6a–c show the |I_d| − V_g, µ_FE − V_g, and µ_eff − Q_h characteristics for 10 and 12 nm thick SnO pFETs. The 12 nm thick SnO pFET shows a superb transistor hole µ_eff of more than 100 cm²/V·s and 31.1 cm²/V·s at a Q_h of 1 × 10¹¹ and 5 × 10¹² cm⁻², respectively. At a high 5 × 10¹² cm⁻² Q_h, it is crucial to notice that the hole µ_eff increases from 27.3 cm²/V·s for the 10 nm thick SnO to 31.1 cm²/V·s for the 12 nm channel thickness. Although a higher µ_eff and output |I_d| are obtained with the thicker SnO pFETs, there is a significant degradation in the I_OFF. The large I_OFF causes too high off-state leakage current and DC power consumption, which is intolerant for modern ICs with multi-billions of FETs. The high I_OFF is attributed to the inability of the gate and surface potentials to fully deplete the thicker SnO channel. It is also noted that UV anneal does not alter the SnO film thickness, as confirmed by similar experiments performed on both SnO₂ nFETs [16] and SnO pFETs [17].

Figure 7a–c show the |I_d| − V_d characteristics for thinner 7 nm thick SnO pFETs under different device conditions, with and without passivation and with and without UV anneal. The increase in I_d| with more −V_g confirms the p-type behavior of the FETs. At a V_g of −2 V, the output |I_d| increases from the control device to the device with surface passivation and the pFET with both passivation and UV anneal. The |I_d| curves do not increase monotonically with V_G, which is due to the roll off of µ_eff with an increasing Q_h [19].

Figure 8a–c present the |I_d| − V_g characteristics of the 7 nm thick SnO device with and without passivation and with and without UV anneal. At V_d = −0.1 V, the SnO pFET with a passivation layer and UV anneal shows the highest |I_d|. Such a higher |I_d| is important for a higher-speed IC device.

Figure 9a shows the comparison of the |I_d| − V_g characteristics for 7 nm thick SnO pFETs without UV anneal. The non-passivated control device exhibits an I_ON/I_OFF of 1.8 × 10⁴, whereas the passivated device achieves a large 1.1 × 10⁶. The threshold voltages (Vth) extracted from the extrapolation of the I_d linear region [22] are −0.1 and 0.2 V for the FETs without and with passivation, respectively. The two-orders-of-magnitude I_ON/I_OFF improvement suggests that the passivation effectively isolates the channel surface from reacting with moisture. The SnO surface reaction with moisture further forms charged defects, which change the Vth and decrease the I_ON. Figure 9b shows the comparison of the |I_d| − V_g characteristics between the control FET and the best-performing FET with passivation and UV anneal. The UV anneal further increases the I_ON/I_OFF from 1.1 × 10⁶ to 6.9 × 10⁶. Such an improvement is attributed to the UV anneal effectively enhancing channel quality, thereby resulting in a superior electrical performance [17].

Figure 10a,b illustrate the µ_FE − V_g and µ_eff − Q_h characteristics for 7 nm thick SnO pFETs, respectively. The peak µ_FE values increase from 5.8 and 14.3 to 20.3 cm²/V·s. The µ_eff values decrease from ~70 m²/V·s with an increasing Q_h. At a Q_h of 5 × 10¹² cm⁻², µ_eff increases from 6.1 and 14.7 to 20.7 cm²/V·s. This is the first time that the hole µ_eff of an oxide semiconductor has reached 20% of that of a single-crystal Si pFET at a 7 nm ultra-thin body thickness [23]. This improved pFET performance is due to both passivation and UV anneal, resulting in reduced defects and an improved quality of the SnO channel. Moreover, the interfacial charge trap density (Dit) [24] is calculated, and we find that passivated SnO with UV anneal has a Dit of 4.6 × 10¹² cm⁻² eV⁻¹, close to that of passivated SnO (4.7 × 10¹² cm⁻² eV⁻¹) and better than the SnO (8.2 × 10¹² cm⁻² eV⁻¹). As shown in Figure 10a, the shoulder-like non-smooth µ_FE feature in the 7 nm thick SnO channel is attributed to extra scattering from defects, which can be improved by passivation and UV anneal. The shoulder-like non-smooth µ_FE feature in Figure 6a,b is due to a thicker SnO channel, where gate electric field cannot fully deplete the SnO channel and defects. This is confirmed by the higher I_ON/I_OFF in thicker SnO channel pFETs.

Figure 11 presents the |I_d| − V_g characteristics of 7 nm thick SnO pFETs as-fabricated and after two months of exposure to air. The control device shows significant deterioration after exposure to air, and the µ_FE decreases from 5.8 to 1.5 cm²/V·s after 2 months. In contrast, the device with passivation exhibits minimal changes in electrical performance as follows: the passivated and non-UV annealed device decreases from 14.3 to 12.3 cm²/V·s, and the passivated and UV-annealed device decreases slightly from 20.3 to 19.2 cm²/V·s. This comparison highlights the significant impact of passivation and channel material quality on device performance. The device shown in Figure 11a is not encapsulated to show the aging effect. The unpassivated control device exhibits significant degradation after two months of air exposure, with the μ_FE dropping from 5.8 to 1.5 cm²/V·s. In contrast, the passivated device only shows a minimal decline from 20.3 to 19.2 cm²/V·s, highlighting the strong protective role of a passivation approach. For future practical integration into ICs, external encapsulation using SiN will be applied to top Cu and low-κ interconnecting BEOL layers to improve long-term stability. However, SiO₂ passivation directly on SnO pFETs must still be applied to prevent any moisture-related degradation during BEOL processes.

To further understand such an excellent performance, the SnO channels are characterized by X-ray photoelectron spectroscopy (XPS) [25,26]. The XPS results are calibrated using the C1s binding energy peak at 284.4 eV as a reference. Figure 12 shows the XPS Sn 3d_5/2 peaks for SnO pFETs under different conditions. The Sn 3d_5/2 peaks can be categorized into the following three types: Sn⁰ at 484.1 eV, Sn²⁺ at 486.3 eV, and Sn⁴⁺ at 486.9 eV [16,27].

Table 2. Summary of Sn3d_5/2 proportions.

Sample	Sn0	Sn2+	Sn4+
SnO	7.1%	65.2%	27.7%
SnO_UV	6.3%	62.4%	31.3%
Passivated SnO	9.3%	68.9%	21.8%
Passivated SnO_UV	9.7%	73.8%	16.5%

summarizes the deconvoluted Sn 3d_5/2 XPS of Sn⁰, Sn²⁺, and Sn⁴⁺. Because the lattice energies of SnO₂ (11,807 kJ mol⁻¹) are much higher than those of SnO (3652 kJ mol⁻¹), surface SnO can react with oxygen and moisture in air to form SnO_1+x [28]. Consequently, when passivation and UV anneal are applied, the proportion of Sn²⁺ increases from 65.2% to 73.8% and Sn⁴⁺ decreases from 27.7% to 16.5%.

Table 3. Comparison of SnO pFET performance.

Refs.	Channel	IOFF (A/μm)	ION/IOFF	SS (mV/dec)	µFE (cm2/V·s)	µeff (cm2/V·s)	Tech. and Anneal
This work	SnO	5.6 × 10−14	6.9 × 106	231	20.3	20.7	200 °C RTA SiO2 passivation UV anneal
[12]	SnO	-	~102	-	1.3	-	200 °C RTA
[10]	SnO	~10−12	6 × 103	7630	6.75	-	180 °C 30 min
[11]	SnO	~4 × 10−10	>103	760	10.83	-	160 °C
[30]	SnO	-	2.7 × 102	4600	6	-	300 °C 1 h
[31]	SnO	-	6.54 × 105	150	1.14	-	300 °C 1 h
[32]	SnO	-	2.5 × 103	240.9	38.7	-	175 °C 2 h
[17]	SnO	~2.5 × 10−13	1.05 × 105	274	13.33	13.38	200 °C RTA UV anneal
[33]	Cu2O	-	4.68 × 104	3910	1.11	-	Thermal anneal 800 °C 1 h
[5]	Cu2O	-	4.1 × 106	2350	1.38	-	100 °C 1 h
[34]	NiO	2.75 × 10−7	3.61 × 104	-	1.09	-	200 °C 30 min
[9]	NiO	-	105	250	4.4	-	250 °C
[35]	SnO	-	4.2 × 103	6100	17.2	19.1	300 °C 1 h
[36]	NiO	-	103	2600	1.07	-	-
[37]	NiOx	-	105	700	25	-	UV treatment, 40 min and anneal 350 °C 1 h
[38]	Cu2O	-	3.4 × 102	26,000	0.9	-	700 °C
[39]	Cu2O	-	-	-	4.3 × 10−2	-	650 °C oxidation
[40]	Cu2O	-	102	-	0.16	-	400 °C 30 min
[41]	Ga-doped Cu2O	-	1.22 × 104	7720	0.74	-	800 °C

summarizes the performance comparison between this study and other SnO pFET devices published in the literature. By applying passivation and UV anneal to SnO, the sub-threshold swing (SS) value is improved to 231 mV/dec compared with SnO (358 mV/dec) and passivated SnO (233 mV/dec). Our SnO pFETs provide the best I_ON/I_OFF near seven orders of magnitude, one of the lowest I_OFF, a small SS, and a remarkably high µ_eff for high-speed and for low-power applications. Device reproducibility has been demonstrated in our previous publications [13,17,29]. The μ_eff of 20.7 cm²/V·s is the highest value obtained for a SnO pFET with a typical standard deviation of 3.4 for 10 devices [13] and an I_ON/I_OFF of 6.9 × 10⁶ with a standard deviation of 87. This level of device variability is comparable to that observed in our previously reported SnON nFETs [2].

4. Conclusions

In this study, we investigated the electrical performance and material properties of the following three types of devices: devices without a passivation layer and without UV anneal, devices with a passivation layer but without UV anneal, and devices with both a passivation layer and UV anneal. From XPS, the SnO with a passivation layer and UV anneal showed a reduced Sn⁴⁺ ratio and increased Sn²⁺, which resulted in an I_ON/I_OFF as high as 6.94 × 10⁶ and an effective mobility of up to 20.7 cm²/V·s at a hole density (Q_h) of 5 × 10¹² cm⁻² in the pFET. These results indicate that this nanosheet SnO FET meets the requirements of simple, low-cost, and low-temperature fabrication, and will be useful for future monolithic 3D CFET applications.