Ring-Oscillator with Multiple Transconductors for Linear Analog-to-Digital Conversion

Round 1

Reviewer 1 Report

The paper deals with mostly/fully digital approach for designing an ADC.
1) In this framework, many works have been published despite they have been completely neglected by the authors.
From a quick search,  VCO-based ADC (10.1109/TCSI.2014.2340551
SAR ADC (10.1109/ACCESS.2020.2986949 , 10.1109/ACCESS.2019.2915365 )
and Flash ADC ( 10.1109/TCSI.2013.2268571 , 10.1109/TCSII.2015.2415231 , 10.1109/ACCESS.2017.2766671) or even ADC building blocks (i.e. DAC  10.1109/TCSI.2019.2903464, or comparator ) can be easily found from a rough search using as a key-word fully-digital or fully-synthesizable. 
I assumed that a more deep search would be able to provide the authors (first) and the paper readers (then) a deep understanding of the established literature behind the same topic. On this basis, the presented works could be better defined highlighting pros and contra with the existing solutions. Thus, properly compare your work with the state-of-the-art and add the most relevant works in the comparison table. On this basis the reference list is weak. Please double/triple the number of papers in the reference list. As a hint, the authors may look at the above-suggested papers, the cited paper, and the papers that cited them.

2)The presented work is based on simulation results only. 
On this basis, please avoid and use wisely words such as "validate" or "test" (i.e. "The architecture has been also tested against PVT and mismatch variations"). A circuit validation and test are made by means of measurements.
Please mention in the table of comparison the works based on simulations or measurements in the first row. Works with silicon validations are surely more robust. Therefore, more Montecarlo and corner simulations will increase the robustness of the work. 

3)Please detail better every block in Fig. 10 for the calibration 

4)Most of the usual figure to define the characteristics of an ADC are missing (i.e. INL, DNL) 

5)Please report in the comparison table ALL the main characteristics of an ADC (i.e. VDD, ENOB, INL, DNL are missing)
 
After the paper will be deeply changed to address the above-mentioned point, I would be glad to review it again. 

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Summary: The author proposed a method to mitigate the nonlinearity of the voltage controlled oscillator (VCO) using a current-controlled oscillator (CCO) architecture.  The proposed VCO is a solution to linearize ring-oscillators-based ADCs. The digital part of the ADC is implemented in Verilog-A.

Strength: 
1. The authors propose a new method to linearize the transfer function of a VCO.

2. The proposed VCO technique improves ENOB by 3, as compared to the traditional VCO implementation.

3. The open-loop structure alleviates stringent jitter requirements.

4. PVT variation and its impact on the VCO is also taken into account.

5. The proposed VCO decreases the harmonic distortion of the ADC (HD2, HD3).

 

Weakness: 
1. The authors propose using multiple transconductors to inject current into the ring-oscillator and making sure at least one device operates in the saturation region to maintain linearity.  However, some of transistors can still operate in a non-linear region, and the current injected into the ring-oscillator is the summation of all the transconductor currents.  Therefore, the total current can still be non-linear due to the transconductors operating in a non-linear region. It would be helpful to characterize the distortion contributed by these non-linear transconductors.

2. In figure 2, the authors propose to divide the VCO into a transconductor front end and a current-controlled oscillator (CCO), while making the transfer function of the transconductor a concave curve.  It is not convincing that the front end shown in figure 5 can provide such a concave transfer function. Since the current is still provided by NMOS transistors, it is unclear how different bias conditions would impact the transfer function. It would be helpful to further elaborate on how to generate such a concave IV plot curve.

3. In figure 6(a), node Xoff,N,3 = 230mV. For a 1.2V power supply, it ís a challenge for a 230mV voltage to fully turn on the input NMOS within the op amp (N3 in figure 7) and maintain the operation of the device in the saturation region.  What is the threshold voltage of the NMOS transistor in this case? Or is it designed to operate in subthreshold?

4. The ideal current source on the top and bottom of the diode connected NMOS would consume additional voltage headroom, it would be helpful to replace them with current mirrors so that the swing limitation would be more predictable.  Can you comment further on the choice of a diode connected NMOS instead of the use of current mirrors.

5. Although the authors divide the input voltage swing into three different DC levels (800 mV, 470 mV, 230mV), it ís unclear what the DC input level is for N1, N2, and N3 in Figure 6(a). It would helpful to provide these voltage as well.

6. The authors provide a calibration architecture for the ADC. It is unclear whether the circuit calibration is implemented in the design? How is the the front end circuit made reconfigurable and what additional circuity is needed is unclear based on the schematic of Figure 6?

7. The digital parts of the ring-oscillator ADC are implemented in Verilog-A. It would be better to fully implement the ADC, extracting the parasitic impedances (including the input capacitance), to fully characterize the effect on the performance. Since the oscillator directly connects to the digital back-end, the load of the oscillator can potentially impact the performance of VCO.

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

The authors propose a ring-oscillator with multiple transconductors for linear analog-to-digital conversion in order to mitigate the distortion generated by the non-linearity. While the paper is generally well written I think that the authors need to address the following points:

• In introduction they mention that their approach is "suitable for the newest CMOS processes such as 16-nm or 7-nm". I think that the authors need to elaborate more on that point, since in this process nodes PVT variations could have a great impact.
• Throughout the paper the transistor length seems different than the simulation results. Are the distortion and output spectrum figures obtained with different CMOS technology?
• Please report which 65-nm CMOS process library is used in the paper.
• Regarding figure 9 authors focus on 27 Celsius. Could be possible to elaborate more on this figure, since for example the performance of FF seems to degrade quickly.
• Section 4 needs significant revision. Reader should be able to easily extract the pros and the cons of the proposed approach. Moreover, a detailed comparison with the methods that they mentioned in the table is also needed.

 

Author Response

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Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

The work has been clearly improved.
Despite this, the authors neglect to address my consideration in my former review. 

Reply to point1
The authors replay:''In relation to including fully-synthesizable architectures we have emphasized in the text that our solution is not intended for fully-synthesizable solutions, but for mostly digital solutions with very small amount of analog circuits (in our case the transconductors) suitable both for low voltage supplies and scalable architectures. "
I may understand that the authors may find a trade-off for a specific reason ( maybe to be explicitly mentioned) but the paper clear moves in the fully digital direction so that the suggested more complete scenario should be discussed and referenced for the readers' benefit. 
I would expect the authors would cite much more than the reference I suggested. On the contrary that has neglected my suggestion.
Notice that MDPI has no limits on pages and references.

Replay to point 4 and 5
Any reader interested in reading a paper on ADCs would expect INL and DNL among the other parameters. The authors explained why but they miss reporting such parameters referring to many papers.  
These references have been only reported for the reviewer's benefit but they should be shown to all the paper reader. 
Notice again, that MDPI has no limits on pages and references.

Please add in the acronyms list all those available along with your paper. Adding the new text some have been missing (i.e. NUS that is not even defined as Not-uniform Sampling)
 

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Review on point 1:
What are the sizes of transistors N1, N2, and N3? It would be helpful to identify the largest and smallest transistors.
From the IV plot, current_N2 shows a similar trend as current_N1, it approximately maintains a constant level after the voltage reaches 800 mV.
Can the non-linearity from current_N1 be purely compensated by current_N3 by tuning the sizes of N1 and N3?

Review on point 2:
Is it possible to expand the linear range to full swing by adding more transconductors to the ring oscillator? What is the distortion if the input voltage is below 0.27 V or 0.67 V?

Review on point 3:
In figure 6, it would be helpful to further illustrate at what input range each op amp is fully turned on and provides unit gain.

Review on point 4:
In figure 6, the drain to source voltage of NMOS M2 is 240 mV at DC level. However, the head room introduced from the diode-connected transistor is one threshold voltage.
What is the threshold voltage of M2 in this case?

Review on point 5:
-

Review on point 6:
For Xoff,N,2, how many different predefined values can be fetched from the LUT? What's the range of the predefined values?
Can Xoff,N,1 and Xoff,N,3 also be adjusted?

Review on point 7:
Since a 50 fF load results in a decrease of the SNDR by 1.3 dB, it would be helpful to sweep the load across a larger range of values and plot the SNDR to fully characterize the performance degradation due to the load.

 

 

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

I think that the authors have address my comments and the paper is ready for publication.

Author Response

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Author Response File: Author Response.pdf

Round 3

Reviewer 1 Report

The authors have finally addressed the reviewer point. 

The work is suitable for publication now