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Electronics
Volume 10
Issue 17
10.3390/electronics10172150
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Article

A Method for Selection of Power MOSFETs to Minimize Power Dissipation

by
Utkarsh Jadli
1,*,
Faisal Mohd-Yasin
1,
Hamid Amini Moghadam
1,
Peyush Pande
2,
Mayank Chaturvedi
1 and
Sima Dimitrijev
1
1
Queensland Micro- and Nanotechnology Centre, Griffith University, Brisbane, QLD 4111, Australia
2
Department of Electronics & Communication Engineering, Graphic Era (Deemed to Be University), Dehradun 248002, Uttarakhand, India
*
Author to whom correspondence should be addressed.
Electronics 2021, 10(17), 2150; https://doi.org/10.3390/electronics10172150
Submission received: 26 July 2021 / Revised: 30 August 2021 / Accepted: 31 August 2021 / Published: 3 September 2021
(This article belongs to the Section Power Electronics)
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Abstract

A balance between static and dynamic losses of a power MOSFET is always desirable for accomplishing the maximum efficiency for a specific power converter. The standard semiconductor theory suggests that a minimum power dissipation in a MOSFET can be achieved by selecting a specific device active area. However, for power circuit designers, the active device area is unknown given that only datasheet parameters are available. Hence, in this paper, we propose a simple method, based on semiconductor theory, to select optimum power MOSFET from a family of MOSFETs using only datasheet parameters. By applying this optimization method to the specific power supply circuit under development, power engineers can select the best transistors to yield lowest power losses for the systems under development.
Keywords: dynamic losses; datasheet parameters; optimization; power dissipation; power MOSFET; static losses dynamic losses; datasheet parameters; optimization; power dissipation; power MOSFET; static losses

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MDPI and ACS Style

Jadli, U.; Mohd-Yasin, F.; Moghadam, H.A.; Pande, P.; Chaturvedi, M.; Dimitrijev, S. A Method for Selection of Power MOSFETs to Minimize Power Dissipation. Electronics 2021, 10, 2150. https://doi.org/10.3390/electronics10172150

AMA Style

Jadli U, Mohd-Yasin F, Moghadam HA, Pande P, Chaturvedi M, Dimitrijev S. A Method for Selection of Power MOSFETs to Minimize Power Dissipation. Electronics. 2021; 10(17):2150. https://doi.org/10.3390/electronics10172150

Chicago/Turabian Style

Jadli, Utkarsh, Faisal Mohd-Yasin, Hamid Amini Moghadam, Peyush Pande, Mayank Chaturvedi, and Sima Dimitrijev. 2021. "A Method for Selection of Power MOSFETs to Minimize Power Dissipation" Electronics 10, no. 17: 2150. https://doi.org/10.3390/electronics10172150

APA Style

Jadli, U., Mohd-Yasin, F., Moghadam, H. A., Pande, P., Chaturvedi, M., & Dimitrijev, S. (2021). A Method for Selection of Power MOSFETs to Minimize Power Dissipation. Electronics, 10(17), 2150. https://doi.org/10.3390/electronics10172150

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