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Article

A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS

by
Lu Tang
1,*,
Kuidong Chen
1,
Youming Zhang
2,
Xusheng Tang
2 and
Changchun Zhang
3
1
School of Information Science and Engineering, Southeast University, Nanjing 210096, China
2
School of Cyber Science and Engineering, Southeast University, Nanjing 211189, China
3
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications, Nanjing 210023, China
*
Author to whom correspondence should be addressed.
Electronics 2021, 10(20), 2494; https://doi.org/10.3390/electronics10202494
Submission received: 21 September 2021 / Revised: 8 October 2021 / Accepted: 11 October 2021 / Published: 13 October 2021
(This article belongs to the Special Issue Analog Microelectronic Circuit Design and Applications)
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Abstract

:
A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.

1. Introduction

Phase-locked loop (PLL)-type frequency synthesizers are widely used to generate local frequency signals in RF transceivers. Programmable frequency dividers are indispensable in PLL-type frequency synthesizers [1,2,3]. Important specifications, such as a wide operation frequency range, low phase noise, and low power consumption are significant to programmable frequency dividers [4,5,6].
Frequency dividers on the basis of a fixed-modulus divider chain are introduced to frequency synthesizers to achieve a higher operating frequency and a wider frequency range. Nevertheless, the frequency divider is not able to work with any different frequency division ratio because the frequency division ratio is fixed by the PLL system in this case [7,8,9]. The programmable frequency dividers on the foundation of a chain of n divide-by-2/3 cells are the additional methods utilized to obtain a higher operating frequency and a wider operation frequency range. However, division ratios lower than 2n cannot be obtained in this topology [10]. Furthermore, higher power consumption will be consumed in the divide-by-2/3-cells-based programmable frequency divider when the current-mode logic (CML)-based latches are employed in the D flip-flop (DFF) of divide-by-2/3 cells [11]. Hence, a suitable, programmable frequency divider based on a dual-modulus prescaler (DMP) and pulse swallow (PS) counters with a higher operating frequency and a wider operation frequency range seems particularly advantageous [12,13].
This paper presents an improved programmable frequency divider for a Ka-band PLL-type frequency synthesizer in a 90 nm CMOS process. An active-inductor-based source-coupled logic (SCL) DFF topology is used in the synchronous divided-by-4/5 circuit of the programmable frequency divider to promote its locking range and operation frequency. Experimental results demonstrate expected properties of proposed circuits. Compared to conventional frequency dividers with a fixed frequency division and the other high-speed frequency divider with higher power consumption, the improved programmable frequency divider shows features such as a higher operating frequency, a wider operation frequency range, a more variable frequency division ratio, and lower power consumption. The key circuit techniques are discussed in Section 2. The experimental results are exhibited and summarized in Section 3. At last, some conclusions are given in Section 4.

2. Circuit Design

The architecture of the Ka-band PLL-type frequency synthesizer system containing the programmable frequency dividers based on pulse swallow counter topology is shown in Figure 1, where the programmable frequency dividers consist of a divide-by-N/N + 1 DMP and pulse swallow (PS) counters made up of a pulse counter of counter-P and a swallow counter of counter-S. Some active-inductor-based SCL DFF topologies are used in the synchronous divided-by-4/5 circuit of the DMP to promote the locking range and operation frequency.
As denoted in Figure 2, the values of P and S are set to counter-P and counter-S, respectively, when they begin to count. The DMP divides the high frequency input signal by N + 1 until counter-S counts up to S. At this point, it switches over and starts to divide-by N until counter-P counts up to P. Then, two counters will be reset and the DMP will switch back to divide by N + 1 simultaneously [14,15]. The total division ratio of the downscaling circuit is:
M = (N + 1)S + N(P − S) = NP + S,
Figure 1 shows that the frequency range of the output signal of the VCO is from 25 GHz to 33 GHz, and therefore that of the injection-locked frequency divider (ILFD) is from 12.5 to 16.5 GHz in the Ka-band PLL. As the circuit of the following stage of the ILFD, the operation frequency range of the programmable frequency divider in the Ka-band PLL should cover the frequency range of the ILFD’s output signal [2,9]. Because there are two optional reference frequency sources of 24 MHz and 32 MHz for the Ka-band PLL, the corresponding variation ranges of the frequency division ratio, M, of the proposed programmable frequency divider are 250–688 and 390–516, respectively. Considering the versatility and portability of the proposed circuit, the improved programmable frequency divider achieves a frequency range from 6 to 20 GHz. Consequently, the value of n is 8, the numerical variation range of M is 250–700, the numerical variation range of P is 30–87, and the numerical variation range of S is 0–7.

2.1. Dual-Modulus Prescaler

As revealed in Figure 1, the divide-by-8/9 DMP consists mainly of a synchronous divided-by-4/5 circuit and an asynchronous divided-by-2 circuit.
Since the synchronous divided-by-4/5 circuit works at the highest frequency in the divide-by-8/9 DMP, it should have features such as a wider operation frequency range, higher speed, lower consumption, and lower phase noise [16]. To promote the locking range and operation frequency, some techniques are adopted to optimize the circuit’s performance.
As revealed in Figure 3, the active inductors realized by transistors M1–M4 and M11–M14 are merged to extend the bandwidth of the latch in the source-coupled logic (SCL) DFFs and then increase the operation frequency of the synchronous divided-by-4/5 circuit. As shown in Figure 4, OR gates are also integrated into DFFs to restrain additional gate delays.
The active inductor’s impedance can be expressed as [17]:
Z ≈ Rs + Ls·s = 1/gm + (Cgs·R/gm) · s,
where R means the controllable resistor realized by transistors M1 (M11) and M4 (M14); gm represents the transconductance parasitic gate–source capacitance of transistors M2 (M12) and M3 (M13); and Cgs denotes the parasitic gate–source capacitance of these transistors. The active inductor can be regarded as an inductor, Ls, in series with a resistor, Rs. The inductance of the active inductor can eliminate the effects of the M2 (M12) and M3 (M13) transistors’ parasitic gate–source capacitances. Therefore, the operating frequency and bandwidth of the latches will be promoted.
A reasonable value of Ls is also related to the involved bias voltage. As exhibited in Figure 3 and Figure 4, constant-gm bias circuits are used in the DFFs mentioned above to generate bias voltage. In contrast to the bias voltage based on a network of resistors, constant-gm bias circuits are able to provide more stable output voltages [18,19].
It is shown in Figure 5 that the asynchronous divided-by-2 circuit in the DMP is implemented with true single-phase-clocked (TSPC) DFFs to achieve higher input sensitivity and lower power consumption.
Figure 6 shows the simulated input sensitivity curves of the proposed programmable frequency divider and its counterpart without active-inductor-based SCL DFFs. Obviously, the proposed programmable frequency divider has a larger operation frequency range and a better input sensitivity character than the counterpart without active inductors. The active-inductor-based SCL DFFs promote the locking range and operation frequency of the programmable frequency divider effectively.
Figure 7 exhibits a comparison of simulated time delay between the asynchronous divide-by-2 circuit based on the TSPC DFF shown in Figure 5 and its counterpart based on a conventional transmission gate DFF. As presented in Figure 7, the TSPC-DFF-based asynchronous divider is more suitable for the improved programmable frequency divider since the TSPC-DFF-based asynchronous divider has a smaller time delay than the conventional transmission-gate-DFF-based asynchronous divider.

2.2. Pulse Swallow Counters

The block diagram of the PS counters is presented in Figure 8a. The working principle of the swallow counter is roughly the same as that of the pulse counter. Either of the two subtractor-based counters will reset and restart counting again if they reduce to 0 [20]. Transistor-level implementation of the TSPC DFFs in the PS counters is illustrated in Figure 8b,c. Some logic gates are embedded into the TSPC DFFs to make them adapt to a higher operation frequency.

3. Experimental Results

The improved programmable frequency divider was fabricated in 90 nm CMOS technology with a 1.2 V power supply, with a die area of 0.165 mm2 including the pads. The microphotograph of the programmable frequency divider chip is shown in Figure 9.
Figure 10a demonstrates the measured, improved programmable frequency divider’s output waveform of 18.52 MHz with an input signal of 12 GHz when the total frequency division ratio is set as 648. The measured output voltage swing (VPk-Pk) on an external 50 Ω load is about 450 mV. Meanwhile, Figure 10b shows the measured, improved programmable frequency divider’s output waveform of 32.32 MHz with an input signal of 19 GHz when the total frequency division ratio is set as 588. The measured output VPk-Pk on an external 50 Ω load is about 380 mV. It can be seen from the experimental results exhibited in Figure 10 that the operation frequency range of the improved programmable frequency divider covers the frequency range of the output signal of the ILFD in the Ka-band PLL. Figure 11 reveals the measured phase noises at a 1 MHz offset of output signals of the programmable frequency divider at different input signals and division rates kept at a low level of less than −136 dBc/Hz. Figure 12 indicates that the measured input sensitivity of the programmable frequency divider is very high, given that the minimum input power is only −27 dBm at 15 GHz.
The experimental results above verify the active-inductor-based SCL DFFs can promote the operation frequency range of the programmable frequency divider effectively. Table 1 compares the performance of the improved programmable frequency divider to some other prior published scientific papers. It can be seen that the improved programmable frequency divider attains a wider operation frequency range with lower power consumption and lower phase noise.

4. Conclusions

An improved programmable frequency divider is fabricated in a 90 nm CMOS technology. An active-inductor-based SCL DFF topology is introduced to the synchronous divided-by-4/5 circuit of the programmable frequency divider to promote the operation frequency range and operation frequency. The chip area of the programmable frequency divider is 0.165 mm2. The operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low power consumption of 9.1 mW. All the phase noises at a 1 MHz offset of output signals of the programmable frequency divider at different input signals and division rates were kept at a low level of less than −136 dBc/Hz. The input sensitivity of the programmable frequency divider is as low as −27 dBm at 15 GHz. Experimental results demonstrate that the improved programmable frequency divider is suitable for Ka-band PLL applications in an RF receiver system.

Author Contributions

Conceptualization and methodology, L.T. and K.C.; writing—original draft preparation, L.T. and K.C.; writing—review and editing, L.T. and Y.Z.; visualization, L.T.; supervision, X.T.; project administration, L.T.; funding acquisition, L.T., C.Z. and X.T. All authors have read and agreed to the published version of the manuscript.

Funding

This work is supported by the National Natural Science Foundation of China (No. 61674036 and 61774037) and the National Key Research and Development Program of China (No. 2018YFB2202200).

Conflicts of Interest

The authors declare no conflict of interest.

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Electronics 10 02494 g001 550
Figure 1. Block diagram of the Ka-band PLL and the improved programmable frequency divider.
Figure 1. Block diagram of the Ka-band PLL and the improved programmable frequency divider.
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Figure 2. Working principle illustration for the frequency division ratio of the improved programmable frequency divider.
Figure 2. Working principle illustration for the frequency division ratio of the improved programmable frequency divider.
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Figure 3. Schematic of the modified DFF based on active inductors.
Figure 3. Schematic of the modified DFF based on active inductors.
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Figure 4. Schematic of the modified DFF based on active inductors integrated with “OR” logic.
Figure 4. Schematic of the modified DFF based on active inductors integrated with “OR” logic.
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Figure 5. Schematic diagram of a TSPC DFF (DFF1) for an asynchronous divider.
Figure 5. Schematic diagram of a TSPC DFF (DFF1) for an asynchronous divider.
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Figure 6. Simulated input sensitivity curves with and without active-inductor-based SCL DFFs.
Figure 6. Simulated input sensitivity curves with and without active-inductor-based SCL DFFs.
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Figure 7. Simulated time delay of asynchronous divide-by-2 circuits based on different kinds of DFFs.
Figure 7. Simulated time delay of asynchronous divide-by-2 circuits based on different kinds of DFFs.
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Figure 8. Diagrams: (a) block diagram of the PS counters; (b) schematic diagram of DFF2 in counter-P; and (c) schematic diagram of DFF3 in counter-S.
Figure 8. Diagrams: (a) block diagram of the PS counters; (b) schematic diagram of DFF2 in counter-P; and (c) schematic diagram of DFF3 in counter-S.
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Figure 9. Chip microphotograph of the programmable frequency divider.
Figure 9. Chip microphotograph of the programmable frequency divider.
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Figure 10. Measured output waveforms of the improved programmable frequency divider: (a) fin = 12 GHz, n = 648; (b) fin = 19 GHz, n = 588.
Figure 10. Measured output waveforms of the improved programmable frequency divider: (a) fin = 12 GHz, n = 648; (b) fin = 19 GHz, n = 588.
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Figure 11. Measured phase noise of the improved programmable integer divider’s output signal: (a) fin = 6.2 GHz, n = 656, and fout = 9.452 MHz; (b) fin = 11.3 GHz, n = 608, and fout = 18.597 MHz; and (c) fin = 19 GHz, n = 588, and fout = 32.32 MHz.
Figure 11. Measured phase noise of the improved programmable integer divider’s output signal: (a) fin = 6.2 GHz, n = 656, and fout = 9.452 MHz; (b) fin = 11.3 GHz, n = 608, and fout = 18.597 MHz; and (c) fin = 19 GHz, n = 588, and fout = 32.32 MHz.
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Figure 12. Measured simulated input sensitivity curves of the programmable frequency divider.
Figure 12. Measured simulated input sensitivity curves of the programmable frequency divider.
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Table
Table 1. Performance summary and comparison to other works.
Table 1. Performance summary and comparison to other works.
Ref.TechSupply (V)Power Dissipation (mW)Operation Frequency Range (GHz)Division RatioPhase Noise (dBc/Hz)
[7]65 nm CMOS1.2-57–6432−102.16@100 kHz
−138.48@1 MHz
[15]0.13 μm CMOS1.213.82.1–632–127−100.98@1 kHz
[21]65 nm CMOS0.9439.82–1916–31−118.8@10 kHz
[22]0.13 μm SiGe2.52501–1032–127−135.51@10 kHz
[23]90 nm CMOS1.210.813.2–18.44−124@100 kHz
[24]0.18 μm CMOS1.83.41–2.31–256−140@1 MHz
[25]65 nm CMOS113.1–10.624–80−141@1 MHz
This work90 nm CMOS1.29.16–20380–700−118.19@10 kHz
−125@100 kHz
−138.48@1 MHz
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MDPI and ACS Style

Tang, L.; Chen, K.; Zhang, Y.; Tang, X.; Zhang, C. A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS. Electronics 2021, 10, 2494. https://doi.org/10.3390/electronics10202494

AMA Style

Tang L, Chen K, Zhang Y, Tang X, Zhang C. A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS. Electronics. 2021; 10(20):2494. https://doi.org/10.3390/electronics10202494

Chicago/Turabian Style

Tang, Lu, Kuidong Chen, Youming Zhang, Xusheng Tang, and Changchun Zhang. 2021. "A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS" Electronics 10, no. 20: 2494. https://doi.org/10.3390/electronics10202494

APA Style

Tang, L., Chen, K., Zhang, Y., Tang, X., & Zhang, C. (2021). A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS. Electronics, 10(20), 2494. https://doi.org/10.3390/electronics10202494

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