A Novel MOS-Channel Diode Embedded in a SiC Superjunction MOSFET for Enhanced Switching Performance and Superior Short Circuit Ruggedness

Abstract

In this study, a novel MOS-channel diode embedded in a SiC superjunction MOSFET (MCD SJ-MOSFET) is proposed and analyzed by means of numerical TCAD simulations. Owing to the electric field shielding effect of the P+ body and the P-pillar, the channel diode oxide thickness (t_co) of MCD can be set to very thin while achieving a low maximum oxide electric field (E_MOX) under 3 MV/cm. Therefore, the turn-on voltage (V_F) of the proposed structure was 1.43 V, deactivating the parasitic PIN body diode. Compared with the SJ-MOSFET, the reverse recovery time (t_rr) and the reverse recovery charge (Q_rr) were improved by 43% and 59%, respectively. Although there is a slight increase in specific on-resistance (R_ON), the MCD SJ-MOSFET shows very low input capacitance (C_ISS) and gate to drain capacitance (C_GD) due to the reduced active gate. Therefore, significantly improved figures of merit R_ON × C_GD by a factor of 4.3 are achieved compared to SJ-MOSFET. As a result, the proposed structure reduced the switching time as well as the switching energy loss (E_SW). Moreover, electro-thermal simulation results show that the MCD SJ-MOSFET has a short circuit withstand time (t_SC) more than twice that of the SJ-MOSFET at various DC bus voltages (400 and 600 V).

1. Introduction

Using the charge balance concept, superjunction (SJ) MOSFETs are considered as a promising approach to improve the trade-off between specific on-resistance (R_ON) and breakdown voltage (BV) beyond silicon’s (Si) limit [1]. Therefore, Si-based SJ-MOSFETs have become a dominant power switch recently in the BV range of 500–650 V. When it comes to higher voltage applications (1.2 kV or more), Si-based MOSFETs face material limitations, and silicon carbide (SiC) SJ-MOSFETs are spotlighted as promising devices [2]. It has been experimentally proven that the SJ concept in SiC devices can achieve an ultra-low R_ON while maintaining high BV due to the superior material properties [3,4,5,6,7]. Meanwhile, the wide depletion region of SJ-MOSFETs causes extensive reverse recovery charge (Q_RR), which limits their usage in hard-switching configuration [8,9]. Additionally, the parasitic PIN body diode of the SiC MOSFET features a relatively higher turn-on voltage (~3 V) than its Si MOSFET counterpart (~0.7 V), owing to the wide band gap properties, which further deteriorates the reverse recovery characteristics. As a result, anti-paralleled external Schottky barrier diodes (SBDs) are normally used in power modules to suppress the activation of the PIN diode. However, it was found that the parasitic inductance between the MOSFET and the external SBD has a great effect on the conduction power loss [10].

The integration of a unipolar diode into SiC SJ-MOSFETs is an attractive option, as it can reduce chip size and prevent parasitic inductance component. Recently, research was conducted to improve the reverse recovery characteristics by embedding a p-type SBD in the drain side of a SiC SJ-MOSFET [11,12]. However, the fabrication process for integrating p-type SBD is too complicated and cost demanding. Additionally, several studies found that integrated SBDs cause high leakage current induced by thermionic field emission in short circuit stress, which lowers the device reliability and narrows the short circuit safe operating area (SCSOA) [13,14,15]. Moreover, the SBD region in SiC MOSFET may suffer from void issues or Schottky barrier height lowering after short circuit stress [16].

Recently, several studies demonstrated that integrating an MOS-channel diode (MCD) is another option for enhancing reverse recovery characteristics [17,18]. The oxide thickness of the MCD is reduced in order to achieve a desired turn-on voltage (V_F), so as to suppress the minority carrier injection from the PIN diode. In addition, some studies adopting the MCD concept in SiC MOSFETs have been conducted [19,20]. However, the thinned oxide layer of MCD increases the maximum oxide electric field (E_MOX) to nearly 4 MV/cm, which may result in oxide breakdown or shorten the lifespan of SiC MOSFETs. Krishnaswami et al. reported that an E_MOX under 3 MV/cm can ensure the gate oxide’s reliability [21]. As a result, concerns about a high oxide electric field make it difficult to maximize the benefits of MCD, producing a relatively high V_F compared to SBDs embedded in SiC MOSFETs. Thus, this will limit their usage in high-voltage applications.

In this study, a novel 1.2 kV class MOS-channel diode embedded in a SiC superjunction MOSFET (MCD SJ-MOSFET) is proposed and analyzed by numerical Sentaurus TCAD simulation compared with a SiC superjunction MOSFET (SJ-MOSFET). Applying the MCD concept in a 650 V class Si SJ-MOSFET was implemented previously [22], but no attempts have been made to do so for the SiC SJ-MOSFET. Moreover, the short circuit characteristics of MCDs embedded in SiC MOSFETs have not been studied yet. The P+ body and the P-pillar regions of the MCD SJ-MOSFET can simultaneously dissipate the electric field, so that the oxide thickness of MCD can be set to very thin while achieving acceptable E_MOX. Due to the low V_F of the MCD, the MCD SJ-MOSFET can greatly improve the reverse recovery characteristics compared with the SJ-MOSFET, while deactivating the parasitic body diode. In addition, the MCD SJ-MOSFET not only greatly reduces the switching energy loss, but also reduces the switching time due to the low input capacitance (C_ISS) and gate drain capacitance (C_GD). Additionally, electro-thermal simulation results show that the MCD SJ-MOSFET boasts superior short circuit performance compared to the SJ-MOSFET.

2. Device Structures and Simulation Background

The physical models used in the Sentaurus TCAD simulation contain bandgap narrowing (BGN) and Fermi–Dirac statistics. The recombination models contain Auger, Shockley–Read–Hall (SRH), the doping-dependent model and the temperature-dependent model [23]. The incomplete ionization and Hatakeyama avalanche models are also included. The mobility model contained the doping-dependent Arora model, Enormal and high field saturation. The anisotropic behavior in mobility and temperature characteristics of the SiC are also taken into consideration. A fixed charge concentration of 1 × 10¹² cm^–2 was included at the SiC/SiO₂ interface for all of the devices [24]. For electro-thermal mixed-mode simulation in short circuit characteristics, the thermodynamic model and analytic TEPower model are considered to describe self-heating effects and thermoelectric powers in nondegenerate semiconductors [25].

Figure 1 represents the schematic cross-sectional views and dimension parameters of the SJ-MOSFET and MCD SJ-MOSFET. The doping and dimension parameters of the two devices refer to published work [20]. Both devices feature the same doping and dimension parameters, except for the gate structure. The active gate extends over the P-base region, set to 0.2 μm in our proposed device. The doping concentration of the JFET region in both structures is set 1 × 10¹⁷ cm^–3 to reduce the R_ON. The body region of SiC MOSFET should be well designed because it has great influence not only on device performance, but also on device reliability [26]. We adopted shielded planar topology in this study, which features a P+ body region under the channel region [27]. Several studies have shown that the P+ region below the channel improves the short circuit capability of the device [25,28]. To obtain the charge balancing effect, the width of the P-pillar was set to 1.25 μm to occupy half of the cell pitch (5 μm), and it had the same doping concentration as that of the N-pillar. Figure 2 shows the influence of the pillar doping concentration on static characteristics in MCD SJ-MOSFET. In this study, we set the doping concentration of both pillar regions at 3.75 × 10¹⁶ cm^–3, which achieves the highest Baliga’s figure of merit (BFOM = BV²/R_ON).

The dummy gate electrically connected to the source electrode features thinner channel diode oxide thickness (t_co) than the active gate oxide thickness (t_ox = 50 nm), which acts as a channel diode. Figure 3a shows the influence of t_co on the reverse conduction characteristics of the MCD SJ-MOSFET in the third quadrant with comparison to the SJ-MOSFET. The result clearly shows that a smaller t_co leads to a faster turn-on in the proposed device because of the decreasing threshold voltage (V_TH) of the MCD. However, since the thinner t_co increases E_MOX, the trade-off between V_F and E_MOX must be discussed. Figure 4a shows the E_MOX and V_F relationship of MCD SJ-MOSFET according to the change in t_co. To meet the 3 MV/cm oxide reliability limit, t_co = 10 nm was chosen for the MCD SJ-MOSFET with an E_MOX of 2.95 MV/cm, as shown in Figure 4b. It seems that owing to the electric field shielding effect of the P+ body and the P-pillar, the electric field near the oxide can be effectively suppressed and the t_co can be very thin. The V_F of the proposed structure was 1.43 V, which was a similar level to that of the SBD-embedded SiC MOSFET [24,29]. The hole density distribution at I_DS = −100 A/cm² and V_GS = −5 V for both devices is shown in Figure 3b,c, respectively. In MCD SJ-MOSFET, minority carrier injection was greatly suppressed in the JFET and the N-pillar region, which means deactivation of the parasitic body diode. Therefore, the MCD SJ-MOSFET can prevent the bipolar degradation issue caused by the body diode [30]. The detailed device parameters of both structures are listed in

Table 1. Device parameters for TCAD simulation.

Parameter	SJ-	MCD-
Drift layer thickness (μm)	10	10
N-pillar/P-pillar doping (cm−3)	3.75 × 1016	3.75 × 1016
JFET doping (cm−3)	1 × 1017	1 × 1017
Channel length (μm)	0.5	0.5
N+ substrate thickness (μm)	100	100
N+ substrate doping (cm−3)	1 × 1019	1 × 1019
Channel doping (cm−3)	1 × 1017	1 × 1017
P+ body doping (cm−3)	5 × 1018	5 × 1018
N+ source doping (cm−3)	1 × 1019	1 × 1019
EFP region doping (cm−3)	5 × 1018	5 × 1018
Width of P-pillar (μm)	1.25	1.25
Cell pitch (μm)	5	5
Width of JFET (μm)	1	1
tox (nm)	50	50
tco (nm)	-	10
Distance of the active gate extend over the channel (μm)	-	0.2

.

The proposed device could be fabricated in a similar way compared to the SJ-MOSFET. Only one additional mask is required to form the stepped oxide, and the separation of the dummy gate and the active gate can be performed simultaneously in the subsequent etching process after N+ polysilicon deposition [17,20]. Additionally, the source contact hole etching process of the dummy gate can be performed simultaneously in the ohmic contact hole etching process.

3. Results and Discussion

3.1. Electrical Characteristics

Figure 5 represents the I–V characteristics of both devices. In this study, BV was obtained at V_GS = 0 V and I_DS = 1 μA/cm² and R_ON was obtained at V_GS = 15 V and I_DS = 100 A/cm². The MCD SJ-MOSFET has a slightly higher R_ON (1.03 mΩ·cm²) than the SJ-MOSFET (0.91 mΩ·cm²), because current flows through only one active gate. However, it still achieved low R_ON level due to the high concentration of JFET region and SJ structure. It can be seen that the proposed structure has about 46% lower saturation current at V_DS = 600 V compared to the SJ-MOSFET. Since the short circuit withstand time (t_SC) and saturation current are usually inversely proportional, it is very helpful for short circuit characteristics [31]. The proposed device has slightly higher BV (1669 V) than the SJ-MOSFET (1654 V), given that the electric field was concentrated on the dummy gate, owing to its thin t_co.

Figure 6a compares the reverse recovery characteristics of both devices. Additionally, the double pulse test circuit used in reverse recovery simulation is shown in Figure 6b. The lower arm MOSFET is used as a switch and the upper arm MOSFET is the actual device under test (DUT). The stray inductance and the gate resistance are 10 nH and 20 Ω, respectively. The load current is set to 500 A/cm² and the drain bias is set to 600 V. In order to make the channel turn off and act as a diode mode, V_GS = −5 V was applied in DUT. The results show that the peak reverse recovery current I_RRM of the MCD SJ-MOSFET is 206 A/cm², which is much lower than that of SJ-MOSFET (324 A/cm²). In addition, the reverse recovery time (t_rr) and the reverse recovery charge (Q_rr) were improved by 43% and 59%, respectively, compared to the SJ-MOSFET. Here, the Q_rr is defined in the following equation:

$${\mathrm{Q}}_{\mathrm{rr}}={\int }_0^{{\mathrm{t}}_{\mathrm{rr}}}{\mathrm{I}}_{\mathrm{DS}}\mathrm{dt}$$

(1)

where t_rr is defined as the time from when the reverse recovery current crosses zero to the time when the reverse recovery current drops down to 10% of the I_RRM. Figure 7 compares the C–V characteristics of both devices. In the MCD SJ-MOSFET, the input capacitance (C_ISS = C_GS + C_GD) decreased by 46% due to the reduced active gate area when V_DS = 600 V. Moreover, the C_GD of the MCD SJ-MOSFET is greatly reduced (79%) when V_DS = 600 V because of the reduced active gate area and depletion region capacitance caused by source-contacted dummy gate [32]. A comprehensive comparison of the device characteristics is shown in

Table 2. Comparison of device characteristics.

	SJ-	MCD-	Unit
VF	2.86	1.43	V
1 BV	1654	1669	V
2 RON	0.91	1.03	mΩ·cm2
BFOM	3006	2704	MW/cm2
3 CISS	27.1	14.5	nF/cm2
3 CGD	21.2	4.4	pF/cm2
RON × CGD	19.3	4.5	mΩ∙pF
IRRM	324	206	A/cm2
trr	44	25	ns
Qrr	7270	2999	nC/cm2

¹ BV was obtained at V_GS = 0 V and I_DS = 1 μA/cm². ² R_ON was obtained at V_GS = 15 V and I_DS = 100 A/cm². ³ C_ISS and C_GD were obtained at V_DS = 600 V.

. Although BFOM is slightly decreased by 10%, it can be seen that the MCD SJ-MOSFET significantly improved the figures of merit R_ON × C_GD by a factor of 4.3 compared to the SJ-MOSFET. As a result, these improvements indicate that the MCD SJ-MOSFET is more suitable for high-frequency applications.

Thereafter, the switching performance analysis of both devices was conducted using double pulse test circuit in Figure 6b. The lower arm MOSFET was the actual DUT and the body diode of the DUT (i.e., upper arm MOSFET) was used as a freewheeling diode. Figure 8a,b show the switching waveforms of both devices. Due to the large reduction in C_ISS and C_GD, the MCD SJ-MOSFET has a short miller plateau region and a large dV_GS/dt. As a result, the turn-off time (T_OFF = from 90% of V_GS to 90% of V_DS) and the turn-on time (T_ON = from 10% of V_GS to 10% of V_DS) of the proposed device is reduced by 56% and 39%, respectively, compared to the SJ-MOSFET. It seems that the overshoot current of the MCD SJ-MOSFET is much lower than that of SJ-MOSFET because of the large reduction in the reverse recovery charge of the upper arm MOSFET [24]. This will further decrease the turn-on switching energy loss (E_ON). Figure 8c compares the switching energy loss of both devices. E_ON and E_OFF are given by the following equations:

$${\mathrm{E}}_{\mathrm{ON}}={\int }_0^{{\mathrm{T}}_{\mathrm{ON}}}{\mathrm{V}}_{\mathrm{DS}}·{\mathrm{I}}_{\mathrm{DS}}\mathrm{dt}$$

(2)

$${\mathrm{E}}_{\mathrm{OFF}}={\int }_0^{{\mathrm{T}}_{\mathrm{OFF}}}{\mathrm{V}}_{\mathrm{DS}}·{\mathrm{I}}_{\mathrm{DS}}\mathrm{dt}$$

(3)

Owing to the faster switching time and enhanced reverse recovery characteristics, the switching energy loss (E_SW = E_ON + E_OFF) of the proposed device is improved by 48.6% compared to SJ-MOSFET. The detailed switching characteristics are summarized in

Table 3. Comparison of device characteristics.

	SJ-	MCD-	Unit
TOFF	750	331	ns
TON	317	194	ns
EOFF	20.03	9.43	mJ/cm2
EON	24.05	13.24	mJ/cm2
ESW	44.08	22.67	mJ/cm2

.

3.2. Short Circuit Characteristics

Short circuit ruggedness is one of the most crucial reliability issues in SiC MOSFETs because high voltage and high current are applied to the small cell area, resulting in high power dissipation [33,34]. Therefore, SiC MOSFETs with improved short circuit characteristics are essential. In this section, short circuit characteristics of both devices are investigated by means of electro-thermal mixed-mode TCAD simulation. The test circuit schematic is shown in Figure 9. The turn-on and turn-off gate voltage are set to 15 and 0 V, respectively, while the DC bus ranges from 400 to 600 V. The external gate resistance (R_G) is 10 Ω.

Figure 10 shows the short circuit current and the maximum temperature (T_MAX) waveforms of both devices with different pulse widths at a low drain bias (V_DD = 400 V). Here, T_MAX means the highest temperature in the device during short circuit simulation. Notably, two unique characteristics can be found in the short circuit current waveforms; the positive slope of the short circuit current at the end of the pulse and the increasing tail current with longer pulse width at turn-off state. This phenomenon is caused by leakage current at the PN junction due to the extremely high temperature, and has already been reported in several studies [35,36,37]. The t_SC of the MCD SJ-MOSFET is 22.5 μs, which is about two times longer than that of the SJ-MOSFET (11 μs). The energy dissipation during the short circuit state (E_SC) is defined as:

$${\mathrm{E}}_{\mathrm{SC}}={\int }_0^{{\mathrm{t}}_{\mathrm{SC}}}{\mathrm{V}}_{\mathrm{DS}}·{\mathrm{I}}_{\mathrm{DS}}\mathrm{dt}$$

(4)

The E_SC values were 1.05 and 1.16 J/cm² for the SJ-MOSFET and MCD SJ-MOSFET, respectively.

Figure 11 compares both devices at the same pulse of 10 μs, with the MCD SJ-MOSFET at V_DD = 400 V (the dotted line is T_MAX and the solid line is I_DS). Both the short circuit current and the T_MAX of the MCD SJ-MOSFET are greatly reduced compared to the SJ-MOSFET. For a detailed understanding of the enhanced short-circuit characteristics of the MCD SJ-MOSFET, the simulated distribution of the electron current density, electric field, lattice temperature, and hole density at point A is shown in Figure 12. Generally, the joule heating equation is expressed as follows [38]:

$${\mathrm{q}}_{\mathrm{j}}=\mathrm{J}·\mathrm{E}$$

(5)

where q_j is the joule heating energy density, J is the current density and E is the electric field. Although the electric field distribution is almost same in both structures, the joule heating energy density of the proposed structure becomes smaller due to the much lower current density. It can be confirmed that the lattice temperature of the SJ-MOSFET is much higher due to the increased joule heating energy density. The highest temperature region (hot spot) of the two devices is widely distributed between the P-pillars rather than being concentrated in the JFET region, as in conventional SiC MOSFETs (i.e., non SJ devices) [35]. This is because of the SJ structure in which the electric field is distributed vertically [39]. Therefore, the hot spot is far away from the gate oxide and source metal region, resulting in high reliability. Additionally, the SJ-MOSFET features a higher hole current (I_h) than the MCD SJ-MOSFET due to the high temperature, as shown in the red line in Figure 11. This explains the high tail current of the SJ-MOSFET, and it can be confirmed that I_h mainly formed at the high temperature region as shown in Figure 12. If the pulse width is further increased where I_h is large enough to activate the parasitic BJT, the drain current rises rapidly and thermal runaway occurs [25].

Finally, further investigation of the short circuit characteristics in high DC bus is conducted in a similar way. Figure 13 shows the short circuit current and the maximum temperature (T_MAX) waveforms of both devices with different pulse widths at a high drain bias (V_DD = 600 V). The t_SC and E_SC were 5.5 μs and 0.86 J/cm² for the SJ-MOSFET and 12 μs and 0.98 J/cm² for the MCD SJ-MOSFET, respectively. The MCD SJ-MOSFET showed a t_SC more than two times higher and an improved E_SC compared to the SJ-MOSFET, even at 600 V. It can be seen that the t_SC and E_SC of both devices are smaller than in the case of low drain bias. This is due to the elevated lattice temperature resulting from the high electric field, which was reported in a previous study [40]. The short circuit characteristics of both devices are summarized in

Table 4. Comparison of short circuit characteristics.

	SJ-	MCD-	Unit
tSC (@VDD = 400 V)	11	22.5	μs
tSC (@VDD = 600 V)	5.5	12	μs
ESC (@VDD = 400 V)	1.05	1.16	J/cm2
ESC (@VDD = 600 V)	0.86	0.98	J/cm2

.

4. Conclusions

In this study, a novel MCD SJ-MOSFET was developed and analyzed based on numerical TCAD simulations. Because of the P+ body and P-pillar region of the MCD SJ-MOSFET, the t_co of the MCD can be set at a significantly lower level, while achieving a low E_MOX of less than 3 MV/cm. Therefore, the proposed structure reduced V_F by approximately half of that of the SJ-MOSFET, thus resulting in superior reverse recovery characteristics. In addition, the MCD SJ-MOSFET achieved a significantly lower C_ISS and C_GD, thus resulting in significantly improved figures of merit R_ON × C_GD when compared with the SJ-MOSFET. As a result, the proposed structure demonstrated a shorter switching time and reduced the E_SW. Moreover, the simulation results revealed that the MCD SJ-MOSFET exhibited excellent short circuit characteristics in terms of the E_SC and t_SC. As a result, the MCD SJ-MOSFET is suitable for high-frequency and high-reliability applications.