A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

Tang, Fang; Ma, Qiyun; Shu, Zhou; Zheng, Yuanjin; Bermak, Amine

doi:10.3390/electronics10222856

Open AccessArticle

A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

by

Fang Tang

¹,

Qiyun Ma

¹

,

Zhou Shu

^1,*,

Yuanjin Zheng

² and

Amine Bermak

³

¹

Chongqing Engineering Laboratory of High Performance Integrated Circuits, School of Microelectronics and Communication Engineering, Chongqing University (CQU), Chongqing 400044, China

²

VIRTUS, IC Design Centre of Excellence, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 637598, Singapore

³

College of Science and Engineering, Hamad Bin Khalifa University, Doha 34110, Qatar

^*

Author to whom correspondence should be addressed.

Electronics 2021, 10(22), 2856; https://doi.org/10.3390/electronics10222856

Submission received: 11 October 2021 / Revised: 13 November 2021 / Accepted: 15 November 2021 / Published: 19 November 2021

(This article belongs to the Special Issue Advances on Analog-to-Digital and Digital-to-Analog Converters)

Download

Browse Figures

Versions Notes

Abstract

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm

^{2}

. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.

Keywords: SAR; ADC; high linearity; low power; switching procedure

Share and Cite

MDPI and ACS Style

Tang, F.; Ma, Q.; Shu, Z.; Zheng, Y.; Bermak, A. A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme. Electronics 2021, 10, 2856. https://doi.org/10.3390/electronics10222856

AMA Style

Tang F, Ma Q, Shu Z, Zheng Y, Bermak A. A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme. Electronics. 2021; 10(22):2856. https://doi.org/10.3390/electronics10222856

Chicago/Turabian Style

Tang, Fang, Qiyun Ma, Zhou Shu, Yuanjin Zheng, and Amine Bermak. 2021. "A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme" Electronics 10, no. 22: 2856. https://doi.org/10.3390/electronics10222856

APA Style

Tang, F., Ma, Q., Shu, Z., Zheng, Y., & Bermak, A. (2021). A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme. Electronics, 10(22), 2856. https://doi.org/10.3390/electronics10222856

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Menu

A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

Abstract

Share and Cite

Article Metrics

Article Access Statistics

Further Information

Guidelines

MDPI Initiatives

Follow MDPI