A 40-nm CMOS Piezoelectric Energy Harvesting IC for Wearable Biomedical Applications

Abstract

This investigation presents an energy harvesting IC (integrated circuit) for piezoelectric materials as a substitute for battery of a wearable biomedical device. It employs a voltage multiplier as first stage which uses water bucket fountain approach to boost the very low voltage generated by the piezoelectric. The boosted voltage was further improved by the boost DC/DC converter which follows a predefined timing control directed by the digital logic for the said converter to be operated efficiently. TSMC 40-nm CMOS process was used for implementation and fabrication of the energy harvesting IC. The chip’s core has an area of 0.013 mm². With an output of 1 V which is enough to supply the wearable biomedical devices, it exhibited the highest pump gain and accommodated the lowest piezoelectric generated voltage among recent related works.

1. Introduction

There is a huge demand for wearable sensors which are mainly used in monitoring health status of patients. Conventional batteries which are utilized as power supplies of these wearable sensors are being replaced. They may leak when they are not properly handled or packaged causing danger to the person. In addition, they cannot supply these wearables consistently due to limited battery capacity and the recharging requirement [1]. Moreover, they occupy too much space and add weight to the wearable sensor platforms [2,3]. Hence, they make the person wearing them feel uncomfortable. As a substitute for batteries in wearable sensor platforms, energy harvesting is being sought as a possible solution in providing power to these wearable sensors.

Meanwhile, human movements like feet and leg motion (walking and running), finger motion (writing and typewriting), and muscle contractions (heart, lung, and muscles) can bring an ample amount of wasted energy which can be harvested and converted to electricity. These biomechanical motions are commonly harvested by piezoelectric, electromagnetic, and triboelectric technologies [4,5]. Among the three energy harvesting technologies, piezoelectric is the most widely used and researched. Through the mechanical deformation of a piezoelectric material, an electricity is generated [4,6,7]. Some of the advantages of piezoelectric energy harvesting over the two technologies are higher energy density and output voltage [4,8]. The most widely known applications which utilized piezoelectrics are implemented in shoes [5,9]. More energy is generated by the piezoelectric when this is placed in shoes due to the weight exerted by the user standing on it and the continuous activities made by the user by walking and running. However, the generated output voltage from the vibration of piezoelectric material is not enough to supply or drive an electronic system [10]. One advantage of piezoelectric is that they can be easily integrated and interfaced with electronic systems implemented in a chip for more enhanced energy harvesting; thus, output voltage is now boosted [4,8,11,12].

Many related works have been reported regarding piezoelectric energy harvesting ICs for typical and wearable biomedical applications. A 0.5-m piezoelectric energy harvester was developed for wireless temperature monitoring which is capable of interfacing with wearables or implants where their data can be transmitted through the Internet (Internet of Things or IoT) [13]. It operates at a minimum input voltage of 0.51 V but generates voltage of only 3 V. In [8], they used a 130-nm CMOS full-bridge rectifier as energy harvester since the the voltage drop across the full-bridge rectifier is lower than the traditional off-chip diode. The voltage conversion ratio or pump gain is 0.987 while the output power is 10.7 W. Meanwhile, a piezoelectric energy harvesting circuit was developed that serves as supply to the wearable cannula for infant respiratory monitoring [14]. It has a pump gain of 0.987 but a higher output power of 11.1 W. A buck-boost converter was used for an input voltage of 0.54 V amplitude [15]. Its generated output voltage and power are 3.3 V and 57 mW, respectively. A 0.18-m piezoelectric energy harvester for wireless sensor nodes was proposed [16], where its possible generated output power and voltage are 94 W and 1.8 V for an input voltage of 1 V. Lastly, a study in [17] presented a 0.5-m CMOS vibrational energy harvester that has a pump gain of 3 but only operates at a minimum input voltage of 1 V.

In this study, a piezoelectric made from polyvinylidene fluoride (PVDF) was used because it is flexible which makes it to be wearable, comfortable, and non-intrusive or unobtrusive [14] to the users than the brittle piezoelectric made from lead zirconate titanate (PZT) [18]. The said PVDF as shown in Figure 1 has a wire diameter of 10 m and wire length of 1 mm. It has a vibration frequency of 6.67 Hz and maximum output voltage of 45 mV. Its output voltage was increased to 120 mV through series connection of the fibers. It was placed on the insole of the shoe.

Based from the previous works presented, none of them have developed an energy harvesting circuit that can accommodate an input voltage below 0.5 V. Previously, we proposed a PVDF film-based energy harvesting circuit [3] for the detection of missing children and elderly using a Bluetooth low energy (BLE) transceiver which requires at least 1 V power supply. Post-layout simulations were made for the evaluation of the said energy harvesting circuit with no chip implementation, measurements, and theoretical analysis conducted. In this paper, an energy harvesting circuit for low voltage PVDF piezoelectric which accommodates at least 120 mV-amplitude input voltage was realized that can be utilized for wearable biomedical applications. TSMC 40-nm CMOS process was used for implementation and fabrication of the energy harvesting IC. The fabricated chip was embedded inside the heel of the shoe for testing. It generates a maximum voltage of 1 V which is enough to drive and supply low-power and low-voltage wearable sensor platforms and systems.

2. System Architecture of Energy Harvester

The piezoelectric energy harvesting circuit architecture for wearable biomedical applications is shown in Figure 2. It is composed of AC/DC Converter, Voltage Monitor, and DC/DC Converter, which will be presented in the following subsections.

2.1. AC/DC Converter

In piezoelectric material energy harvesting circuits, AC/DC converters are needed. There are many different implementations for AC/DC converter circuits, e.g., [19]. However, due to efficiency and simplicity in practical applications of PVDF energy harvesting circuit for wearable biomedical devices, Voltage Multiplier or Charge Pump as shown in Figure 3 was selected in this study as AC/DC Converter in Figure 2. This 5-stage Voltage Multiplier is widely used in energy harvesting to convert AC to DC signals. It is a switched capacitor which elevates the lower voltage to a higher voltage value. Moreover, it can provide a preliminary boost to facilitate the design of the DC/DC Converter, thereby alleviating the problem of too small input voltage in the subsequent DC/DC Converter design. Because the PVDF film’s output voltages at PZ1 and PZ2 are very low, a low $V_{th}$ transistor is utilized reducing the voltage drop and boosting the voltage efficiently.

2.2. Voltage Monitor

Since a very low output voltage is generated by the PVDF film, energy must be stored at C_st first. Then, the next stage will be driven by the large stored energy in C_st. As shown in Figure 4, V_st is monitored by a CMOS-based Schmitt trigger [20]. When V_st > high switching voltage V_SPH, the power MOS switch M_sw in Figure 2 is switched on. At this moment, the DC/DC converter is started by an enable signal (V_{sw_n} = 1). When V_st < low switching voltage V_SPL, a disable signal is sent by the Schmitt trigger (V_{sw_n} = 0) to turn off the DC/DC converter and restore energy in C_st.

2.3. DC/DC Converter

The Boost DC/DC Converter is displayed in Figure 5 [21]. It is composed of Digital Logic, On-time Mode Generator (T_on Generator), Off-time Mode Generator (T_off Generator). The PMOS switch P_sw is used to replace the diode which has lower voltage drop and better efficiency; hence, the said converter is a synchronous type instead of a diode architecture. Because of very low output voltage of PVDF, the bucket fountain method [22] is used in which the energy is kept in C_st until it is fully charged to the preset voltage value, and then the second stage boost is used to drive the wearable biomedical device. The Voltage Monitor is used to determine whether the stored voltage is sufficient. If the stored voltage is large enough, the power transistor (M_sw) in Figure 2 is turned on, and a large enough voltage is generated through the DC/DC converter to drive the wearable biomedical device. The system is in standby state waiting for the next startup. When the Voltage Monitor sends an enable signal (V_{sw_n} = 1), the DC/DC converter will now start to operate. S₁, S₂, and S₃ are generated by the Digital Logic. $\overline{S2}$ and $\overline{S3}$ are denoted by S_{2_b} and S_{3_b}, respectively. A comparator is interfaced to the Digital Logic for output adjustment.

2.3.1. T_on Generator

The T_on Generator in Figure 5 is shown in Figure 6. It directs the V_n signal in Figure 5 to maintain the high pulse width (V_n = 1) which governs the ON time of the POWER NMOS N_sw. During T_on mode, S₁ is high, S₂ and S₃ are low, MN3 is turned on while MP4 is at cutoff. A fixed current (I_on) discharges C_on when V_con < V_in is achieved. During T_off mode, S₁ and S₃ are low, S₂ is high, and MN3 and MP4 are at cutoff prior to becoming equal values of V_con and V_in. Figure 7 shows the timing diagram at T_on mode.

2.3.2. T_off Generator

The Toff generator in Figure 5 is shown in Figure 8. It directs the V_p signal to maintain the low pulse width (V_p = 1) for the ON time of power PMOS transistor P_sw, and generates charging and discharging currents through the current mirror. During T_on mode where S₁ is high, S₂ and S₃ are low, transistors MN7, MP10, and MN11 are at cutoff. On the contrary, during T_off mode, where S₁ and S₃ are low, S₂ is high, MN11 is at cutoff while MN7 and MP10 are on. Therefore, this charges C_off with a fixed current until V_coff > V_in is expected. Figure 9 shows the timing diagram at T_off mode.

2.3.3. Digital Logic

Digital Logic in Figure 5 controls the signals’ timing sequence in the DC/DC converter, so that the DC/DC converter follows a predefined function for it to be operated correctly.

Figure 10 and Figure 11 show the flowchart and the timing diagram, respectively, of the timing control of Digital Logic in steady state. There are 3 modes: idle, on-time (T_on), and off-time (T_off). Looking at Figure 5 and Figure 10, the DC/DC converter starts at idle mode, and Digital Logic is at initial state when V_{sw_n} is low and S₃ and V_con are high.

The power MOS transistor (M_sw) in Figure 2 will be on when a sufficiently high voltage is across C_st; thus, making V_{sw_n} high. When S₁ which is connected to the Gate Buffer of N_sw and V_{sw_n} are high, and S₂ which is connected to the Gate Buffer of P_sw is low, the system enters T_on mode. At this time, the inductor L stores energy when I_L flows through N_sw. The T_on generator controls the duration of the T_on mode. It will enable S₁ to low after a predefined time when V_con drops below V_in changing the system from T_on to T_off mode.

When S₂ is high and S₁ is low, the system enters T_on mode. C_load charges when (I_L) flows through P_sw. The T_off generator controls the duration of the T_off mode. It will enable S₂ to low and S₃ to high after a predefined time when V_in drops below V_coff returning the system back from T_off to idle mode.

2.3.4. Reference Current Generator

Figure 12 shows the Reference Current Generator which provides a stable reference current (I_bias) needed in Figure 6 and Figure 8. The duty cycle contributed by the power switches (N_sw and P_sw) depend on the Reference Current Generator. Since I_bias can be affected by power supply’s voltage and temperature variations, proportional (PTAT) and complementary to absolute temperature (CTAT) circuits are implemented to suppress the influence of temperature on accuracy and stability. In PTAT, both MN1 and MN2 are driven to subthreshold operation while both MP3 and MP4 are biased into strong inversion operation. PTAT current generator consists of transistors MN1, MN2, MP3, and MP4. Its generated I_pt0 is mirrored by MP3 and MP9 to the resulting (I_pt). Moreover, CTAT current generator is composed of MP5, MN6, MN7, and MP8. Its I_nt0 is mirrored by MP8 and MP9 to the output (I_nt). Then, the output current I_bias is the sum of I_nt and I_pt, which will be insensitive to temperature variations.

2.3.5. Comparator Circuit

The two comparators in the T_on and T_off Generators are used to regulate the on-time and off-time modes’ maintenance duration, respectively. For these two comparators, their propagation delay and noise have less effect to the their function and performance than the output-regulated Comparator in Figure 5. Therefore, the two comparators’ quiescent current can be fixed to a smaller value to consume less power. However, the trade-off is that the propagation delay will be larger. In this design, a two-stage open-loop comparator is used for the AC/DC converter’s output adjustment. It is shown in Figure 13.

3. Measurement Results and Discussion

TSMC 40-nm CMOS process was used to implement and fabricate the PVDF piezoelectric energy harvesting IC. All of the transistor lengths are at minimum size. The aspect ratio of the width of the NMOS and PMOS transistors used in this chip is 2:1. The layout view of the core which has an area of 0.1223 × 0.1065 mm² is shown in Figure 14 and Figure 15 and shows the die photo of the chip which has an area of 0.7097 × 0.7097 mm². The core was covered by a dummy layer, as seen in the die photo, because there is a minimum metal density required by the foundry; hence, only the pads and the wire-bonds can be seen in the photo.

The fabricated chip was connected to PCB board and SMA connectors to reduce the loading effect. A power supply (ABM PRT3230 (ABM, Hsinchu City, Taiwan)) was used to provide VDD (0.9 V) and GND. A signal generator (Tektronix AFG3252 (Tektronix, Johnston, OH, USA))provides input signals for testing. It generates a 120 mV-amplitude sinusoid which mimics the excitation and the output voltage of the PVDF film for easy testing and validation of the proposed energy harvesting circuit. An oscilloscope (Teledyne Lecroy Waverunner 610Zi (Teledyne Lecroy, Thousand Oaks, CA, USA))observed the input and output waveforms. It was also used for the measurement and characterization of the PVDF film’s output voltage.

The output signal generated by the PVDF film, V_st, and V_{sw_n} signals are shown in Figure 16. A maximum of 100 kHz was used as PVDF’s vibration frequency for this testing. From Figure 17, it is noted that at the beginning the capacitor (C_st) was charged at 260 mV. When V_st reaches at least 260 mV, the Voltage Monitor sends an enable signal (V_{sw_n} = 1 V) to the DC/DC Converter to start the second mode of boosting which is the T_on mode.

Figure 18 summarizes the output specifications. The output voltage, current, and power are 1 V, 4.2 mA, and 4.2 mW, respectively. When the on-voltage value (V_on) is lower than V_st (237 mV), V_{sw_n} is 0 then wait for the next enable signal. The resulting waveforms of the digital logic timing control in steady state is shown in Figure 18. It is consistent with the designed Digital Logic’s timing control waveforms in Figure 19.

Figure 20 shows the waveform of the output voltage V_out generated by the piezoelectric energy harvesting IC which is 1 V. For the PVDF generated voltage of 120 mV to 1 V, a regulated output voltage of 1 V is expected. The developed piezoelectric energy harvesting IC can be operated with a PVDF’s vibration frequency of 6.67 Hz to 100 kHz. The measurement results correspond with the post-layout simulation results made in the prior work [3]. With this, it can provide a stable power supply to the low-power and low-voltage wearable biomedical devices. The proposed piezoelectric energy harvesting IC is compared with the prior studies as shown in

Table 1. Comparison of the piezoelectric energy harvesting circuit with prior studies.

	[13]	[8]	[14]	[15]	[16]	[17]	This work
Year	2017	2017	2017	2016	2014	2011	2021
Type	PZT	Vibrational	PVDF	Piezoelectric	PZT	Vibrational	PVDF
Process	0.5 μm	130 nm	130 nm	PSpice	0.18 μm	0.5 μm	40 nm
PVDF voltage	0.51 V	0.704 V	0.703 V	0.54 V	1 V	1 V	0.12 V
Vout	3 V	0.694 V	0.694 V	3.3 V	1.8 V	3 V	1 V
Pout	N.A.	10.7 μW	11.1 μW	57 mW	55 μW	3.9 mW	4.2 mW
Ripple	40 mV	N.A.	N.A.	N.A.	N.A.	N.A.	3 mV
Pump gain	5.88	0.987	0.987	6.11	1.80	3	8.33

. In Table 1, it should be noted that the pump gain is represented as the ratio of V_out and the PVDF generated voltage. As shown in Table 1, the largest pump gain was generated by the proposed piezoelectric energy harvester IC over all the prior energy harvesting circuits cited in the literature.

4. Conclusions

A 40-nm CMOS piezoelectric energy harvesting IC has been presented. A Voltage Multiplier was constructed alleviating the problem of very low input voltage from the PVDF piezoelectric by boosting this low voltage. DC/DC converter improves the boosted voltage by following the Digital Logic’s predefined timing of three operating modes, namely, idle, T_on, and T_off. With this, the low-power, low-voltage wearable biomedical devices, which normally require 1 V as their supply, can be operated at stable condition by the developed piezoelectric energy harvesting IC. Among the prior studies, the proposed energy harvesting IC exhibited the highest pump gain and accommodated the lowest piezoelectric generated voltage.