Analysis of Electrothermal Effects in Devices and Arrays in InGaP/GaAs HBT Technology

Abstract

In this paper, the dc electrothermal behavior of InGaP/GaAs HBT test devices and arrays for power amplifier output stages is extensively analyzed through an efficient simulation approach. The approach relies on a full circuit representation of the domains, which accounts for electrothermal effects through the thermal equivalent of the Ohm’s law and can be solved in any commercial circuit simulator. In particular, the power-temperature feedback is described through an equivalent thermal network automatically obtained by (i) generating a realistic 3-D geometry/mesh of the domain in the environment of a numerical tool with the aid of an in-house routine; (ii) feeding the geometry/mesh to FANTASTIC, which extracts the network without performing simulations. Nonlinear thermal effects adversely affecting the behavior of devices/arrays at high temperatures are included through a calibrated Kirchhoff’s transformation. For the test devices, the thermally-induced distortion in I–V curves is explained, and the limits of the safe operating regions are identified for a wide range of bias conditions. A deep insight into the electrothermal behavior of the arrays is then provided, with particular emphasis on the detrimental nonuniform operation. Useful guidelines are offered to designers in terms of layout and choice of the ballasting strategy.

1. Introduction

Gallium arsenide (GaAs) heterojunction bipolar transistors (HBTs) are the dominant technology for handset power amplifier (PA) design by virtue of their power density, cut-off frequency, and efficiency [1]. However, designing rugged circuits with GaAs HBT devices requires extra care because of strong electrothermal (ET) effects arising from (i) low thermal conductivity of the substrate, (ii) lateral heat confinement by mesa isolation, and (iii) high operating currents. Thermal-aware design methodologies relying on suitable ET simulation tools are highly desired to alleviate or avoid performance and reliability degradation. Unfortunately, the choice of the simulation approach is challenging. Full 3-D ET device simulations based on the finite-element method (FEM), e.g., with Atlas from Silvaco or Sentaurus from Synopsys, are computationally onerous or even unviable when dealing with complex structures like practical transistor arrays and packages.

A more efficient, yet accurate enough, approach is based on the generation and solution of a SPICE-compatible purely-electrical macrocircuit that accounts for ET effects by means of the thermal equivalent of the Ohm’s law (TEOL). In this macrocircuit, the power-temperature feedback is included through an equivalent thermal network (ETN, an electrical circuit relying on the TEOL), the components of which can be optimized in a pre-processing stage with the aid of 3-D thermal-only FEM simulations. A key part of this strategy is implementing an analytical transistor model as a subcircuit, in which the temperature-sensitive parameters are allowed to vary during the simulation run thanks to the TEOL (e.g., [2,3,4]). We adopted such an approach—based on in-house models for individual transistors—to examine the dc and transient ET behavior of devices/circuits for a large variety of technologies and applications, namely, single- and multi-finger silicon-on-glass (SOG) bipolar transistors [5,6,7]; output arrays of PAs in InGaP/GaAs HBT technology, yet with relevant approximations in describing the geometry of the devices [8]; basic analog blocks, like simple current mirrors [9,10], differential pairs [11,12], and cascode amplifiers [13] in many bipolar technologies (GaAs, SOG, and silicon-germanium); vertical double-diffused silicon-carbide MOS transistors with a multicellular pattern [14].

In our earlier contribution [15], we exploited the aforementioned approach to analyze the dc ET behavior of test devices meant for experimental characterization and arrays for output stages of PAs in InGaP/GaAs HBT technology. In that case, a simple ETN based on the N×N thermal resistance (R_TH) matrix, N being the number of individual HBTs (each associated to one heat source), was adopted in the macrocircuits. The R_THs were determined through pre-processing 3-D linear FEM simulations performed with COMSOL [16] aided by an in-house routine [17] for an exceptionally accurate and automated construction of the geometry/mesh of the structures. Nonlinear thermal effects dictated by high temperatures were taken into account through the Kirchhoff’s transformation [18,19]. The ET simulations were performed using the popular PSPICE program [20].

This paper is aimed at extending [15] in a multi-fold way.

• More details of the individual transistor model and its subcircuit implementation are provided.
• Differently from [15], where the arrays were assumed to lie on an unthinned GaAs substrate (as typical for known-good-die identification), here they are considered in a realistic phone-board environment, i.e., the substrate is thinned and attached on a laminate, the bottom of which is at T_B = 358 K.
• Similar to [21], in this work the linear power-temperature feedback is described by invoking FANTASTIC [22,23], which is fed with the COMSOL geometry/mesh accompanied with additional information (on position/shape of heat sources, boundary conditions, and thermal conductivities), and rapidly extracts an ETN based on the R_TH matrix without performing simulations. Contrary to conventional ETNs (like the one used in [15]), the FANTASTIC network allows reconstructing the overall temperature field for selected bias conditions in a post-processing step.
• In [15], the Kirchhoff’s transformation was applied by assuming that all materials share the same nonlinear thermal behavior as GaAs. Unfortunately, this was found to lead to a perceptible overestimation of ET effects. Here, more realistic results are achieved by carrying out a suitable preliminary calibration procedure, similar to that made in [21].

By virtue of the above points, this work can be reviewed as an improved, and self-consistent, version of [15].

The remainder of the paper is outlined as follows. In Section 2, the technology/layout details of test devices and arrays are given. Section 3 probes into the simulation approach; in particular, the transistor model, its subcircuit representation, the COMSOL geometry/mesh generation, the FANTASTIC extraction of the R_TH-based ETN, and the assembling of the final macrocircuit are described. Section 4 reports and discusses the dc ET simulation results carried out by PSPICE. Conclusions are then drawn in Section 5.

2. Devices and Arrays

The structures investigated in this paper are mesa-isolated InGaP/GaAs NPN HBTs manufactured by Qorvo using an HBT-only process (referred to as HBT8) with two metal layers (e.g., [23,24]), the key features of which are reported in

Table 1. Key features of the investigated HBT technology.

Parameter	Value
Common-emitter current gain at 300 K and medium current levels βF0	135
Open-emitter breakdown voltage BVCBO	27 V
Open-base breakdown voltage BVCEO	17 V
Peak cut-off frequency fT for VCE = 3 V	40 GHz
Collector current density JC at peak fT for VCE = 3 V	0.2 mA/µm2
Maximum oscillation frequency fMAX	82 GHz

. The individual transistor, hereinafter also denoted as unit cell (Figure 1), is composed by four emitter fingers, each with a 2 × 20.5 µm² area (the total emitter area is then equal to 164 µm²). The emitter is composed by a stack of four layers, namely (from the top):

• an In_0.5Ga_0.5As cap to reduce the contact resistance with the gold (Au)-based emitter metallization;
• a grading In_xGa_1-xAs layer (with x spanning from 0.5 to 0) used to ensure a good lattice continuity with the underneath layer;
• a GaAs layer acting as a set-back for an easier manufacturing process;
• an n-doped In_0.49Ga_0.51P emitter layer, the bottom surface of which corresponds to the metallurgical base-emitter junction.

The base is a thin p-doped GaAs layer lying on a thick n-type GaAs mesa.

Both the base and collector contacts are designed with materials compatible with the manufacturing process in order to reduce the parasitic resistances. More specifically, the base contact is composed by the series of titanium (Ti) and platinum (Pt) layers that alloy through the leftover InGaP emitter on the base mesa, while the collector contact is located at the bottom of this mesa on the highly-doped GaAs subcollector layer and consists of a stack of Au-germanium (Ge)-nickel (Ni) layers. A metallization with two Au levels is exploited to electrically connect the unit cells and plays a role in the thermal exchange by favoring heat shunt and spread [24].

The electrical isolation from potential neighboring components is ensured by ion-implant damage (referred to as GaAs-ISO) resulting in an amorphous GaAs layer. Far from the active regions, the metal layers are separated from the GaAs substrate through a thin silicon nitride (Si₃N₄) layer providing some shunt effect. A 10-µm-thick polybenzoxazole (PBO) layer covers the whole structure.

The analysis first focuses on devices fabricated on a 620-µm-thick GaAs substrate (thickness normally used for testing) and provided with 65 × 65 µm² pads (in a ground–signal–ground configuration) for bare-die experimental characterization through RF probes. The devices have been designed with a single unit cell, as well as with two and three paralleled cells, respectively (Figure 2, top). In the analysis reported in Section 4, the temperature T₀ = 300 K (hereinafter also denoted as reference temperature) is assumed to be applied to the substrate backside, which can be practically done with a thermochuck.

Subsequently, the investigation is conducted on transistor arrays for PA output stages, where the unit cells are arranged in columns to (i) ensure an almost uniform distance from them to the through-wafer via providing the ground; (ii) meet the very stringent die size requirements. The arrays are assumed to be operating in a typical phone-board environment. Architectures with even and odd number of unit cells per column are examined to offer helpful guidelines to designers. In particular, arrays comprising 24 and 28 unit cells are considered, which are both arranged in four columns composed by six and seven cells each, respectively (Figure 2, bottom). In contrast to the simplified analysis performed in [15], (i) the arrays lie on a 100 µm-thick die, obtained by thinning the original 620-µm-thick wafer; (ii) the die is attached with epoxy to an 830 × 830 µm²-wide and 270 µm-thick laminate, which includes eight 600 × 600 µm²-wide 12 µm-thick Cu plates connected by nine circular Cu vias, all embedded in a dielectric; (iii) as previously mentioned, the laminate bottom is held at T_B = 358 K, which is typical in the phone-board environment.

3. Simulation Approach

3.1. General Description

Similar to our previous papers [5,6,7,8,9,10,11,12,13,14,15,21], we chose to employ a circuit-based approach, which provides a good trade-off between computational overhead and accuracy. Such an approach makes use of the TEOL and can be summarized as follows:

• Each four-finger unit cell is represented with one SPICE-compatible subcircuit (Section 3.3) implementing a simple analytical transistor model (Section 3.2). This assumption relies on the following considerations: (i) the two metals uniformly distribute the temperature over the base-emitter junction; (ii) the electron currents emerging from the four closely-spaced individual emitters are expected to spread and give rise to only one heat source. The subcircuit uses (i) a basic/standard bipolar transistor at reference (and unchangeable) temperature T₀ as a core component, and (ii) linear and nonlinear controlled sources to account for the variation of the temperature-sensitive parameters during the simulation run, as well as for other specific mechanisms. According to the TEOL, the temperature rise ΔT_j = T_j − T₀ averaged over the base-emitter junction (which mainly influences the ET device behavior) is actually a voltage, while the dissipated power P_D is treated as a current. In addition to the standard transistor terminals (emitter, base, and collector), the unit-cell subcircuit is also equipped with an input node carrying the “voltage” ΔT_j and with an output node offering the “current” P_D.
• The power-temperature feedback is described with a SPICE-compatible thermal feedback block (TFB), the construction of which is carried out in a pre-processing stage. The TFB contains an ETN including the matrix of self-heating (SH) R_THs of the unit cells and mutual R_THs among them. The inputs of the ETN are the powers P_D dissipated by the cells (represented with currents), and the outputs are their temperature rises ΔT_jlin = T_jlin − T₀ for the test devices or ΔT_jlinB = T_jlin − T_B for the arrays (all emulated with voltages) under linear thermal conditions.
• The ETN is automatically determined through the following procedure. First, an accurate 3-D geometry/mesh of the domain is built in the COMSOL environment using an in-house routine; then, the geometry/mesh, along with additional information concerning position/shape of heat sources, boundary conditions, and thermal conductivities, is fed to FANTASTIC, which extracts the ETN in a really short time without the need of user’s intervention/expertise or onerous FEM simulations (Section 3.5). Generally, the whole process is very fast and error-free. The adoption of FANTASTIC is an improvement over our prior contribution [15], where (i) the R_TH matrix was calculated by performing N purely-thermal static COMSOL simulations by activating only one heat source at a time, and (ii) the simple ETN adopted did not allow a post-processing reconstruction of the whole temperature map in the domain.
• As mentioned above, the ETN only accounts for linear thermal conditions. However, nonlinear thermal effects can be significant when particularly high temperatures are reached. Such effects are taken into account by making use of the Kirchhoff’s transformation, which converts the linear temperature rises ΔT_jlin (test devices) or ΔT_jlinB (arrays) offered by the ETN into the nonlinear counterparts ΔT_j = T_j − T₀ and ΔT_jB = T_j − T_B, respectively. Contrary to [15], here the transformation was properly calibrated (Section 3.4) to improve the ET simulation accuracy.
• Besides the ETN, the TFB also includes N voltage-controlled voltage sources that apply the calibrated Kirchhoff’s transformation to the ETN linear outcomes; as a result, the nonlinear temperature rises ΔT_j (test devices) and ΔT_jB (arrays) are computed; only for the arrays, the increment T_B − T₀ is added to ΔT_jB to get the N nonlinear ΔT_j = T_j − T₀ to be provided to the unit-cell subcircuits.
• The subcircuits are then connected to the TFB in the environment of a commercial circuit simulation tool. As a result, the whole domain is transformed into a purely-electrical macrocircuit, which inherently accounts for ET effects (Section 3.6): the temperature, and thus the temperature-sensitive parameters, are allowed to vary during the simulation run. The task of solving this macrocircuit is given to the powerful and robust engine of the circuit simulation tool, with very low computational effort and minimized occurrence of convergence issues compared to other numerical methods.

3.2. Bipolar Transistor Model

The analytical model used to describe the dc behavior of the unit cell is simple, accurate enough, and associated to a low-effort parameter extraction process; this provides high flexibility to the overall approach. The collector current in forward active mode is given by [13]

$$I_C=I_{CnoAV}+I_{AV}=M·I_{CnoAV}=M·\left(1+\frac{V_{CB}}{V_{AF}}\right)·\frac{1}{B_{HI}}·A_E·J_{S0}·\exp \left(\frac{V_{BEj}+\mathsf{\varphi }·\Delta T_j}{\eta ·V_{T0}}\right)$$

(1)

where:

• I_CnoAV [A] is the collector current in the absence of impact-ionization (II), or avalanche, effects;
• I_AV [A] is the collector current component only induced by avalanche;
• V_CB [V] is the collector-base voltage;
• V_AF [V] is the forward Early voltage;
• M (≥ 1) is the dimensionless V_CB-dependent avalanche multiplication factor;
• A_E [µm²] is the emitter area;
• J_S0 [A/µm²] is the reverse saturation current density at the reference temperature T₀ = 300 K;
• η is the ideality coefficient at T₀;
• V_T0 = 0.02586 V is the thermal voltage at T₀;
• V_BEj [V] is the internal (junction) base-emitter voltage, that is, V_BEj = V_BE − R_B·I_B − R_E·I_E, where V_BE is the externally-accessible base-emitter voltage, I_B, I_E [A] are the base and emitter currents, and R_B, R_E [Ω] are the parasitic base and emitter resistances, respectively;
• the temperature rise ΔT_j [K] is defined as T_j − T₀, T_j being the temperature averaged over the base-emitter junction;
• ϕ [V/K] is the temperature coefficient of V_BEj;
• B_HI (≥1) is an I_E-dependent dimensionless term introduced to describe the attenuation dictated by high-injection (HI) effects, i.e., the Kirk-induced gain roll-off.

In this approach, the temperature dependence of I_C is taken into account with a V_BEj shift, while J_S0, η, and V_T0 are kept at their T₀ values (e.g., [25]). Coefficient ϕ [V/K] is assumed to vary with emitter current I_E according to the following logarithmic law [11,13,26,27,28,29]:

$$\mathsf{\varphi }={\mathsf{\varphi }}_0-\mathsf{\eta }·\frac{k}{q}·\ln \left(\frac{I_E}{A_E·J_{S0}}\right)$$

(2)

where k [eV/K] is the Boltzmann’s constant, and q [C] is the (absolute value of the) electron charge; parameter ϕ₀ can be extracted by comparing (1) with I_C–V_BE characteristics measured at various backside temperatures at low current levels for V_CB = 0 V [29].

As far as factor M is concerned, any model can in principle be adopted. For the GaAs HBTs under analysis, we chose the classic Miller model given by [30]

$$M=\frac{1}{1-{\left(\frac{V_{CB}}{B{V}_{CBO}}\right)}^{n_{AV}}}$$

(3)

BV_CBO [V] and n_AV being the open-emitter breakdown voltage and a fitting power factor, respectively.

The HI attenuation term B_HI is modeled as [5,13]

$$B_{HI}=1+{\left(\frac{{\mathsf{\alpha }}_F·I_E}{A_E·J_{HI}}\right)}^{n_{HI}}$$

(4)

where α_F is the common-base (CB) forward current gain, while J_HI [A/µm²] and n_HI are fitting parameters.

The common-emitter (CE) forward current gain β_F is modeled as

$${\mathsf{\beta }}_F={\mathsf{\beta }}_{F0}·\left(1+\frac{V_{CB}}{V_{AF}}\right)·\frac{1}{B_{HI}}·\exp \left[\frac{\Delta E_G}{k}·\left(\frac{1}{\Delta T_j+T_0}-\frac{1}{T_0}\right)\right]$$

(5)

where β_F0 is the gain at T₀, at medium current levels (i.e., before the Kirk-induced fall-off), and in the absence of Early effect, while ΔE_G [eV] is the positive difference between the bandgaps of emitter and base yielding a negative temperature coefficient (NTC). The CB gain α_F in (4) is related to the CE counterpart by α_F = β_F/(1 + β_F).

The base current is given by (e.g., [13,31])

$$I_B=I_{BnoAV}-I_{AV}=\frac{I_{CnoAV}}{{\mathsf{\beta }}_F}-\left(M-1\right)·I_{CnoAV}=I_{CnoAV}·\left(\frac{1}{{\mathsf{\alpha }}_F}-M\right)=I_C·\left(\frac{1}{{\mathsf{\alpha }}_{F}M}-1\right)$$

(6)

where use has been made of (1).

We note that replacing the simple M formulation (3) with a more complex one (e.g., [31]), the model can be adopted for bipolar transistors fabricated in any technology if a proper parameter calibration procedure is performed (in silicon devices, ΔE_G is negative, since the emitter bandgap is narrower than that of the base due to high doping levels).

The parameter extraction procedure is straightforward (details are reported in [29]). The values adopted for the simulations described in Section 4 are reported in

Table 2. Model parameter values.

Parameter	Value
AE	164 µm2
JS0	3.5 × 10−26 A/µm2
η	1.01
VAF	1000 V
βF0	135
ϕ0	5.4 mV/K
ΔEG/k	200 K−1
JHI	0.35 mA/µm2
nHI	1
BVCBO	27 V
nAV	9 [32]
RE	1 Ω
RB	3.5 Ω

.

3.3. SPICE Unit-Cell Subcircuit

A sketch of the subcircuit is reported in Figure 3, which evidences the standard bipolar transistor model as a core component at temperature T₀, as well as the additional ΔT_j (input) and P_D (output) terminals. Linear/nonlinear controlled voltage/current sources are added to enable the variation of the temperature-sensitive parameters during the simulation run, as well as to account for physical mechanisms not included in the standard transistor (for this reason, the resulting subcircuit is also popularly referred to as wrapper model). The II-free collector current I_CnoAV accounting for the temperature dependence of V_BEj, HI, and Early effects is computed with the nonlinear source denoted with A. The II-unaffected base current I_BnoAV is calculated by source B as I_CnoAV/β_F, β_F being evaluated by the nonlinear source C from V_CB, I_E, and ΔT_j according to (5). The II (avalanche) current I_AV is determined as (M − 1) × I_CnoAV by source D, where factor M described by (3) is provided by the nonlinear source E; the collector current I_C is obtained by adding I_AV to I_CnoAV, while the base current I_B is given by I_BnoAV-I_AV. The lumped resistances R_B and R_E emulate the parasitic base and emitter resistances, respectively. The subcircuit also includes further nonlinear sources (omitted in Figure 3) to describe the cell behavior in saturation mode. The dissipated power P_D under dc conditions (to be given to the TFB) is determined as

$$P_D=I_B·V_{BE}+I_C·V_{CE}=I_E·V_{BE}+I_C·V_{CB}$$

(7)

3.4. Construction of the Geometry/Mesh in COMSOL and Calibration of the Kirchhoff’s Transformation

The 3-D geometry/mesh of each domain was constructed in the environment of the COMSOL software package [16] by making use of an in-house routine that relies on the MATLAB-COMSOL Livelink and the Toolbox for files in GDSII format provided by U. Griesmann [17]. The procedure is described as follows: first, the GDS layout file (i.e., the masks used for the technological process) is input to the routine along with the thicknesses of the layers, mask biases, and material parameters; then, the routine automatically draws the 3-D geometry, and finally generates and optimizes the mesh in the COMSOL environment. Such a process is error-free and requires a much shorter time compared to a painstakingly-long manual approach.

A single heat source (geometrically coinciding with the base-collector SCR [17]) and a single subcircuit were assigned to each unit cell (Figure 1); as mentioned earlier (Section 3.1), this intrinsically assumes that the fingers within the cell are tightly thermally coupled, and thus not prone to thermal hogging. Figure 4 depicts the geometry of the 1-cell test device, while Figure 5 shows the mesh of the 2-cell one.

For the arrays, the horizontal symmetry was exploited to construct the geometry/mesh of only half of the domains (Figure 2, bottom), thus alleviating the computational burden; the missing portions were virtually restored by applying an adiabatic boundary condition to the plane of symmetry. Figure 6 illustrates the geometry of (half of) the 24-cell array, while Figure 7 shows the mesh of (half of) the 28-cell array, both in COMSOL.

Besides the geometry/mesh of the domains and the position of the heat sources, FANTASTIC [22,23] requires information on the boundary conditions and thermal conductivities to extract the ETN including the R_TH matrix (Section 3.5). As mentioned in Section 2, the backside of the GaAs substrate was assumed to be at T₀ for the test devices, while the laminate bottom was set to T_B for the arrays. All the other surfaces were considered adiabatic (i.e., with zero outgoing heat flux), such an assumption being justified by the particular scratch-protection coating employed in the technology (thick PBO).

The thermal conductivities associated to the materials of the test devices (at T₀) and arrays (at T_B) are listed in

Table 3. Thermal conductivities of the materials composing the devices and arrays.

Material	k(T0) (W/µmK)	k(TB) (W/µmK)	Temperature Dependence
Si3N4	18.5 × 10−6 [33]	19.6 × 10−6	(8), α = −0.33 [33]
In0.5Ga0.5As	0.048 × 10−4 [33]	3.9 × 10−6	(8), α = 1.175 [33]
InxGa1-xAs (0 < x< 0.5)	0.092 × 10−4 [33] average in the layer	7.4 × 10−6	(8), α = 1.212 [33]
GaAs	4.6 × 10−5 [33]	3.69 × 10−5	(8), α = 1.25 [33]
ion-implanted GaAs	0.046 × 10−5 [33]	0.0369 × 10−5	(8), α = 1.25 [33]
In0.49Ga0.51P	0.052 × 10−4 [33]	0.041 × 10−4	(8), α = 1.4 [33]
Au	3.18 × 10−4 [34,35]	3.14 × 10−4	(9), β = 6.98 × 10−8 W/μmK2 [34,35]
Pt	0.71 × 10−4 [34,35]	0.71 × 10−4	independent
Ti	0.22 × 10−4 [34,35]	0.22 × 10−4	independent
Ni	0.91 × 10−4 [35]	0.863 × 10−4	(9), β = 8.1 × 10−8 W/μmK2 [35]
Ge	0.6 × 10−4 [33]	0.48 × 10−4	(8), α = 1.25 [33]
Cu	3.98 × 10−4 [35]	3.95 × 10−4	(9), β = 5.83 × 10−8 W/μmK2 [35]
Glue	1 × 10−4	1 × 10−4	independent
Polybenzoxazole (PBO)	0.0014 × 10−4	0.0014 × 10−4	independent
laminate dielectric	0.0065 × 10−4	0.0065 × 10−4	independent

.

The ETN is generated by FANTASTIC under linear thermal conditions (temperature-insensitive thermal conductivities). However, as very high temperatures are reached, nonlinear thermal effects can no longer be neglected. More specifically, the thermal conductivities of the materials vary with temperature T according to the following laws:

$$k\left(T\right)=k\left(T_0\right)·{\left(\frac{T}{T_0}\right)}^{-\mathsf{\alpha }}$$

(8)

$$k\left(T\right)=k\left(T_0\right)-\mathsf{\beta }·\left(T-T_0\right)$$

(9)

where (8) applies to semiconductors and insulators, and (9) to some metals; the accepted values of the α and β coefficients are also reported in Table 3. In order to account for the temperature dependences described by (8) and (9), we resorted to the Kirchhoff’s transformation [18,19], which converts the linear junction temperature rises (ΔT_jlin and ΔT_jlinB) into the nonlinear counterparts (ΔT_j and ΔT_jB) through [36]

$$\Delta T_j=T_j-T_0=T_0·{\left[m_k+\left(1-m_k\right)·\frac{\Delta T_{jlin}+T_0}{T_0}\right]}^{\frac{1}{1-m_k}}-T_0=T_0·{\left[1+\left(1-m_k\right)·\frac{\Delta T_{jlin}}{T_0}\right]}^{\frac{1}{1-m_k}}-T_0$$

(10)

for the test devices, and

$$\Delta T_{jB}=T_j-T_B=T_B·{\left[m_k+\left(1-m_k\right)·\frac{\Delta T_{jlinB}+T_B}{T_B}\right]}^{\frac{1}{1-m_k}}-T_B=T_B·{\left[1+\left(1-m_k\right)·\frac{\Delta T_{jlinB}}{T_B}\right]}^{\frac{1}{1-m_k}}-T_B$$

(11)

for the arrays. Contrary to the simplified analysis in [15], where m_k was chosen equal to 1.25 (α value for GaAs) for all the domains under investigation, here a preliminary calibration procedure was performed for this parameter. Let us refer to the 1-cell test device for the sake of simplicity. This HBT was simulated with COMSOL over a wide range of dissipated powers P_D by activating the thermal conductivity dependences upon temperature (8), (9) (nonlinear thermal conditions), and the average temperature rise over T₀ at the base-emitter junction ΔT_j was computed for each P_D. The linear temperature rise ΔT_jlin over the same P_D span was evaluated by multiplying P_D by the R_TH obtained by COMSOL under linear conditions. Then the Kirchhoff’s transformation was applied to ΔT_jlin, and m_k was tuned so as to ensure the best agreement between the nonlinear temperature rise ΔT_j calculated by the transformation and the realistic one evaluated by COMSOL; the optimum m_k value was 0.8333 (Figure 8). The same operation was repeated by activating one cell belonging to an array and considering the average junction temperature rise over T_B; in that case, the optimum m_k value was found to be 0.8932. As a result, m_k = 0.8333 was used in (10) for the ET simulations of the test devices (Section 4.1), whereas m_k = 0.8932 was adopted in (11) for the ET simulations of the arrays (Section 4.2).

3.5. FANTASTIC

The FAst Novel Thermal Analysis Simulation Tool for Integrated Circuits (FANTASTIC), originally presented in [22,23], was conceived and developed to approximate a FEM model of heat conduction in an electronic device, having typically millions of DoFs, with a dynamic compact thermal model (DCTM), having only tens of DoFs, and the corresponding ETN [21]. The extraction of the DCTM and ETN does not require to solve the FEM model, as it is performed in short times through a refinement of the truncated balance-based moment matching approach to model-order reduction (MOR) introduced in [37]. Moreover, it also allows the extraction of a static compact thermal model (SCTM) and the related ETN relying on the R_TH matrix (hereinafter indicated with R_TH); for this simplified case, FANTASTIC is even quicker, as briefly discussed below.

The heat conduction problem in the structure, assumed to be static and linear, is imported from either commercial (e.g., COMSOL) or open-source numerical tools in the form of: mesh discretizing the geometry, position/shape of the heat sources, boundary conditions, and thermal conductivities (also mass densities and specific heats are required for the dynamic case). Both hexahedral and tetrahedral meshes can be used. Arbitrary tensorial thermal conductivity distributions can be defined. Neumann’s, Dirichlet’s, or Robin’s boundary conditions can be applied.

A FEM model of the problem is then assembled by FANTASTIC. In particular, the stiffness matrix K is constructed. High-order basis functions can be adopted; the typical choice is to select tetrahedral meshes and 2nd-order basis functions, as a good trade-off between accuracy and efficiency. The M DoFs of the temperature rise distribution, forming the M-row vector ϑ, are solution of the discretized heat conduction problem

$$\mathbf{K}\mathit{\vartheta }=\mathbf{q}$$

(12)

in which the power density distribution vector q takes the form

$$\mathbf{q}=\mathbf{Q}{\mathbf{P}}_{\mathbf{D}}$$

(13)

In (13), P_D is an N-row vector with the powers dissipated by the N heat sources, and Q is an M × N matrix, the n-th column of which is the power density distribution vector of the n-th heat source, with n = 1, …, N. The port temperature rises of the N heat sources form the N-row column vector ΔT_jlin (ΔT_jlinB for the arrays) defined as [37]

$$\Delta {\mathbf{T}}_{\mathbf{j}\mathbf{l}\mathbf{i}\mathbf{n}}={\mathbf{Q}}^T\mathit{\vartheta }$$

(14)

In order to extract a compact thermal model, an M × $\hat{M}$ matrix V with $\hat{M}$ ≪ M is defined, which allows expressing ϑ by means of a reduced number $\hat{M}$ of DoFs, thus forming the $\hat{M}$-vector $\hat{\mathit{\vartheta }}$ so that

$$\mathit{\vartheta }=\mathbf{V}\hat{\mathit{\vartheta }}$$

(15)

The V matrix is used for projecting the discretized heat conduction problem (12)–(14) by the Galerkin’s method, deriving an SCTM in the form

$$\hat{\mathbf{K}}\hat{\mathit{\vartheta }}=\hat{\mathbf{q}}$$

(16)

where

$$\hat{\mathbf{q}}=\hat{\mathbf{G}}{\mathbf{P}}_{\mathbf{D}}$$

(17)

$$\Delta {\mathbf{T}}_{\mathbf{j}\mathbf{l}\mathbf{i}\mathbf{n}}={\hat{\mathbf{G}}}^T\mathit{\vartheta }$$

(18)

in which

$$\hat{\mathbf{K}}={\mathbf{V}}^T\mathbf{K}\mathbf{V}$$

(19)

is an $\hat{M}$th-order matrix and

$$\hat{\mathbf{G}}={\mathbf{V}}^T\mathbf{Q}$$

(20)

is an $\hat{M}$ × N matrix. The V matrix is determined by the Algorithm 1 reported below.

Algorithm 1: SCTM extraction

Set V:=0

for each heat source n=1, …, N do

1  Solve (21) for Θn

2  Update matrix V by appending Θn

3  Generate a SCTM projecting (12)–(14) onto V

At line 1, the temperature response to the n-th heat source is solved for the static heat conduction problem. Thus, equation

$$\mathbf{K}{\mathbf{\Theta }}_n=\mathbf{Q}{\mathbf{e}}_n$$

(21)

is solved for Θ_n, e_n being the vector selecting the n-th column of Q. Since the coefficient matrices of these linear systems are symmetric positive definite, the most efficient multigrid iterative solvers can be used for their solution.

At line 2, the V matrix is updated by appending vector Θ_n to its columns if it is linearly independent with respect to them.

At line 3, the SCTM is determined proceeding as in (16)–(18), and has dimension $\hat{M}$ ≤ N ≪ M. A much smaller dimension is thus obtained with respect to the dynamic case; moreover, since a much smaller number of discretized heat conduction problems are solved, a large speedup of the algorithm is also achieved.

It is now observed that by solving at limited cost the eigenvalue problem

$${\hat{\mathbf{U}}}^T\hat{\mathbf{K}}\hat{\mathbf{U}}=\hat{\mathbf{\Lambda }}$$

(22)

having as unknown the $\hat{M}$th-order orthogonal matrix $\hat{\mathbf{U}}$, in which $\hat{\mathbf{\Lambda }}$ is an $\hat{M}$th-order diagonal matrix, and introducing the change of variables

$$\hat{\mathit{\vartheta }}=\hat{\mathbf{U}}\hat{\xi }$$

(23)

the SCTM Equations (16)–(18) are transformed into the equivalent form

$$\hat{\mathbf{\Lambda }}\hat{\xi }=\hat{\mathbf{\Gamma }}{\mathbf{P}}_{\mathbf{D}}$$

(24)

$$\Delta {\mathbf{T}}_{\mathbf{j}\mathbf{l}\mathbf{i}\mathbf{n}}={\hat{\mathbf{\Gamma }}}^T\hat{\xi }$$

(25)

where $\hat{\mathbf{\Gamma }}$ is the $\hat{M}$ × N matrix ${\hat{\mathbf{V}}}^T$$\hat{\mathbf{G}}$. The spatial distribution of the temperature rise is then reconstructed as

$$\mathit{\vartheta }=\mathbf{\Xi }\hat{\xi }$$

(26)

Being $\mathbf{\Xi }=\mathbf{V}\hat{\mathbf{U}}$ an $M$ × $\hat{M}$ matrix like V. The $\hat{\xi }$ vector encompasses the DoFs of the thermal field. These DoFs are the node temperature rises in the extracted ETN sketched in Figure 9, which is governed by (24) and (25) and represents a simplified version of the dynamic counterpart [21,22,23], as it benefits from a much lower (by one order of magnitude) number of nodes, resistances, and controlled sources. The ETN transforms the port powers P_D into the port temperature rises ΔT_jlin by inherently accounting for the boundary conditions initially applied to the FEM model. The port response of this network defines the N^th-order resistance matrix $\hat{\mathbf{R}}$_TH [K/W] of the SCTM given by ${\hat{\mathbf{Q}}}^T{\hat{\mathbf{K}}}^{-1}\hat{\mathbf{Q}}$. Since by construction the $\hat{M}$ columns of the V matrix span the N columns of matrix K⁻¹Q, it is straightforward to prove that $\hat{\mathbf{R}}$_TH = R_TH, where R_TH is the thermal resistance matrix of the discretized heat conduction problem (12)–(14) given by Q^TK⁻¹Q. This further strengthens the general result relating the thermal impedance matrices of the compact thermal model and of the discretized heat conduction problem in the dynamic case [38].

The resulting ETN is particularly well-suited to be solved by means of modified nodal analysis in SPICE-like circuit simulators, since all circuit elements are voltage-controlled, and thus the number of variables added by the SCTM is limited to $\hat{M}$. The topology is general and can be implemented into any circuit simulation program.

It is worth noting that, after the circuit simulation, as a post-processing stage, the whole spatial distribution of temperature rise in the examined domain can be reconstructed at negligible computational cost and memory storage using (26), for both thermal-only and ET simulations. The temperature map can be plotted by any proper tool, like e.g., Paraview. This option is not allowed using conventional ETNs like in our former paper [15].

3.6. Construction of the Macrocircuit

The ETN derived by FANTASTIC was enriched with N nonlinear voltage-controlled voltage sources to account for the Kirchhoff’s transformation, and the TFB was then obtained. The ΔT_j and P_D nodes of the subcircuits (the unit cells) were connected to the TFB, thereby giving rise to the whole TEOL-based SPICE-compatible macrocircuit, a simplified scheme of which is reported in Figure 10. As previously mentioned, the solution of the macrocircuit was delegated to PSPICE [20], although any other commercial circuit simulation software (e.g., LTSPICE, Eldo, Keysight ADS [39], and SIMetrix) could in principle be used.

3.7. Extension to the Dynamic Case

Unlike advanced bipolar transistor models equipped with temperature-dependent parameters and a thermal node (like HiCUM [40], VBIC, AHBT, and Mextram504, all available in ADS), the proposed unit-cell model/subcircuit is only suited to fairly well describe forward active and saturation modes under dc conditions. RF simulations including ET effects can be enabled by resorting to a variant of our approach based on one of the above models in the ADS environment; the strategy can be described as follows.

• The selected transistor model must be provided with a power (output) node, and the internal one- or two-pair thermal network has to be deactivated.
• All parameters of the model must be extracted from experimental data, which is a nontrivial task.
• As mentioned in Section 3.5, if FANTASTIC is also fed with the mass density and specific heat for all materials, it can be enabled to extract a DCTM of the domain and the associated ETN accounting for the dynamic heat propagation [21,22,23]. Such an ETN, together with the Kirchhoff’s transformation sources, will constitute the SPICE- and ADS-compatible TFB.
• Lastly, the macrocircuit has to be built in ADS by connecting the model instances among them and with the TFB.

It is worth noting that the adoption of the one- or two-pair thermal networks embedded in the transistor models instead of our TFB (i) would lead to a significant inaccuracy in terms of SH of the single cell (the typically-used single pair is not enough for the transient SH response [23]), and (ii) would exclude the mutual thermal interactions among unit cells, which however play a relevant role, as demonstrated in Section 4.

As an alternative, one could resort to an ET solver available in recent ADS releases, which couples a quasi−3-D layout-based numerical thermal tool to the circuit simulator (the thermal networks embedded in the model instances being disabled) [41]. However, (i) this strategy is only applicable to device models equipped with a thermal node; (ii) using such a solver for layout optimization is very labor-intensive; (iii) the iterative process leading to convergence is resource-hungry.

4. Results and Discussion

4.1. Test Devices

The analysis of the test devices is two-fold: it is intended (i) to offer an overview of the ET- and II-induced positive-feedback mechanisms limiting the safe operating region, and (ii) to explore the thermally-stabilizing effect ensured by the base ballasting. In the latter case, an integrated resistor R_Bext = 400 Ω was used per each cell, as this is the typical ballasting strategy chosen for the arrays investigated in Section 4.2.

Let us first consider the single-cell device, which does not require an ETN, but only a linear SH R_TH to which the Kirchhoff’s transformation is applied. The R_TH was computed to be about 440 K/W, which is in good agreement with the experimental value extracted by means of the classic method proposed in [42]. Figure 11 shows the V_BE-constant I_C–V_CE and ΔT_j–V_CE characteristics. It can be inferred that the curves of the unballasted device are affected by a flyback (also denoted as snapback or turnover) mechanism followed by a negative-differential-resistance (NDR) branch [6,13,31,43,44,45,46], which can be simulated/measured by (i) incrementing I_C or (ii) connecting a resistor R_Cext to the collector terminal, sweeping V_Cext on the available resistor node (Cext), and evaluating V_CE as V_CextE − R_Cext·I_C. It is worth noting that increasing V_CE beyond the value corresponding to the flyback would have instead led to a thermal runaway (shown for V_BE = 1.25 V) and sudden device failure. Adding a base-ballasting resistor (as suggested in [31,47,48]) with R_Bext = 400 Ω prevents the flyback (and thus the runaway); however, it reduces the internal (junction) V_BEj at medium/high current levels, decreasing and limiting the collector current.

Figure 12 shows the behavior of the 2-cell test device under I_BTOT-constant conditions. As can be seen, a bifurcation phenomenon is triggered: beyond a critical V_CE, cell #2 tends to conduct the whole current, while #1 gradually turns off [26,49,50,51]. For I_BTOT = 0.5 mA, the critical V_CE is equal to 8 V for the unballasted case, and reduces with increasing I_BTOT. It is not possible to identify a priori which cell will take all the current, since it is determined by random (and unavoidable) technology and layout fluctuations. In PSPICE the cells are assumed electrically identical, and the current hogging in cell #2 is favored by a marginally higher SH R_TH due to a slight layout asymmetry. As far as the total collector current I_CTOT is concerned, a smooth NDR region due to the β_F NTC is observed in the V_CE range where I_CTOT is equally shared by the two cells. The NDR mechanism is then replaced by a marked I_CTOT reduction within the bifurcation region due to the ‘faster’ temperature growth with V_CE in the hotter cell, which implies a significant β_F decrease; such a behavior is also denoted as collapse of collector current [49] or collapse of current gain [26,50,51]. As V_CE exceeds 13 V, the II current I_AV2 (≈90 µA at V_CE = 15 V) can no longer be neglected with respect to I_BTOT (=500 µA); as a result, the avalanche-less current I_BnoAV2, almost equal to I_BTOT + I_AV2, perceptibly grows due to the I_AV2 increase, and in turn raises I_CnoAV2 ≈ I_C2 ≈ I_CTOT. The inclusion of base ballasting with R_Bext = 400 Ω per cell pushes the critical V_CE to 16.6 V, restoring a uniform behavior over a large voltage range [47].

Figure 13 illustrates the behavior of the 2-cell test device under V_BE-constant conditions. Let us first examine the unballasted case. If I_CTOT is swept, the current is equally divided between the unit cells until a flyback takes place, followed by an NDR branch still showing uniform operation; at low V_BE (e.g., 1.2 V), a bifurcation will also occur for relatively low cell temperatures [31]. A similar behavior was observed for more paralleled BJTs in SOG technology [7]; in that case, an uneven current distribution was found to arise beyond the uniform NDR branch under I_CTOT-controlled conditions. By increasing V_CE, the whole device (or at least one of the two cells) would have blown up beyond the value corresponding to the flyback; this means that our simulations do not confirm the observation of a ‘safe’ collapse encountered in [50,51].

Let us next consider the device with base-ballasted cells subject to the same biasing conditions (Figure 14). As far as the V_BE = 1.2 V case is concerned, the flyback point moves to the left, thus shrinking the V_CE-controlled safe operating region; this can be ascribed to the increased avalanche current flowing in the unit cells, in turn induced by R_Bext = 400 Ω, which favors the positive feedback action related to II [31,48]. On the other hand, the thermally-induced bifurcation disappears; it was found than the bifurcation-triggered discrepancy between I_C1 and I_C2 reduces with increasing R_Bext, and R_Bext = 400 Ω is the threshold value for which the uniform behavior is fully restored. For higher V_BEs, the ballasting makes the flyback mechanism vanish, thus improving the thermal stability of the device; however, the current capability significantly plummets at high current levels.

It is also important to analyze the ET behavior of the 2-cell device under I_ETOT-controlled conditions, typical for differential pairs and comparators [52,53]. Results obtained by increasing the total emitter current I_ETOT for V_CB = 8 V are shown in Figure 15 for both the unballasted and ballasted cases. It is shown that without ballasting a bifurcation phenomenon is triggered for a critical I_ETOT (33 mA), and the whole I_CTOT eventually flows in cell #2, rapidly increasing its temperature; a similar behavior would be obtained by fixing I_ETOT and sweeping V_CB [6,31]. Applying the resistors R_Bext = 400 Ω, thermal effects are weakened and the bifurcation disappears, limiting the maximum temperature reached by the device.

We now consider the ET behavior of the test device composed by three unit cells, assumed ideally identical in PSPICE. The first simulation was performed under CE conditions by increasing V_CE with a constant I_BTOT = 0.7 mA (Figure 16). Let us focus on the unballasted case. It is found that cell #2 starts conducting more current due to the thermal coupling with both the adjacent (outer) cells #1 and #3. For higher V_CE values, a counterintuitive behavior takes place: a bifurcation mechanism involving cells #1 and #3 occurs at V_CE = 7 V; in particular, cell #3 eventually bears more current, whereas #1 turns off, as induced by the slightly higher SH R_TH of #3 with respect to #1. By further increasing V_CE, cell #3 prevails over #2 since the SH R_TH of #3 (396.2 K/W under linear thermal conditions) is perceptibly higher than that of cell #2 (361.7 K/W), which experiences a more effective heat flow through metal 2 (top metal). The strongly uneven current distribution for V_CE > 7 V turns into a collapse in the I_CTOT–V_CE curve. For V_CE > 13 V, cell #3 conducts the whole current, and therefore I_B3 = I_BnoAV3 − I_AV3 is almost equal to I_BTOT = 0.7 mA; the increase in I_AV3 with V_CE due to the enhanced II leads to a growth in I_BnoAV3, which dominates over the NTC of β_F3, thus driving an I_C3 ≈ I_CTOT increase. Adopting R_Bext = 400 Ω for all cells pushes the uneven current distribution to V_CE > 15.7 V, thus leading to a much wider uniform operating region.

It is worth noting that increasing the emitter area of cell #1 by only 1 µm², the onset of the bifurcation takes place at the same critical V_CE, but the behavior of cells #1 and #3 reverses: cell #1 prevails over #3, and eventually sinks also the current of #2. Nevertheless, the I_CTOT–V_CE curve would coincide with that obtained for cells sharing ideally identical areas. This means that it is impossible to foresee which of the outer cells will dominate, since it depends on unavoidable technological/layout discrepancies. The practical implication is that the failure analysis should look at planes of symmetry, and not at the specific failed cells.

An overview of the I_CTOT–V_CE characteristics for various I_BTOT values is illustrated in Figure 17 for both the unballasted and base-ballasted cases; it is apparent how the collapse locus (which can be reviewed as the boundary of the safe operating area) significantly moves rightward by virtue of the external base resistances [47].

In the above analysis, it was stated that the 3-cell test device benefits from a lower SH R_TH of the inner cell #2 compared to the outer cells. We decided to quantify the related thermally-stabilizing effect by performing a test simulation where the R_TH of cell #2 was considered identical to those of the lateral cells (396 K/W under linear thermal conditions) and the mutual R_THs between adjacent cells were assumed to coincide (115 K/W). Figure 18 shows that the classic collapse with #2 conducting the whole current is obtained. Unfortunately, the collapse onset in the I_CTOT–V_CE characteristic takes place at the same V_CE as in the real test device with lower R_TH for cell #2; this means that the bifurcation mechanism occurring for the outer cells in the real case is as deleterious as the strong thermal coupling affecting #2 in the ideal device with uniform SH R_THs.

4.2. Transistor Arrays

As already mentioned in Section 2 and Section 3.4, only half of each array for PA output stages was drawn, meshed, and simulated by exploiting the horizontal symmetry. This means that only 12 (14) cells were taken into account for the 24-cell (28-cell) arrays. Our simulation approach allows monitoring the dc ET behavior of the arrays at cell-level, that is, besides the junction temperature, all the key parameters, voltages, and currents are available for each cell; this would have been unviable by performing experiments since the collector layers of the individual cells are all shorted to one another, by being in a single isolation tub.

Hereinafter, I_CTOT and I_BTOT are the total collector and base currents of the semi-arrays.

The analysis focuses on I_BTOT-constant CE conditions, since GSM PAs are more or less biased with a constant I_BTOT. A base ballasting with the nominal value R_Bext = 400 Ω per unit cell was applied following a strategy denoted as segmented or split, in which such resistances only appear in the dc path and there is no RF performance penalty. The bottom of the laminate was held at T_B.

Let us first consider the halved 24-cell array. Figure 19 reports the PSPICE results corresponding to I_BTOT = 2 mA; the simulation lasted less than 100 s on a normal PC, in spite of the very small V_CE step used. A significant current/temperature nonuniformity is observed as V_CE exceeds 9 V, leading to an I_CTOT collapse; more specifically, the right (internal) column (#7 to #12) conducts the entire current, while the cells belonging to the left (external) one (#1 to #6) tend to turn off. Below V_CE = 11 V, the symmetric cell pairs of the right column (namely, #9 and #10, #8 and #11, and #7 and #12) share the same current. For V_CE higher than 11 V, a bifurcation mechanism occurs for all these pairs, as dictated by slight layout asymmetries: in particular, the top cells (#7, #8, and #9) prevail over the bottom counterparts (#10, #11, and #12, respectively). The uneven behavior is thus enhanced, and I_CTOT decreases more steeply with V_CE. Over the V_CE span from 11 to 12 V, cell #9 is the hottest cell since it suffers from the stronger thermal coupling with the surrounding cells. As V_CE exceeds 12 V, only the adjacent cells #7 to #9 are conducting, whereas cells #10 to #12 run dry; as a consequence, mutual thermal interactions among cells play a minor role, while the behavior is dominated by the SH R_THs of the "active" cells, namely, 541, 533.3, and 531.5 K/W for #7, #8, and #9, respectively, under linear conditions (the closer the cell to the die border, the higher the R_TH). For a higher V_CE, the total current first focuses over cells #7 and #8 (at V_CE = 12.6 V, ΔT_j7 = 500 K, and ΔT_j8 = 700 K), and then, if #8 survives, over cell #7 only.

It must be remarked that introducing an intentional (very small) technological discrepancy between #9 and #10 to favor a slightly higher conduction of #10, for V_CE > 11 V the bottom cells of the right column dominate over the top ones; by further increasing V_CE, cells #11 and #12 sink the whole current, which eventually focuses in the outer #12 suffering from the highest R_TH. The I_CTOT–V_CE curve, including the collapse region, remains instead unaltered.

If the applied I_BTOT is higher, the current nonuniformity (i.e., the collapse onset) and the subsequent bifurcation phenomenon involving symmetric cells occur for slightly lower critical V_CEs, as ET effects are exacerbated by the higher currents (and dissipated powers). Clearly, the temperatures reached by the right-column cells at the bifurcation are higher than in the lower-I_BTOT case. Figure 20 illustrates the scenario corresponding to I_BTOT = 3 mA; here it is shown that, as the bifurcation takes place, the ΔT_j shared by the inner cells #9 and #10 has already exceeded 600 K; this suggests that in a real array the metallization and surrounding interlevel dielectrics of these cells is likely to melt before the bifurcation arises.

In the total absence of ballasting, the V_CE range enjoying uniform current and temperature distribution dramatically reduces; beyond a critical (and low) V_CE, the pair #9, #10 starts taking more current, which translates in the collapse onset in the I_CTOT–V_CE characteristic; then, the bifurcation between symmetric cells in the right column arises, and, for a slightly higher V_CE, the current flows only in cell #9. An example is reported in Figure 21, which corresponds to I_BTOT = 3 mA. It is observed that, as #9 dominates, the cells symmetric with respect to #9 (i.e., #8 and #10, and #7 and #11) tend to exhibit a similar behavior (i.e., they conduct almost the same current and are at the same temperature). Again, by intentionally applying a technological discrepancy leading to a slightly higher current capability for cell #10, the current will focus only on this cell in the deep collapse region, without distorting the I_CTOT–V_CE characteristic.

Finally, the case of emitter ballasting with R_Eext = 4 Ω per cell is examined, as it is considered approximately equivalent to R_Bext = 400 Ω by circuit designers; however, in this case a significant degradation in terms of f_T and f_MAX (both by some GHz), as well as of RF gain, is induced. Figure 22 depicts the individual collector currents of the unit cells and the associated temperature rises above T₀ with I_BTOT = 3 mA applied. By virtue of the reduced ET feedback with respect to the unballasted array, (i) the collapse locus is shifted ahead of about 3.5 V and (ii) the bifurcation involving the right-column cells occurs for much higher temperature values; (iii) in the thermally-unstable nonuniform region, the behavior of the individual currents vs. V_CE resembles that observed in the unballasted case: beyond the bifurcation onset, a current hogging over cell #9 takes place. Another interesting result is that the stabilizing effect is much less effective than the base ballasting with R_Bext = 400 Ω per cell: for this specific I_BTOT, the critical V_CE triggering the collapse is about 6.5 V, whereas R_Bext = 400 Ω allows extending this value to 9 V.

Figure 23 summarizes the comparison between the ballasting schemes, by showing the I_CTOT–V_CE curves simulated at various I_BTOT values for the case of nominal base ballasting (R_Bext = 400 Ω per each cell), emitter ballasting (R_Eext = 4 Ω per each cell), and no ballasting, as well as the corresponding temperature rises over T₀ affecting cell #9. A wide I_BTOT range was selected so as to cover the typical operating current densities [54]. The considerable reduction in the safe operating region for the unballasted case and the inferior aid ensured by R_Eext = 4 Ω with respect to R_Bext = 400 Ω are apparent.

From the overall analysis, the following relevant findings emerge:

• The collapse onset in an I_BTOT-constant I_CTOT–V_CE curve is associated to a uneven current/temperature distribution, wherein the right-column cells (in particular, the inner ones) bear almost all the current.
• The steeper I_CTOT drop in the collapse region is induced by a bifurcation mechanism involving the symmetric cells belonging to the right column. In the base-ballasted case (with R_Bext = 400 Ω) this leads to three adjacent cells conducting all the current (either the top or the bottom ones, depending on small technological/layout discrepancies); a further V_CE increase makes the current flow in two cells, and eventually in only one cell (the outer one). In the unballasted and emitter-ballasted case (with R_Eext = 4 Ω), for V_CE slightly higher than that entailing the bifurcation, the current flows in only one of the inner cells (#9 or #10). This leads to a very sharp and linear temperature increment vs. V_CE of this cell (plainly illustrated for cell #9 in Figure 23b).
• Such a linear nature of the ΔT_j9–V_CE behavior can be straightforwardly explained as follows. Neglecting II effects, which is reasonable in both the unballasted and emitter-ballasted cases, ΔT_j9 is approximately equal to R_TH99(T_j9)·β_F(T_j9)·I_BTOT·V_CE + 58 K (I_B9 ≈ I_BTOT), where R_TH99 is the SH thermal resistance of cell #9, and 58 K is the difference between T_B and T₀; as V_CE increases, there is a compensation between the NTC of β_F and the increase in R_TH99 with temperature due to nonlinear thermal effects.

We shall now focus on half of the 28-cell array; all cells are base-ballasted with R_Bext = 400 Ω. Figure 24 depicts the PSPICE results obtained under CE conditions for I_BTOT = 3.5 mA. It is found that beyond V_CE = 8.5 V the current distribution becomes uneven, leading to the onset of collapse in the I_CTOT–V_CE curve. The right-column cells (#8 to #14) carry all the current, while the left-column counterparts (#1 to #7) turn off. In particular, the current is mostly conducted by the inner cells: the highest by the innermost #11, a slightly lower one by each of the symmetric cells #10, #12, an even lower by #9, #13, and so on. At V_CE = 10.8 V, a bifurcation occurs for these symmetric pairs, and #10, #9, and #8 prevail over #12, #13, and #14, so that only the top group composed by the adjacent #8 to #11 cells conducts. Further increasing V_CE, the current would first focus over the 3-cell group #8 to #10, then over the pair #8, #9, and would eventually flow only in the outermost cell #8, which is affected by the highest R_TH. On the other hand, the reduction in the number of conducting top cells is found to occur after the temperature rise of cells #11, #10, and #9 has well exceeded 600 K; consequently, in the practical case, the metallization and dielectrics over such cells are expected to lose their integrity when still the whole group #8 to #11 is conducting.

As mentioned in Section 3.5, unlike conventional ETNs, the one derived by FANTASTIC allows the reconstruction of the whole linear temperature rise field ΔT_lin(x, y, z) = T_lin(x, y, z) − T₀, which can be easily processed through the calibrated Kirchhoff’s transformation to get the nonlinear ΔT(x, y, z), for selected biasing conditions. Figure 25 shows the ΔT(x, y, z) map for half of the 28-cell array biased with I_BTOT = 3.5 mA and V_CE equal to 6 V (as representative of the uniform operating region), 10 V (collapse region: all the right-column cells are conducting), and 13.3 V (deep/marked collapse: after the bifurcation mechanism, the current flows only through the group #8 to #11).

Lastly, an interesting and fair comparison is performed between the halved portions of the base-ballasted 24- and 28-cell arrays by applying various I_BTOT values ensuring the same total base current density J_BTOT = I_BTOT/A_ETOT in both cases. Results are reported in Figure 26; more specifically, Figure 26a shows the J_CTOT–V_CE characteristic (J_CTOT = I_CTOT/A_ETOT), and Figure 26b depicts the junction temperature rise of cell #9 for the 24-cell array, and of cell #11 for the 28-cell one. The analysis demonstrates that the 28-cell array featuring an odd number of cells (seven) per column is less thermally robust than the 24-cell counterpart with an even number of cells (six) per column (the collapse locus is shifted leftward). This is attributed to the fact that the nonuniform current/temperature distribution triggering the collapse in the 28-cell structure implies that the innermost cell #11 takes more current than the others, while two cells (#9 and #10) concurrently bear this task in the 24-cell array. It is worth noting that, although this seems to be an expected results, there are still many designers using arrays with an odd number of cells per column.

5. Conclusions

In this paper, an efficient simulation approach has been used to analyze the dc electrothermal behavior of test devices and arrays for output stages of power amplifiers in InGaP/GaAs HBT technology. The approach relies on a full circuit representation of the structures under investigation (also referred to as macrocircuit), the solution of which can be evaluated by any circuit simulation software and requires tens of seconds at most, despite the complexity of the analysis. The macrocircuit is based on the thermal equivalent of the Ohm’s law, and includes subcircuits to describe the unit cells, as well as a thermal feedback block to account for the power-temperature feedback. The thermal feedback block is obtained by combining (i) a FEM thermal tool aided by an in-house routine to generate an exceptionally accurate 3-D geometry/mesh of the structure, (ii) the FANTASTIC code to automatically get an equivalent thermal network without the need of simulations or user’s experience, (iii) a preliminarily-calibrated Kirchhoff’s transformation to include nonlinear thermal effects. The test devices have been analyzed under all the bias conditions of interest. An overview has been given on the thermally- and avalanche-induced distortion in the I–V characteristics, the limits of the safe behavior have been identified, and the beneficial effect of base ballasting has been explored. As far as the HBT arrays are concerned, the approach better shows its potential, as the individual currents, temperatures, and key parameters of all unit cells can be monitored. Some of the most important findings are: the base ballasting has been found to be more effective than emitter ballasting, which is typically suggested for breakdown-limited bipolar transistors; the arrays are more thermally-robust if arranged in columns with an even number of unit cells, where two central cells concurrently bear the heat coming from the outer ones as a nonuniform operating condition occurs. The approach is well suited to support engineers and designers in making choices oriented to develop more thermally-rugged and reliable circuits through, e.g., layout and/or nonuniform ballasting optimization.