Smooth-Transition Simple Digital PWM Modulator for Four-Switch Buck-Boost Converters

Abstract

This paper proposes a simple, hardware-efficient digital pulse width modulator for a 4SBB that enables operation in Buck, Boost, and Buck+Boost modes, achieving smooth transitions between the different modes. The proposed modulator is simulated using Simulink and experimentally demonstrated using a 500 W 4SBB converter with 24 V input voltage and 12–36 V output voltage range.

1. Introduction

Cascaded Buck-Boost converters are being extensively used in a variety of applications. Two-switch cascaded Buck-Boost converters were first proposed as Power Factor Correction circuits [1]; evolving from this topology, four switch non-inverting Buck-Boost (4SBB) converters have become a preferred choice in non-isolated applications where both voltage step-up and step-down are required. Its applications include space power systems [2], DC microgrids [3], photovoltaic systems [4], and DC power systems [5]. Among other things, this topology features bidirectional power transfer capability, high efficiency, simplicity, and voltage step-up/step-down capabilities. Figure 1 shows a diagram of a conventional 4SBB including a simple digital voltage feedback loop.

Considering v₁ and v₂ as the input and output voltage respectively, it is desirable to operate the 4SBB as a Buck converter when v₂ < v₁. This can be simply achieved by turning M₄ on and M₃ off, while switching M₁ and M₂. Conversely, when v₂ > v₁, it is desirable to turn on M₁ and turn off M₂, and operate the 4SBB in a Boost-like manner switching M₃ and M₄. Only one pair of switches operates in each mode, thus minimizing switching losses and enabling high-efficiency operation. Note that this approach requires near-unity conversion ratios when v₁ ≈ v₂, which are difficult to achieve in practice typically due to pulse-width limitations imposed by driver ICs [6].

Several alternative operating modes have been proposed in the literature to address this issue. In [7] a mixed Buck+Boost mode with all four switches operating at the same time is used to achieve near-unity conversion ratios. In [8] a transition technique is proposed to achieve a full-range, linear conversion ratio using hysteresis methods implemented on a Digital Signal Controller (DSC). However, small discontinuities inherent to this method are perceived in the output voltage. In [9] a DSC is also used to achieve a full-range, continuous conversion ratio using a Buck-Boost operation applying model prediction control. This added complexity limits operation due to long processing times. In [10] a bypass mode is used when v₁ ≈ v₂, achieving an interesting increase in the efficiency at the cost of losing voltage regulation capabilities. In [11] a different modulation technique, in which the four transistors are switching in the complete operating range, is used to control the converter. A complex transition method based on inductor current sensing is used in [12]. In [13,14] four-mode modulation and duty-locking methods are proposed respectively to operate in the transition region, achieving full-range conversion capabilities. Furthermore, ref. [15] uses a similar four-mode modulation approach, decreasing switching frequency during buck-boost operation to minimize losses.

Although the previously mentioned papers provide different methods for smooth control, little emphasis is placed on the analysis of the transition method and its subsequent implementation on a digital platform, which is the scope of this work.

The operation of the 4SBB converter in Buck+Boost mode used in [7] has proven to be the most adequate approach to achieve simple and efficient near-unity conversion ratios. However, this approach requires generating two distinct duty cycles to control each pair of switches from the control signal d[n]. This paper addresses the issue of adequately generating those signals in the 4SBB converter focusing on the Buck+Boost mode operation and the transitions between modes. In that context, this work proposes a simple Digital Pulse-Width Modulator (DPWM) for a 4SBB converter that automatically enables full-range conversion ratios; the converter operates in the three modes (Buck, Boost, and Buck+Boost) depending on the required conversion ratio, generating the necessary control signals for all switches in each mode and achieving smooth transitions between the different modes. The DPWM is based on a simple state machine that runs on top of two conventional DPWM modulators, each one controlling one pair of switches, M₁/M₂ and M₃/M₄, that can be implemented in an FPGA or ASIC, resulting in a low-resources and easily scalable solution.

The paper is organized as follows: Section 2 describes the operation of the 4SBB converter with near-unity conversion ratios and unveils the problem that arises in such condition; Section 3 describes the operation principles and a simple FPGA-based implementation of the proposed smooth-transition DPWM; Section 4 shows simulation and experimental results; and Section 5 concludes the paper.

2. Operation of the 4SBB Converter

Figure 2a shows an ideal map of the typical operating modes of the 4SBB converter as a function of the control signal d[n] in Figure 1. The conversion ratio M is defined as

$$\mathrm{M}=\frac{{\mathrm{v}}_2}{{\mathrm{v}}_1}.$$

(1)

When M < 1, the 4SBB converter operates as a Buck converter, leaving M₃ off and M₄ on while switching M₁/M₂. In this mode, M₁ is switched on during a fraction of the switching period T_s equal to T_s·d_buck[n]. When M > 1, the 4SBB is operated in Boost mode: M₁ is left on and M₂ is off, while switching M₃/M₄. In this mode M₃ is on during a fraction of the switching period equal to T_s·d_boost[n]. Figure 3 shows a set of typical operating waveforms in each mode of operation.

As shown in Figure 1, the control loop produces a unique control signal d[n] from which d_buck[n] and d_boost[n] need to be obtained. According to previously the described operation, a straightforward mapping to obtain d_buck[n] and d_boost[n] from d[n] is:

$$\begin{array}{c}{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]=\mathrm{d}\left[\mathrm{n}\right]\\ { \mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]=0\end{array}\}\hspace{1em}\hspace{1em}\hspace{1em}\mathrm{when} \mathrm{d}\left[\mathrm{n}\right]\le 1$$

(2)

$$\begin{array}{c}{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]=1\\ {\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]=\mathrm{d}\left[\mathrm{n}\right]-1\end{array}\}\hspace{1em}\mathrm{when} \mathrm{d}\left[\mathrm{n}\right]>1$$

(3)

where d[n] ∈ [0,2]. With this approach d[n] ≤ 1 indicates Buck operation whereas d[n] > 1 indicates Boost operation.

However, this simple mapping is not feasible in practical converters; due to pulse-width limitations imposed by MOSFET driver ICs, an upper limit for d_buck[n] (d_buck,max) as well as a lower limit for d_boost[n] (d_boost,min) exist. Even if very short control pulses could be produced by the drivers, semiconductor devices may not be able to fully switch in such short periods, causing circuit malfunction. Therefore, it is in general desirable to limit the actual operating duty cycles such that d_buck[n] < d_buck,max and d_boost[n] > d_boost,min. This causes the dead-zone of unachievable conversion ratios shown in Figure 2b, which in turn leads to the modification of (2) and (3) as:

$$\begin{array}{c}{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]=\mathrm{d}\left[\mathrm{n}\right]\\ { \mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]=0\end{array}\}\hspace{1em}\hspace{1em}\hspace{1em}\mathrm{when} \mathrm{d}\left[\mathrm{n}\right]\le {\mathrm{d}}_{\mathrm{buck},\max }$$

(4)

$$\begin{array}{c}{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]={\mathrm{f}}_{\mathrm{buck}}\left(\mathrm{d}\left[\mathrm{n}\right]\right)\\ {\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]={\mathrm{f}}_{\mathrm{boost}}\left(\mathrm{d}\left[\mathrm{n}\right]\right)\end{array}\}{\hspace{1em}\mathrm{when} \mathrm{d}}_{\mathrm{buck},\max }<\mathrm{d}\left[\mathrm{n}\right]<1+{\mathrm{d}}_{\mathrm{boost},\min } (\mathrm{dead} \mathrm{zone})$$

(5)

$$\begin{array}{c}{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]=1\\ {\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]=\mathrm{d}\left[\mathrm{n}\right]-1\end{array}\}\hspace{1em}\mathrm{when} \mathrm{d}\left[\mathrm{n}\right]\ge 1+{\mathrm{d}}_{\mathrm{boost},\min }$$

(6)

Several representative alternatives proposed in the literature to overcome this problem are briefly described next.

2.1. Bypass and Saturation Modes

A simple solution proposed in [10] is the use of a bypass mode. For the values of d[n] that fall into the dead zone, the input and output voltages are relatively close and, in this mode, the input is directly connected to the output, therefore having v₂ ≈ v₁. This solution is easily implemented using the following mapping for the dead-zone:

$$\begin{array}{c}{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]=1\\ { \mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]=0\end{array}\}{\hspace{1em}\hspace{1em}\mathrm{when} \mathrm{d}}_{\mathrm{buck},\max }<\mathrm{d}\left[\mathrm{n}\right]<1+{\mathrm{d}}_{\mathrm{boost},\min }$$

(7)

A very good efficiency in the dead-zone is obtained using this solution because none of the transistors are switching. The main disadvantage of this technique is the loss of output voltage regulation capabilities.

A similar solution consists in using the saturated values of d_buck[n] and d_boost[n] when d[n] is in the dead-zone. The corresponding mapping is:

$$\begin{array}{c}{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]={\mathrm{d}}_{\mathrm{buck},\max }\\ { \mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]=0\end{array}\}{\hspace{1em}\hspace{1em}\mathrm{when} \mathrm{d}}_{\mathrm{buck},\max }<\mathrm{d}\left[\mathrm{n}\right]<1$$

(8)

$$\begin{array}{c}{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]=1\\ { \mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]={ \mathrm{d}}_{\mathrm{boost},\min }\end{array}\}\hspace{1em}\hspace{1em}\mathrm{when} 1<\mathrm{d}\left[\mathrm{n}\right]<1+{ \mathrm{d}}_{\mathrm{boost},\min }$$

(9)

With this technique voltage regulation capabilities are also lost. However, note that in close-loop operation the controller will jump between the nearest allowable duty cycles to, on average, produce the required output voltage. Figure 4 shows the conversion ratio as a function of d[n] with these two alternative solutions.

2.2. Buck-Boost Mode

The 4SBB can also be operated as a Buck-Boost converter when M ≈ 1 [16], which can simply be achieved by setting d_buck[n] = d_boost[n]. Note that in this mode of operation the conversion ratio can be expressed as

$$\mathrm{M}=\frac{{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]}{1-{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]}=\frac{{\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]}{1-{\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]},$$

(10)

M = 1 can be achieved by setting d_buck = d_boost = 1/2. Therefore, a simple mapping that fulfills the desired behavior can be defined as:

$$\begin{array}{c}{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]=\frac{\mathrm{d}\left[\mathrm{n}\right]}{2}\\ { \mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]=\frac{\mathrm{d}\left[\mathrm{n}\right]}{2}\end{array}\}{\hspace{1em}\hspace{1em}\mathrm{when} \mathrm{d}}_{\mathrm{buck},\max }<\mathrm{d}\left[\mathrm{n}\right]<1+{\mathrm{d}}_{\mathrm{boost},\min }$$

(11)

where the fact that the converter enters Buck-Boost mode when d[n] ≈ 1 has been used to approximate d_buck[n] = d_boost[n] ≈ d[n]/2. With this definition both d_buck[n] and d_boost[n] can be immediately computed from d[n] at almost no hardware cost. Figure 5 shows the conversion ratio as a function of d[n] with this operating mode.

However, operation of the 4SBB converter as a true Buck-Boost brings certain drawbacks. First, it may severely increase current stresses in the power stage. Note that the maximum inductor current ripple during Buck operation is

$$\max \{{\mathsf{\Delta }\mathrm{i}}_{\mathrm{L},\mathrm{buck}}\}=\frac{{\mathrm{v}}_1{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]\left(1-{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]\right){\mathrm{T}}_{\mathrm{s}}}{\mathrm{L}}=\frac{{\mathrm{V}}_{\mathrm{in}}{\mathrm{T}}_{\mathrm{s}}}{4\mathrm{L}} .$$

(12)

In the 4SBB operated in true Buck-Boost mode as described above, inductor current ripple is

$$\max \{{\mathsf{\Delta }\mathrm{i}}_{\mathrm{L},\mathrm{buck}-\mathrm{boost}}\}=\frac{{\mathrm{v}}_1{\mathrm{d}}_{\mathrm{buck}-\mathrm{boost}}\left[\mathrm{n}\right]{\mathrm{T}}_{\mathrm{s}}}{\mathrm{L}}\approx \frac{{\mathrm{V}}_{\mathrm{in}}{\mathrm{T}}_{\mathrm{s}}}{2\mathrm{L}} ,$$

(13)

That is, the inductor current ripple is twice as large as the worst-case Buck mode ripple, and may even exceed rated inductor current ripple for the design, depending on the maximum required step-up ratio. Second, the efficiency of the converter while operating in this mode decreases significantly due to the increased circulating currents.

Also note that when the converter enters Buck-Boost mode the inductor current ripple suffers an abrupt change, from almost zero to a very large value. This sudden change in the converter state variables may pose extra burdens on the control loop and is not desirable. The abrupt state change may also cause stability issues [11].

2.3. Buck+Boost Mode

Figure 6 shows the operating waveforms that correspond to the Buck+Boost operation mode. It consists in operating M₁/M₂ with duty cycle d_buck[n], while at the same time M₃/M₄ are operated with duty cycle d_boost[n]. Using the waveforms of Figure 6, the inductor volt-seconds balance can be found as:

$${\mathrm{v}}_1·{\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]+\left({\mathrm{v}}_1-{\mathrm{v}}_2\right)·\left({\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]-{\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]\right)-{\mathrm{v}}_2·\left(1-{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]\right)=0 ,$$

(14)

resulting in the following conversion ratio:

$$\mathrm{M}=\frac{{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]}{1-{\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]} ,$$

(15)

This mode of operation is advantageous as it does not increase inductor current ripple; it also maintains high efficiency operation during the transition and avoids abrupt changes in the inductor current. However, a question arises on how to appropriately obtain d_buck[n] and d_boost[n] from d[n] given the conditions d_buck[n] < d_buck,max and d_boost[n] > d_boost,min.

To gain insight into this issue the state of the converter can be plotted in a (d_buck[n],d_boost[n]) plane as shown in Figure 7. Assume that the converter is in Buck mode and d[n] is increasing: the converter then moves along the X axis until it reaches point A at the boundary of the region of unachievable duty cycles. It must then jump to a feasible point B and, after that, move towards D following a certain trajectory (intermediate points C could also be used as it will be shown next). Note that d[n] is being increased throughout the process. Provided that the simple mapping stated in (4) and (6) is maintained, once d[n] reaches d_boost,min the converter can safely enter Boost mode where (6) applies and thus move to point E. Note that the selection of points B, C, and D and the trajectory between them determine the evolution of the conversion ratio (M) as a function of d[n]. This issue is addressed in the next section, and it is the main contribution of this work.

3. Smooth Transition DPWM

In this section a simple method is proposed to achieve a continuous and smooth behavior of the conversion ratio M with respect to d[n]. To find a mapping d[n] → (d_buck[n],d_boost[n]) that fulfills such requirement, it is useful to examine M in the (d_buck[n],d_boost[n]) plane. Figure 8a shows contour plots of constant M for different (d_buck[n],d_boost[n]) pairs. A certain mapping would thus be represented as a trajectory in the (d_buck[n],d_boost[n]) plane. Assume that the converter is operating in Buck mode, with d_buck[n] = d[n] and d_boost[n] = 0, and d[n] is increased until it reaches the maximum feasible duty cycle. To ensure continuity in M(d[n]), (d_buck[n],d_boost[n]) pairs can simply be chosen such that the trajectory moves along a contour of constant M at the transition. Such trajectory is represented in Figure 8b. After moving from B to D, once d[n] reaches d_boost,min the converter can move back to Boost mode with d_boost[n] = d[n] − 1, d_buck[n] = 1. Note that the goal is also to maintain Equations (4) and (6) to mimic the ideal mapping to the largest possible extent.

When the converter is in Boost mode, d_boost[n] = d[n] − 1 and d_buck[n] = 1, and the duty cycle is being decreased, the opposite applies: at the transition point d[n] = d_boost,min, the converter enters Buck+Boost mode moving along a constant M contour. Such trajectory is the same as the one represented in Figure 2b, but just in the opposite direction. Once d[n] reaches d_buck,max, the converter can move back to Buck mode with d_boost[n] = 0 and d_buck[n] = d[n].

3.1. Ideal Smooth Transition DPWM

The conversion ratio as a function of d_buck[n] and d_boost[n] can be written as:

$$\mathrm{M}\left({\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right],{ \mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]\right)=\frac{{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]}{1-{\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]}.$$

(16)

Note that (16) is equal to (15) but in this case is used to define the conversion ratio for all modes of operation (d_boost[n] = 0 in Buck mode, d_buck[n] = 1 in Boost mode). Moreover, in Buck mode the conversion ratio is:

$$\mathrm{M}\left({\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right],{ \mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]\right)=\mathrm{d}\left[\mathrm{n}\right],$$

(17)

while in Boost mode the conversion ratio is:

$$\mathrm{M}\left({\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right],{ \mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]\right)=\frac{1}{1-\left(\mathrm{d}\left[\mathrm{n}\right]-1\right)} .$$

(18)

To mimic the ideal mapping in (2) and (3), the Buck mode conversion ratio (17) is desired when d[n] < 1, whereas the Boost mode conversion ratio (18) is desired when d[n] > 1. To fulfill these conditions while in Buck+Boost mode (i.e., also fulfilling (16)), (d_buck[n],d_boost[n]) pairs must be appropriately chosen.

To ensure continuity in M(d[n]) during the transition from Buck to Buck+Boost mode, from (16) and (17) the required d_buck[n] that guarantees moving along a constant M trajectory in Buck+Boost mode can be found as,

$${\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]=\mathrm{d}\left[\mathrm{n}\right]·\left(1-{\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]\right).$$

(19)

One possibility to determine (d_buck[n],d_boost[n]) pairs to obtain an ideal transition is to select d_boost[n] as d_boost,min and calculate d_buck[n] using (19) as:

$${\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]=\mathrm{d}\left[\mathrm{n}\right]·\left(1-{\mathrm{d}}_{\mathrm{boost},\min }\right).$$

(20)

Using this approach, two different but similar trajectories to go from B to D in Figure 7 can be followed. Depending on the values of d_buck,max and d_boost,min the two possibilities presented in Figure 9 can be considered.

d_buck,max < 1 − d_boost,min (Figure 9a): d_buck[n] obeys (20) while d[n] is lower than unity (trajectory B-C1). At C1, d_buck[n] is fixed as d_buck,max and along the trajectory C1-C d_boost[n] is calculated using (16) and (17):

$${\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]=1-\frac{{\mathrm{d}}_{\mathrm{buck},\max }}{\mathrm{d}\left[\mathrm{n}\right]} .$$

(21)

When point C is reached (d[n] = 1, M = 1) the trajectory C-D begins. In this case, the conversion ratio of the Boost mode (18) must be followed to ensure continuity in M(d[n]) during the transition between Buck+Boost and Boost mode. Consequently, d_boost[n] must be calculated using (16) and (18):

$${\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]=1-\left(1-\left(\mathrm{d}\left[\mathrm{n}\right]-1\right)\right)·{\mathrm{d}}_{\mathrm{buck}}$$

(22)

Again for simplicity, d_buck[n] remains fixed as d_buck,max and d_boost[n] can thus be simplified to:

$${\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]=1-\left(1-\left(\mathrm{d}\left[\mathrm{n}\right]-1\right)\right)·{\mathrm{d}}_{\mathrm{buck},\max }$$

(23)

The previous definitions are summarized in

Table 1. Definition of (d_buck[n],d_boost[n]) pairs to go from B to D when d_buck,max < 1 − d_boost,min.

d[n] Ranges	dbuck[n]	dboost[n]	Conversion Ratio (M)	Trajectory
$\mathrm{d}\left[\mathrm{n}\right]<\frac{{\mathrm{d}}_{\mathrm{buck},\max }}{1-{\mathrm{d}}_{\mathrm{boost},\min }}$	$\mathrm{d}\left[\mathrm{n}\right]\left(1-{\mathrm{d}}_{\mathrm{boost},\min }\right)$	${\mathrm{d}}_{\mathrm{boost},\min }$	$\mathrm{d}\left[\mathrm{n}\right]$	B-C1
$\frac{{\mathrm{d}}_{\mathrm{buck},\max }}{1-{\mathrm{d}}_{\mathrm{boost},\min }}<\mathrm{d}\left[\mathrm{n}\right]<1$	${\mathrm{d}}_{\mathrm{buck},\max }$	$1-\frac{{\mathrm{d}}_{\mathrm{buck},\max }}{\mathrm{d}\left[\mathrm{n}\right]}$	$\mathrm{d}\left[\mathrm{n}\right]$	C1-C
$\mathrm{d}\left[\mathrm{n}\right]>1$	${\mathrm{d}}_{\mathrm{buck},\max }$	$1-\left(2-\mathrm{d}\left[\mathrm{n}\right]\right){\mathrm{d}}_{\mathrm{buck},\max }$	$\frac{1}{1-\left(\mathrm{d}\left[\mathrm{n}\right]-1\right)}$	C-D

and depicted in Figure 3a.

d_buck,max > 1 − d_boost,min (Figure 9b): from B to C, d_boost[n] is fixed as d_boost,min and d_buck[n] is given by (20) as in the previous case. However, in this case d[n] reaches 1 before d_buck[n] (calculated using (20)) reaches d_buck,max. In this case d_buck[n] must be calculated using the conversion ratio of the Boost mode (18) to ensure continuity in M(d[n]) during the transition between Buck+Boost and Boost mode. To follow the trajectory depicted between C and C1 in Figure 9b d_boost[n] remains as d_boost,min and d_buck[n] must be calculated to perform the conversion ratio of the Boost mode (because d[n] > 1) and is given using (16) and (18) as:

$${\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]=\frac{1-{\mathrm{d}}_{\mathrm{boost},\min }}{1-\left(\mathrm{d}\left[\mathrm{n}\right]-1\right)} .$$

(24)

When using (24) d_buck[n] reaches d_buck,max, then d_buck[n] is fixed as d_buck,max and the trajectory C1-D takes place; d_boost[n] is calculated using (23). This possibility is summarized in

Table 2. Definition of (d_buck[n],d_boost[n]) pairs to go from B to D when d_buck,max > 1 − d_boost,min.

d[n] Ranges	dbuck[n]	dboost[n]	Conversion Ratio (M)	Trajectory
$\mathrm{d}\left[\mathrm{n}\right]<1$	$\mathrm{d}\left[\mathrm{n}\right]\left(1-{\mathrm{d}}_{\mathrm{boost},\min }\right)$	${\mathrm{d}}_{\mathrm{boost},\min }$	$\mathrm{d}\left[\mathrm{n}\right]$	B-C
$1\text{<}\mathrm{d}\left[\mathrm{n}\right]<2-\frac{1-{\mathrm{d}}_{\mathrm{boost},\min }}{{\mathrm{d}}_{\mathrm{buck},\max }}$	$\frac{1-{\mathrm{d}}_{\mathrm{boost},\min }}{1-\left(\mathrm{d}\left[\mathrm{n}\right]-1\right)}$	${\mathrm{d}}_{\mathrm{boost},\min }$	$\frac{1}{1-\left(\mathrm{d}\left[\mathrm{n}\right]-1\right)}$	C-C1
$\mathrm{d}\left[\mathrm{n}\right]>2-\frac{1-{\mathrm{d}}_{\mathrm{boost},\min }}{{\mathrm{d}}_{\mathrm{buck},\max }}$	${\mathrm{d}}_{\mathrm{buck},\max }$	$1-\left(2-\mathrm{d}\left[\mathrm{n}\right]\right){\mathrm{d}}_{\mathrm{buck},\max }$	$\frac{1}{1-\left(\mathrm{d}\left[\mathrm{n}\right]-1\right)}$	C1-D

and depicted in Figure 9b.

Note that when d_buck,max = 1 − d_boost,min, trajectory C-C1 does not exist and consequently both Figure 9a,b and Table 1 and Table 2 are the same.

Figure 10a shows M as d[n] sweeps from 0.8 to 1.2 using the previously defined mapping. Figure 10b shows the values of d_buck[n] and d_boost[n] selected by the state machine in each operation mode using d_buck,max = 0.95 and d_boost,min = 0.05. Note that a perfectly smooth transition is achieved as expected.

Note that, although it provides nearly perfect transitions, this ideal mapping requires a significant amount of computational resources. For an FPGA or ASIC implementation, it is desirable to simplify (19), (21), (22), and (24).

3.2. Simplified Smooth Transition DPWM

In order to simplify the computation of d_buck[n] and d_boost[n], a linearization of the expressions in Table 1 and Table 2 is proposed. For simplicity, d_buck,max and 1 − d_boost,min will be assumed to be equal. As has been previously stated, when d_buck,max = 1 − d_boost,min trajectory C-C1 or C1-C does not exist and the trajectories in Figure 9a,b become the one shown in Figure 11. Considering this simplification only (19) and (22) need to be taken into account.

When d[n] = d_buck,max, the transition from Buck to Buck+Boost mode begins. In this transition, jump from A to B and then trajectory from B to C, d_boost[n] is defined as d_boost,min and d_buck[n] is given by (20); this expression can be approximated by its Taylor series as:

$${\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]={\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]{|}_{\mathrm{B}}+\frac{\partial {\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]}{\partial \mathrm{d}\left[\mathrm{n}\right]}{|}_{\mathrm{B}}·\left(\mathrm{d}\left[\mathrm{n}\right]-\mathrm{d}\left[\mathrm{n}\right]{|}_{\mathrm{B}}\right),$$

(25)

where the values at B are defined as follows:

$$\mathrm{d}\left[\mathrm{n}\right]{|}_{\mathrm{B}}={\mathrm{d}}_{\mathrm{buck},\max },$$

(26)

$$\begin{array}{ll}{\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]{|}_{\mathrm{B}}={\mathrm{d}}_{\mathrm{buck},\mathrm{B}}& =\mathrm{d}\left[\mathrm{n}\right]{|}_{\mathrm{B}}·\left(1-{\mathrm{d}}_{\mathrm{boost},\min }\right)\\ & ={\mathrm{d}}_{\mathrm{buck},\max }·\left(1-{\mathrm{d}}_{\mathrm{boost},\min }\right).\end{array}$$

(27)

Using (26) and (27) d_buck[n] is given by:

$${\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]={\mathrm{d}}_{\mathrm{buck},\mathrm{B}}+\left(1-{\mathrm{d}}_{\mathrm{boost},\min }\right)·\left(\mathrm{d}\left[\mathrm{n}\right]-{\mathrm{d}}_{\mathrm{buck},\max }\right).$$

(28)

Finally, to avoid multiplications in (28), (1 − d_boost,min) is approximated by 1, allowing a simple calculation of the value of d_buck[n] as:

$${\mathrm{d}}_{\mathrm{buck}}\left[\mathrm{n}\right]\approx {\mathrm{d}}_{\mathrm{buck},\mathrm{B}}+\mathrm{d}\left[\mathrm{n}\right]-{\mathrm{d}}_{\mathrm{buck},\max }={\mathrm{d}}_{\mathrm{buck},\max }·\left(1-{\mathrm{d}}_{\mathrm{boost},\min }\right)+\mathrm{d}\left[\mathrm{n}\right]-{\mathrm{d}}_{\mathrm{buck},\max } .$$

(29)

This trajectory ends when d_buck[n], calculated using (29), is equal to d_buck,max and the point C is reached. To follow the trajectory C–D, d_buck[n] is now defined as d_buck,max and d_boost[n] is given by (22); this expression can be also approximated by its Taylor series as:

$${\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]={\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]{|}_{\mathrm{C}}+\frac{\partial {\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]}{\partial \mathrm{d}\left[\mathrm{n}\right]}{|}_{\mathrm{C}}·\left(\mathrm{d}\left[\mathrm{n}\right]-\mathrm{d}\left[\mathrm{n}\right]{|}_{\mathrm{C}}\right),$$

(30)

where the values at C are defined using (29) as:

$$\mathrm{d}\left[\mathrm{n}\right]{|}_{\mathrm{c}}=2{\mathrm{d}}_{\mathrm{buck},\max }-{\mathrm{d}}_{\mathrm{buck},\max }·\left(1-{\mathrm{d}}_{\mathrm{boost},\min }\right),$$

(31)

$${\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]{|}_{\mathrm{C}}={\mathrm{d}}_{\mathrm{boost},\mathrm{C}}={\mathrm{d}}_{\mathrm{boost},\min }.$$

(32)

Using (31) and (32) d_boost[n] is given by:

$${\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]={\mathrm{d}}_{\mathrm{boost},\mathrm{C}}+{\mathrm{d}}_{\mathrm{buck},\max }·\left(\mathrm{d}\left[\mathrm{n}\right]-2{\mathrm{d}}_{\mathrm{buck},\max }+{\mathrm{d}}_{\mathrm{buck},\max }·\left(1-{\mathrm{d}}_{\mathrm{boost},\min }\right)\right).$$

(33)

Once again, to avoid simplifications in (33), d_buck,max is approximated by 1, resulting in:

$${\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]\approx {\mathrm{d}}_{\mathrm{boost},\min }+\mathrm{d}\left[\mathrm{n}\right]-2{\mathrm{d}}_{\mathrm{buck},\max }+{\mathrm{d}}_{\mathrm{buck},\max }·\left(1-{\mathrm{d}}_{\mathrm{boost},\min }\right).$$

(34)

Table 3. Definition of (d_buck[n],d_boost[n]) pairs to go from B to D as a function of d[n] using the proposed simplifications. Note that all the expressions are in function of d[n], d_buck,max, and d_boost,min (d_buck,B = d_buck,max·(1 − d_boost,min)).

d[n]	dbuck[n]	dboost[n]	Trajectory
$\mathrm{d}\left[\mathrm{n}\right]<2{\mathrm{d}}_{\mathrm{buck},\max }-{\mathrm{d}}_{\mathrm{buck},\mathrm{B}}$	${\mathrm{d}}_{\mathrm{buck},\mathrm{B}}+\mathrm{d}\left[\mathrm{n}\right]-{\mathrm{d}}_{\mathrm{buck},\max }$	${\mathrm{d}}_{\mathrm{boost},\min }$	B–C
$\mathrm{d}\left[\mathrm{n}\right]>2{\mathrm{d}}_{\mathrm{buck},\max }-{\mathrm{d}}_{\mathrm{buck},\mathrm{B}}$	${\mathrm{d}}_{\mathrm{buck},\max }$	${\mathrm{d}}_{\mathrm{boost}, \min }+\mathrm{d}\left[\mathrm{n}\right]-2{\mathrm{d}}_{\mathrm{buck},\max }+{\mathrm{d}}_{\mathrm{buck},\mathrm{B}}$	C–D

summarizes the approximated expressions to calculate (d_buck[n],d_boost[n]) pairs and to obtain the trajectory presented in Figure 11.

Using (29) and (34), a simple modulator that chooses adequate (d_buck[n],d_boost[n]) pairs while maintaining quasi-smooth transitions can be implemented. This method reduces the computational requirements and the time required to calculate each duty cycle allowing a very simple and cost-effective FPGA or ASIC implementation.

With the proposed implementation and a proper selection of d_buck,B, a completely smooth transition can be obtained between Buck and Buck+Boost mode while a small discontinuity appears in the transition between Buck+Boost and Boost mode (see Figure 12a,b). To avoid steps in the transition between Buck and Buck+Boost mode, the point d_buck,B has been defined using (27).

The step in the transition between Buck+Boost and Boost mode is due to the approximations carried out in (29) and (34). Figure 12a shows a representation of M(d[n]) using the proposed implementation in Table 3 and values of d_buck,max = 0.95 and d_boost,min = 0.05. As can be seen, the step in the transition between Buck+Boost and Boost mode is relatively small. However, for wider ranges of forbidden values of d_buck[n] and d_boost[n] (wider dead zone) the step can be higher. Figure 12b shows M(d[n]) using the same implementation with values of d_buck,max = 0.9 and d_boost,min = 0.1. A simple modification is proposed next to reduce the magnitude of the discontinuity.

3.3. Simplified Smooth Transition DPWM with Distributed Conversion Ratio Steps

The discontinuity can be easily distributed between both transitions using a different value for d_buck,B. The new value that replaces d_buck,B is called d_buck,B2. To determine the value of d_buck,B2, first the error in the conversion ratio obtained using d_buck,B, ΔM, is calculated as:

$$\Delta \mathrm{M}={\mathrm{M}}_{\mathrm{buck}+\mathrm{boost}}{|}_{\mathrm{D}}-{\mathrm{M}}_{\mathrm{boost}}{|}_{\mathrm{E}}.$$

(35)

$${\mathrm{M}}_{\mathrm{boost}}{|}_{\mathrm{E}}=\frac{1}{1-{\mathrm{d}}_{\mathrm{boost}, \min }},$$

(36)

$${\mathrm{M}}_{\mathrm{buck}+\mathrm{boost}}{|}_{\mathrm{D}}=\frac{{\mathrm{d}}_{\mathrm{buck},\max }}{1-{\mathrm{d}}_{\mathrm{boost}}\left[\mathrm{n}\right]}=\frac{{\mathrm{d}}_{\mathrm{buck},\max }}{-2{\mathrm{d}}_{\mathrm{boost}, \min }+2{\mathrm{d}}_{\mathrm{buck},\max }-{ \mathrm{d}}_{\mathrm{buck},\mathrm{B}}},$$

(37)

Using (37) the new value (d_buck,B2) to distribute the step in both transitions can be calculated as:

$${\mathrm{d}}_{\mathrm{buck},\mathrm{B}2}={\mathrm{d}}_{\mathrm{buck},\mathrm{B}}-\Delta \mathrm{M}/2.$$

(38)

Figure 12c shows the results, where the discontinuity has been evenly distributed between both transitions.

Table 4. Comparison of the conversion ratio obtained with different implementations.

Implementation	Error	Normalized
dbuck,max = 0.95, dboost,min = 0.05. One step in the Boost transition	1.04 × 10−5	4.16
dbuck,max = 0.95, dboost,min = 0.05. Two steps distributed	2.50 × 10−6	1
dbuck,max = 0.95, dboost,min = 0.05. Buck-Boost mode.	8.09 × 10−4	323.6
dbuck,max = 0.90, dboost,min = 0.10. One step in the Boost transition	2.13 × 10−4	4.34
dbuck,max = 0.90, dboost,min = 0.10. Two steps distributed	4.90 × 10−5	1
dbuck,max = 0.90, dboost,min =0.10. Buck-Boost mode	3.17 × 10−3	64.69

shows an estimated error of the different implementations proposed. The Buck-Boost solution presented in Figure 5 and the ideal solution shown in Figure 10 are also shown for reference. This error is calculated using the following expression,

$$\mathrm{error}=\frac{\int {({\mathrm{M}}_{\mathrm{ideal}}\left(\mathrm{d}\left[\mathrm{n}\right]\right)-{\mathrm{M}}_{\mathrm{comp}}\left(\mathrm{d}\left[\mathrm{n}\right]\right))}^2}{\int {\mathrm{M}}_{\mathrm{ideal}}{\left(\mathrm{d}\left[\mathrm{n}\right]\right)}^2}{ \mathrm{for} \mathrm{d}}_{\mathrm{buck},\max }<\mathrm{d}\left[\mathrm{n}\right]<1+{\mathrm{d}}_{\mathrm{boost},\min },$$

(39)

M_ideal(d[n]) being the conversion ratio of the ideal solution and M_comp(d[n]) the conversion ratio of the implementation under comparison, while d[n] is increased from d_buck,max to 1+d_boost,min. Figure 13 shows the different strategies that have been presented in an example with d_buck,max = 0.9 and d_boost,min = 0.1. From Figure 13 and Table 4, the implementation that distributes the step in both transitions achieves the best results.

3.4. Complete Smooth Transition DPWM with Hysteresis and Dead-Times

During practical operation two additional issues arise. First, a hysteresis value (h) needs to be introduced to avoid undesired chattering between modes, in a similar way as in [8]. This value is applied to change from Buck+Boost mode to either Boost or Buck mode.

Second, the use of dead times in each pair of transistors is required. These introduce a slight decrease in the effective duty cycle that in turn causes a decrease in the output voltage and thus in the conversion ratio. In Buck or in Boost mode, only one pair of transistors is switching and thus only its dead time affects the conversion ratio. However, in Buck+Boost mode the four transistors are switching and both dead times contribute to decrease the conversion ratio. This effect can be easily accounted for by adding its value to the calculated duty cycle. Only the effect of the dead time in M₃/M₄ pair of transistors in Buck+Boost mode is corrected. Consequently, the effect of the dead times of only one pair of transistors contributes to decrease the conversion ratio in all the operating modes and thus it does not impact the transition between modes.

Figure 14 and

Table 5. Definition of (d_buck[n],d_boost[n]) pairs.

Mode	Output
Buck	dbuck[n] = d[n] dboost[n] = 0
Buck+Boost (Trajectory B-C)	dbuck[n] = dbuck,B2 + d[n] − dbuck,max dboost[n] = dboost,min + dtboost
Buck+Boost (Trajectory C–D)	dbuck[n] = dbuck,max dboost[n] = dboost,min + d[n] − dbuck,max + dbuck,B2 + dtboost
Boost	dbuck[n] = 1 dboost[n] = d[n] − 1

show the final DPWM state machine including the hysteresis (h) and the correction of dead time (dt_boost) effect in M₃/M₄.

4. Results and Discussion

The operation of the 4SBB with the proposed modulator has been simulated using Simulink-MATLAB^® and the Simpower toolbox. The parameters presented in

Table 6. Specifications of 4SBB to obtain simulation and experimental results.

Input voltage:	v1 = 24 V
Output voltage:	v2 = 12–36 V
Maximum power:	Pmax = 500 W
Switching frequency:	fsw = 100 kHz
MOSFETs:	IRFB4310Z
Inductance value:	L = 8 µH
Output capacitance:	C2 = 470 µF
Maximum duty cycle:	dbuck,max = 0.90
Minimum duty cycle:	dboost,min = 0.10
Dead times:	dtboost = 0.01
Hysteresis:	h = 0.02

have been used both in simulation and during the experiments.

To validate the proposed approach the control variable d[n] is swept from 0.8 to 1.2. The signals d_buck[n] and d_boost[n] produced by the state machine are fed to two conventional DPWMs that generate the gate signals for M₁/M₂ and M₃/M₄.

Figure 15 shows the simulated output voltage obtained during the sweep for the approaches described in Section 2.1 as a reference. Note that the case where there are no limits for d_buck[n] and d_boost[n] produces an almost perfectly smooth transition as expected. The waveform corresponding to the bypass mode using d_buck,max = 0.90 and d_boost,min = 0.10, and the waveform corresponding to the mapping d_buck[n] = d_buck,max when d_buck,max < d[n] < 1 and d_boost[n] = d_boost,min when 1 < d[n] < 1 + d_boost,min are also shown.

Figure 16 shows the simulated output voltage for different implementations of the proposed method. The dashed waveform corresponds to the ideal implementation detailed in Table 1 and Table 2, without dead-time correction. The continuous waveform shows the ideal implementation with dead-time correction. Finally, the dashed and dotted waveform corresponds to the proposed simple DPWM (Table 3) using d_buck,B2, whereas the dotted uses d_buck,B.

A 4SBB prototype was used to experimentally test the proposed approach. An FPGA Virtex 4 SX35 from Xilinx [17] has been used to implement the control modulator of the prototype. Figure 17 shows a picture of the prototype.

As in the simulation results, a variable duty cycle is generated by the FPGA with the same values (d[n] from 0.8 to 1.2). This signal is used by the proposed modulator to generate the two duty cycles (d_buck[n],d_boost[n]). Finally, a DPWM modulator generates the complementary control signals of each MOSFET.

The different alternatives mentioned before were synthesized, yielding a resource usage shown in

Table 7. Resources used in the FPGA for the different modulators.

Modulator	Finite State Machine	D-Type Flip-Flop	Adder/Subtractor	Multiplier	Comparator
Ideal	1	73	5	2	5
Simplified	1	73	9	0	5

(prior to synthesizer optimization). As can be seen, the main difference is the required multipliers in the case of the ideal modulator as has been previously detailed.

Figure 18 shows the output voltage of the 4SBB using the presented implementations of the proposed control modulator. Figure 18a the ideal implementation presented in Table 2 is used. As can be seen the output voltage shows no discontinuities, achieving an almost perfect transition. Figure 18b shows the output voltage obtained using the proposed simplified method (Table 5); over imposed is the simulation result, showing good agreement. A slight step in the transitions can be appreciated. Figure 18c shows the output voltage using a narrower dead-zone (d_buck,max = 0.95 and d_boost,min = 0.05), where the discontinuity is almost non-existent, and the effects of the hysteresis are highlighted (also Table 5 is used).

Finally, the main operation waveforms in each operation mode are shown in Figure 19. As can be seen, the inductor current ripple in Buck+Boost mode is small as expected.

A qualitative analysis has been made, testing and comparing this implementation against some of the main referenced methods. The results are listed in

Table 8. Performance comparison.

Mode	Efficiency	Output Voltage Regulation	Computational Cost	Complexity	Scalability
Pass-through [10]	High	Low	Low	Low	High
One-mode modulation [13]	Low	High	Medium	Low	High
Duty-locking [7]	Medium	Medium	Medium	Medium	Medium
Hysteretic control [8]	Medium	Medium	Medium	Medium	Medium
Model-predictive control [9]	Medium	Medium	High	High	Low
This work	Medium	Medium	Low	Medium	High

. Apart from overall efficiency and output voltage regulation, other aspects that evaluate their universal applicability have been taken into account. They are computational cost, complexity of the implementation, and scalability.

From these results, it can be seen that [10] gives the highest efficiency and lowest complexity in general, but the output voltage is not regulated when input and output voltages are similar. Furthermore, [13] sacrifices efficiency for ease of implementation, while [7] and [8] constitute a good compromise between complexity and efficiency. It can be observed that [9] provides a similar result and uses a novel implementation, but its computational cost is way higher than the other options. Our work, on the other hand, while providing similar results, takes computational cost to a minimum and it is more scalable than the other options.

5. Conclusions

Four-switch Buck-Boost converters are widely used in many applications where voltage step up and down capabilities are required; however, near-unity conversion ratios are difficult to achieve due to limitations introduced by driver ICs.

In this work a simple digital pulse-width modulator for 4SBB converters that automatically produces adequate control signals to achieve full-range conversion ratios has been proposed. The modulator enables operation in Buck, Boost and Buck+Boost modes, ensuring high efficiency and guaranteeing relatively smooth transitions between the different modes. A light-resource hardware implementation, FPGA-based, composed of a simple state-machine and two conventional pulse-width modulators is proposed. This way, scalability and adaptability to the different applications is enabled. The proposed solution also addresses non-idealities such as dead-times or hysteresis; its feasibility has been demonstrated through simulations and experiments, achieving full-range conversion ratio and smooth transitions in a 500 W 4SBB converter with 24 V input and 12–36 V output voltage range. However, it should be noted that the proposed DPWM solution still has room for improvement, mainly in the minimization of the step that appears due to the simplification of the duty cycles, but also it would be interesting to study the performance in other aspects, such as increasing switching frequency operation or voltage ripple reduction.