A Thermally Stable Quasi-CMOS Bipolar Logic

Abstract

Logic gates made of pairs of NPN and PNP bipolar transistors, similar to CMOS logic gates, have been proposed and patented long ago but did not find any practical application until now. Other bipolar technologies (TTL, TTL-S, ECL), once the technologies of choice for digital systems, were abandoned and superseded by CMOS. In this paper it is shown that now, when truly complementary pairs of bipolar transistors can be made, properly biased bipolar gates similar to CMOS gates are feasible, can be thermally stable and find practical applications.

1. Introduction

Bipolar technologies such as TTL, TTL-S and ECL, once the technologies of choice for digital systems, were totally abandoned and superseded by CMOS. The reasons are well known: large area of vertical bipolar transistors in comparison with MOS devices, larger device count in bipolar logic gates and larger power consumption. These properties made the bipolar technologies mentioned above unsuitable for VLSI circuits. CMOS-like complementary bipolar logic gates similar to CMOS logic gates (Figure 1) were proposed long ago (1976, [1]) but never used. They will be called CBip in this paper. In traditional bipolar technologies, in which TTL or ECL gates were made, good NPN vertical bipolar transistors were available but PNP transistors had different physical structures and much worse parameters. They were not complementary to their NPN counterparts. Moreover, vertical transistors were strongly asymmetric, with heavily doped emitters, much lower doping in the collector and different areas of emitter-base and collector-base junctions. Such transistors have a relatively high voltage drop between the emitter and collector when switched “on” in a digital gate. As a result, both “0” and “1” voltage levels would be degraded (“0” voltage level higher than “0” and “1” voltage level lower than the supply voltage) if asymmetric transistors were used in a CMOS-like digital gate.

In 2011 a new structure of a lateral bipolar transistor on SOI, technologically compatible with PD-SOI (Partially Depleted Silicon on Insulator) CMOS circuits, has been demonstrated [2]. Such transistors are small and symmetric, complementary pairs of NPN and PNP devices can be made. Later in a series of papers [3,4,5,6,7] these transistors were investigated both theoretically and experimentally, including experimental characterization of inverters, SRAM cell flip-flops and ring oscillators. It was suggested that CMOS-like bipolar logic, i.e., logic gates made of complementary pairs of NPN and PNP transistors, could be useful both for very fast circuits and very low power circuits. Later another SOI-based technology, in which complementary pairs of symmetric NPN and PNP transistors as well as MOS devices can be made, has been demonstrated [8,9,10]. One more bipolar device concept-symmetric lateral doping-free bipolar transistor-has been proposed [11] and investigated [12,13]. In spite of these very promising works CMOS-like bipolar logic is still not used in digital integrated circuits.

There is a fundamental difference between CMOS logic gates and similar CBip logic gates: the input current. In MOS transistors the input (gate) current is equal to zero (except gate leakage that is negligible in state-of-the-art very small devices) while in bipolar transistors the input (base) current in the “on” state is not negligible. When the output of a CBip gate is connected to the input of another CBip gate, the current drawn by this input from the output of the previous gate (as shown in Figure 2) distorts the voltage transfer curve of the previous gate.

The input (base) currents in CBip gates depend exponentially on the input (base-emitter) voltages and rise exponentially with temperature. This thermal effect is highly undesirable and makes CBip-based logic circuits practically useless at elevated temperatures. In this paper a simple solution mitigating this effect is proposed in Section 2, and Appendix A gives its mathematical analysis. In Section 3 CBip gates performing NOT, NOR and NAND logic functions are simulated and their properties discussed in the context of the solution proposed in Section 2. Examples of CBip-based logic circuits are also shown. Section 4 discusses the results shown in previous sections and suggests possible applications of CBip circuits. Transistor models used in simulations are given in Appendix B. These models roughly correspond to the experimental characteristics of lateral symmetric NPN devices discussed in [2] (see Figure 9 in [2]). To simplify interpretation of the simulation results, in most cases it is assumed that the models of NPN and PNP devices are identical.

2. Thermal Stability of CBip Gates

Let us consider a CBip inverter biased, as in Figure 3. It is assumed that the voltage level of logic “1” equals the supply voltage V_CC.

Figure 4 shows a simulated DC transfer characteristic and input current vs. input voltage for V_CC = 1 V at 300 K. The transfer characteristic is excellent, but the input current is unacceptable—up to 0.7 mA.

If the supply voltage is reduced to 0.65 V, the transfer characteristic is still acceptable, and the input current is reduced to nanoamperes—see Figure 5.

However, reduction of the supply voltage does not solve the problem of the input current because this current strongly increases with temperature. Figure 6 shows the transfer characteristic and input current at 400 K. The input current increases from 3 to 600 nA.

To mitigate this thermal effect, a solution borrowed from an analog domain can be used. It is based on the observation that the collector current of a bipolar transistor operating in forward active mode (i.e., with V_CB ≤ 0 and V_BE > 0, where V_CB is the collector-base voltage and V_BE is the base-emitter voltage; positive voltage means forward bias and negative voltage—reverse bias of the respective transistor pn junctions) does not depend on the collector-base bias voltage (neglecting secondary effects). Therefore, if the same base-emitter voltage V_BE is applied to two identical transistors operating in the same temperature, their collector currents will be identical. This directly follows from the Ebers–Moll bipolar transistor model [14]. The expression for the collector current can be written as [14] (see Equation (17) in [14]).

$$I_C=I_{ES}\left(e^{\frac{q{V}_{BE}}{kT}}-1\right)-I_{CS}\left(e^{\frac{q{V}_{CB}}{kT}}-1\right)$$

(1)

where I_ES and I_CS are constants, and $kT/q$ is the thermal voltage (approx. 26 mV at room temperature). If V_CB ≤ 0, the second term can be neglected, and if V_BE >> $kT/q$ (in practice if V_BE is larger than 100~150 mV), (1) can be reduced to

$$I_C=I_{ES}{e}^{\frac{q{V}_{BE}}{kT}}$$

(2)

Expression (2) is widely used in analog bipolar circuit design.

Figure 7 shows the proposed solution. The supply voltage for the CBip inverter Q2–Q3 equals the base-emitter voltage of transistor Q1. This voltage also defines the logic level “1”. With “1” (i.e., V_supply) at the input of the inverter transistors, Q1 and Q2 make the current mirror. If both are identical and their temperatures are identical, both collector currents are the same (neglecting base currents). If the collector current of Q1 (determined by the V_CC voltage and resistance R) will not depend on temperature, the collector current of Q2 also will not depend on temperature. The input current of the inverter will be h_FE—times lower, where h_FE is the DC current gain factor, i.e., the ratio of the collector DC current to the base DC current. The input current of the inverter will depend somewhat on temperature because h_FE is temperature dependent, but this dependence is weak, not exponential. Moreover, in the configuration shown in Figure 7 the collector current of Q1 will not be absolutely constant. The current flowing across the resistor R will be equal to $\left(V_{CC}-V_{BE}\right)/R$, and, since V_BE will decrease with temperature, the current flowing across the resistor R and the collector current of Q1 will increase. In practical integrated circuits thermal dependence of the collector current of Q1 can be minimized because resistance of resistors in integrated circuits increases with temperature. Appendix A discusses this issue quantitatively. However, in this paper resistance R is constant in all simulations.

It is worth noting that Q1 and Q2 need not be identical. If they are not, the collector current of Q2 will be proportional to the collector current of Q1. If the collector current of Q1 does not depend on temperature, the collector current of Q2 will not depend on it either.

If the logic level at the input of the inverter is “0”, the current mirror is composed of transistors Q1 and Q3—see Figure 8. The base-emitter voltages of Q1 and Q3 are identical. In the general case Q1 (an NPN device) and Q3 (a PNP device) will not be identical, but since the collector current of Q1 is temperature-independent, thermal stability of the inverter will be maintained. To demonstrate this, the simulations shown in Figure 9 and Figure 10 were carried out with an NPN model different from the PNP model—see Appendix B. The input current characteristics are no longer symmetric but the input current at 400 K is almost the same as at 300 K.

The thermal stabilization idea shown in Figure 7 and Figure 8 can be extended to logic blocks with any number of CBip inverters and other gates, as shown in Figure 11. By varying R, one can vary the sum of all currents consumed by the logic gates in this block, i.e., the overall current consumption. Of course, thermal stabilization of the whole block requires the same temperature of Q1 and all the transistors in the logic block.

Note that an increase in the temperature from 300 to 400 K results in reduction of the supply voltage, which is also the “1” voltage level, from 650 to 465 mV (Figure 9 and Figure 10). This is not a problem in a digital circuit if the supply voltage and the “1” voltage level are the same for all CBip gates in the circuit, as in Figure 11. Examples are shown in the next section.

3. CBip Gates and Circuits

3.1. NAND and NOR Gates

The schematic diagrams of NAND and NOR gates are shown in Figure 12.

Figure 13 shows the simulated transfer characteristics of the NAND and NOR gates. Characteristics (b) and (c) are similar to the characteristics of CMOS gates. Characteristic (a) is different, somewhat similar to the transfer characteristics of the logic gates in the old NMOS technology with NMOS enhancement mode transistors as active devices and an NMOS depletion mode transistor as pull-up device. Although the (a) characteristics are not as good as (b) and (c) characteristics, the NAND and NOR gates work correctly in logic circuits, as will be demonstrated in Section 3.

3.2. AND and OR Gates

By adding inverters at outputs of NAND and NOR gates we obtain AND and OR gates (Figure 14).

Figure 15 shows simulated transfer characteristics of these gates.

3.3. The Effects of Load

All transfer characteristics shown above (Figure 4, Figure 5, Figure 6, Figure 9, Figure 10, Figure 13 and Figure 15) were obtained for gates without any load connected to their outputs. Figure 16 shows inverters with resistive load (a) and load in the form of input of another inverter (b).

The maximum current that can be drawn from output of any gate will never exceed the current supplied from V_CC: $I_{max}=\left(V_{CC}-V_{BE}\right)/R$. In practice, this means that the load resistance R_L must be much larger than R. However, even resistive load that meets this requirement will shift the transfer characteristics of the gate. This is shown in Figure 17a.

If the output of a CBip gate is connected to the input of another CBip gate, as in Figure 16b, the transfer characteristic of the first gate is strongly distorted, as shown in Figure 17b. However, the transfer characteristic from the input to the output of the second gate is correct. In the next subsection it is demonstrated that logic blocks with CBip gates work correctly despite distortion shown in Figure 17b.

3.4. Two Examples

The first example demonstrates the operation of a simple logic block (C17 ISCAS benchmark) implemented with CBip gates. The logic diagram of C17 benchmark is shown in Figure 18. The block is thermally stabilized in the way shown in Figure 11.

The input and output signals are shown in Figure 19. For comparison, operation of the same block implemented with 22 nm CMOS gates is shown. The logical response of the CBip-based block does not differ from response of the CMOS-based block

It has been demonstrated [4,6] that the delay of a CBip inverter can be varied by many orders of magnitude by varying its supply voltage. The performance of CBip-based thermally stabilized digital circuits can be adjusted by the voltage V_CC and/or resistance R. The second example demonstrates this feature by replacing resistor R with a NMOS transistor, whose gate voltage is controlled by a voltage source V_REG (Figure 20). By varying this voltage, the supply voltage and the frequency of oscillation of the ring oscillator are varied.

Figure 21 shows that the CBip ring oscillator can be used as a voltage-controlled oscillator. The shortest oscillation period at V_REG = 1.5 V equals 0.28 ns; the longest period at V_REG = 0.95 V is approximately 125 ns. This simulation demonstrates the flexibility of CBip-based logic circuits: the same circuit can be used either as a high-performance circuit or as a low-power circuit by changing the V_CC voltage and/or the resistance R (Figure 7 and Figure 8). If the resistance R is replaced by an active voltage-controlled device, as in Figure 20, the performance and power consumption can be easily controlled in a working circuit and adjusted as needed for a given task.

For comparison, Figure 22 shows the same CBip ring oscillator simulated at temperature 400 K. The I_DD current is larger and oscillator periods are shorter. The shortest oscillation period at V_REG = 1.5 V equals 0.19 ns; the longest period at V_REG = 0.95 V is approximately 5 ns only. This simulation result is also affected by temperature dependence of the parameters of the MOS transistor M and capacitances of bipolar devices.

4. Discussion and Conclusions

The purpose of this paper is to show that CBip gates thermally stabilized as shown in Figure 7 and Figure 8 can be used to build fully functional digital circuits working well in a broad range of temperatures. A unique feature of CBip-based digital circuits is that the same circuit can be used either as an ultra-low power circuit or as a high-performance circuit, and power vs. performance tradeoff can be easily controlled in a working circuit.

But the question is: who needs CBip gates?

It is rather obvious that CBip-based digital circuits will not replace the most advanced FinFet or Nanosheet-based CMOS circuits. However, they can become a valuable addition to more traditional CMOS circuits. The symmetric lateral bipolar transistors on PD-SOI substrates [2,3,4,5,6,7] and CBip gates using them could be used as additional components of PD-SOI CMOS circuits, for example in I/O buffers, or even as either high-performance or ultra-low power digital blocks, as suggested in [5,6,7]. The doping-free symmetric lateral bipolar transistors [11,12,13] could be added to FD-SOI (Fully Depleted Silicon on Insulator) CMOS circuits, where the channel area of MOS devices is not intentionally doped. Unfortunately, manufacturers do not offer symmetrical lateral bipolar transistors in their PD-SOI or FD-SOI technologies yet. Therefore, the simulations described in the paper cannot be directly compared with experiments. However, the transistor models used in the simulations roughly correspond to the experimental characteristics of NPN devices discussed in [2] (Figure 9).

It is worth noting that bipolar transistors are very useful in analog circuits. In mixed-signal circuits the symmetric lateral bipolar transistors could be used, e.g., in low-noise amplifiers as well as in RF amplifiers. This topic is, however, beyond the scope of this paper.