Next Article in Journal
The Use of Excess Electric Charge for Highly Sensitive Protein Detection: Proof of Concept
Next Article in Special Issue
A Unified FPGA Realization for Fractional-Order Integrator and Differentiator
Previous Article in Journal
A Low-Power ADPLL with Calibration-Free RO-Based Injection-Locking TDC for BLE Applications
Previous Article in Special Issue
Antimonotonicity, Hysteresis and Coexisting Attractors in a Shinriki Circuit with a Physical Memristor as a Nonlinear Resistor
 
 
Article
Peer-Review Record

A 1-to-3 GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28 nm CMOS

Electronics 2022, 11(13), 1954; https://doi.org/10.3390/electronics11131954
by Binghui Wang 1,2, Haigang Yang 3,* and Yiping Jia 4
Reviewer 1:
Reviewer 2: Anonymous
Electronics 2022, 11(13), 1954; https://doi.org/10.3390/electronics11131954
Submission received: 22 May 2022 / Revised: 16 June 2022 / Accepted: 19 June 2022 / Published: 22 June 2022
(This article belongs to the Special Issue Design and Applications of Nonlinear Circuits and Systems)

Round 1

Reviewer 1 Report


Comments for author File: Comments.pdf

Author Response

Thanks, we very much appreciate the reviewer’s supporting comments.

Author Response File: Author Response.pdf

Reviewer 2 Report

An adaptive fast-locking self-biased phase locked loop is designed using 28 nm CMOS process. The tuning range is from 1-3 GHz, which makes it suitable for microwave applications. The novelty lies in suggesting an adaptive fast-locking current circuit to make the PLL parameters achieve independency from the operating frequency and frequency division ratio. Comparative studies with the recent literature clearly demonstrate the benefits of the proposed circuit topology. Authors may consider the following suggestions to further improve the work.

1. It is claimed in the Abstract that the PLL has been fabricated. However, the paper does not provide supporting evidence and results of the actual fabricated PLL; rather, only the simulation results are shown. Authors are encouraged to include the photograph of the fabricated chip, and show detailed comparisons of the experimental measurement results with those of the simulated ones.

2. The Introduction is too short and abruptly ends without emphasizing the novelty and contributions of the work in detail.

3. Discussion on Fig. 1 needs significant improvement. For instance, what is PFD, CP1, CP2? What is the expected output from O1 and O2? Divder should be Divider. Better to use f instead of F when referring to frequency, as in f_REF instead of F_REF. AFFCC should be AFLCC.

4. Maintain consistency in the names of the voltages/currents used in the text and the figures. For example, check Fig. 3 where it is Ilock versus I_{lock} in text.

5. Table 1 should have Meas/Sim instead of Meas.Sim. Discussions on Table 1 are completely missing.

6. Mention the limitations of the work in the Conclusions.

Author Response

Thanks, we very much appreciate the reviewer’s supporting comments.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Thanks to the authors for addressing my comments. I have no further suggestions, except one minor one: A space should exist between "Figure" and its number. For e.g., Fig. 1 instead of Fig.1. Otherwise, the paper can be accepted. 

Back to TopTop