Coplanar Asymmetry Transformer Distributed Modeling for X-Band Drive Power Amplifier Design on GaN Process

Abstract

In this paper, a methodology for designing a distributed model for coplanar asymmetry transformer on gallium nitride (GaN) process is proposed, which can accurately characterize the transformer’s feature up to a millimeter-wave band. The paper analyses a transformer-based matching circuit and proposes a practical transformer design procedure. A two stage, transformer matching based X-band power amplifier (PA) is reported here. Using the proposed transformer model and correlated transformer design procedure can sharply reduce schematic design period and optimum process time. The PA chip is designed on a 0.25 µm GaN technology process and occupies a 1.515 mm² area. At a 28 V supply, the gain and output power of the PA reaches 15 dB and 29 dBm respectively, and the wideband matching transformer reaches 47.6% bandwidth. To the best of our knowledge, the distributed model for coplanar asymmetry transformer and transformer-based X-band MMIC PA on GaN process in this work is the first case among the reported papers.

1. Introduction

In recent years, the transformer has been widely used in Radio Frequency (RF)/mm Wave circuit design [1,2,3,4,5,6], such as the Voltage Control Oscillator (VCO) [7], frequency multiplier, mixer, low noise amplifier (LNA) [8], and PA [9,10,11]. Essentially, the on-chip transformer is a high-order LC network that composes prime/secondary winding and parasite capacitance. Its easy-to-deploy layout enables designers to have a high degree of design freedom, and far more adjustable parameters [12], which are favorable to wideband PA design. The transformer has the capability of low-loss AC coupling, impedance matching/transformation, and power combining [6,13]. Especially, transformer matching can absorb device output capacitance into the matching network and is widely used as broadband CMOS PA design [14,15,16]. Instead of CMOS process, on-chip transformer is also be integrated on SiGe [9], GaAs [11], and BiCMOS [17,18] process chips.

Electronic Design Automation (EDA) platform Electromagnetic (EM) simulation tools provided us with a way to build transformer model, thus the designer had a higher degree of freedom for designing on-chip transformers, and no longer relayed on the foundry provided model. Generally, there are two kinds of modeling methods for on-chip transformers: lumped element modeling [10], and distributed modeling [19,20]. The lumped element modeling method explores transformer inherent parasitic and loss mechanism, using the lumped element to build the transformer model; the famous symmetric 2π-model [10] is the most representative one. However, lumped element modeling heavily relies on simulation results and embodies numerous parameters that need to be determined, which makes the modeling process so complex, and the distributed modeling method views the transformer as the coupling transmission line. Thus, to be able to obtain the complete characteristic of the transformer, it has been widely studied in recent years. In this work, we also use the distributed modeling method and an accurate distributed model for a coplane asymmetrical transformer on GaN process is built.

Based on the CMOS process, several sets of research for on-chip transformer designing have been proposed, such as Inductively Coupled Resonators (ICR) design flow [21], transformer-based matching networks (TMN) synthesizing method [22], magnetically coupled resonator (MCR) design method [12], and coupled line based electric (capacitive) couplings [19]. In this work we also provide a simplified transformer design procedure for GaN process.

However, previous research has rarely concerned transformer performance on MMIC design and lacks corresponding modeling, designing methodology. The normal method to model on-chip transformers in Radio Frequency (RF) is the use of S-parameters, obtained from ElectroMagnetic (EM) simulation. The drawback of such an approach is that EM simulation can be time-consuming and the simulated S-parameters may cause a divergence problem in the transient simulation of the circuits [10]. Moreover, the distributed modeling [10,17,19,20] method for coplanar asymmetry transformer has not been studied yet. The asymmetric coupling structure means it cannot be analyzed through the traditional even–odd mode method [23], and wideband design requirements worsen the case. Additionally, because of wavelength and device scale, transformer matching has rarely been used in microwave frequency band RF circuits. Therefore, the urgency for developing a new model for asymmetry coplanar transformer within microwave band and corresponding design method on MMIC cannot be ignored.

This paper proposes a distributed model for an asymmetric coplanar transformer at microwave band and discusses the transformer impedance matching mechanism for PA design. All the design methods and experiment results are carried out on MMIC GaN technology process. The paper is organized as follows: Section 2 discusses transformer design process parameters and the influence on the transformer performance. Section 3 describes the proposed modeling method for asymmetric coplanar transformer and equivalent distributed model. The transformer design procedure and port impedance characteristics are illustrated in Section 4. In Section 5, a two-stage transformer matching power amplifier design on 0.25 µm GaN process is presented. By using the proposed analytical method and the transformer model, the designed PA achieves ideal performance. The conclusion is set in the last part, Section 6.

2. Transformer Design Process Comparison

The IC technology process decides a fabricated inductor or transformer’s performance. The transformer-related technology process parameters include top metal layer thickness, metal conductance, minimum metal space, the metal layers’ distance towards the substrate, substrate dielectric constant, and so on. Because of the parasitics and different loss mechanisms, the impedance transformation ratio is highly frequency and size-dependent and deviates from its ideal value of 1, even for a 1:1 transformer [10]. Although some of the parameters are predefined in the technology process, it provides us with a reference for transformer design.

2.1. Process Parameters’ Influence to On-Chip Transformer

Table 1. Technology process parameter comparison for transformer design.

Technology Process	TSMC 0.13 µm RF CMOS	TSMC 0.18 µm RF CMOS	TSMC 0.25 µm RF CMOS	0.15 µm InGaAs pHEMT	0.25 µm GaN on Sic
Number of metal layers	8	6	5	2	2
Min. metal layer space (Top thick metal) (µm)	-	1.5	-	4 (MET2 scale > 50 µm)	6
Top layer Metal thickness (µm)	3.3	2.34	0.99	2	4
Top metal to substrate distance (µm)	7.470	8.15	7.47	5.2	1.62
Top metal conductance (S/m)	5.816 × 107	2.464 × 107	2.464 × 107	4.1 × 107	4.1 × 107
Substrate dielectric constant	11.9	11.9	11.9	12.9	9.7

All the data, collected from PDK, only serves for research use.

lists major RF technology process parameters comparisons. The advanced smaller feature size CMOS process has more metal layers and thicker top metal, and the top metal conductance significantly improves to 5.816 × 10⁷ S/m in the TSMC 0.13 µm CMOS process. From TSMC 0.25 µm to 0.13 µm CMOS process, the metal layers are added from 5 to 8. While III-V compound processes like GaAs and GaN listed in this Table have two metal layers, and comparatively larger metal conductance and layer space, in 0.25 µm GaN process, top metal thickness reaches 4 µm, which is the thickest among the listed processes. Using the thicker metal layer to design an on-chip transformer can effectively increase coupling coefficient and reduce the loss, and it also helps to enlarge transformer self-resonate frequency (f_srf), which is of great use in practical design.

Thus, compared to CMOS technology, GaN process has a thicker top metal layer and larger metal conductance, but its metal layers are closer to the substrate, which will suffer more substrate loss. The comparatively larger minimum metal layer space on the GaN process, 6 µm for MET2 layer, will constrain the designed coplanar transformer coupling coefficient to some extent.

2.2. Transformer Design on GaN Process

Figure 1a reveals the simplified 0.25 µm-GaN technology process cross-section view. Metal layers, MET1 and MET2, have the same conductance but different thickness. MET2 is 4 µm thick, and 1.622 µm away from SiC subtract, while MET1 is only 1.1 µm thick and 0.252 µm to the subtract. The substrate and floating shields take up 100 µm thickness. Both MET1 and MET2 layers can be used for designing the passive element on MMIC. However, MET2 is much thicker and further to the substrate, which makes it more favorable. In Figure 1c, a vertical design on this process is shown that uses the MET1 and MET2 vertical structure to form a coupling structure. Due to the narrow space between the two metal layers—0.272 µm for this GaN process as we can see in Figure 1a—the practical vertical transformer has larger coupling coefficient and parasite capacitance and these parameters are hardly adjustable, which greatly restricts practical transformer design freedom on 0.25 µm-GaN process. In Figure 1d, an octagonal coplanar transformer designed on MET2 is shown, and MET1 is used for cross-layer interconnection. w1/w2 represent primary/secondary winding metal line width, or trace width, d represents transformer inner diameter and s represents space between the primary and secondary winding. Notice that the trace width, w1/w2, for primary and secondary winding is asymmetric. This asymmetric physical structure makes coupling effect analyzing become much more complex, and different trace width at primary/secondary winding can be used for adjusting equivalent inductance. Ports 3/6 are central-tap, normally used for device biasing. Figure 1b shows the proposed distributed model for the coplanar transformer that is based on asymmetric parallel coupling transmission line models, CLA and CLB. Ports numbers in Figure 1b,d are equivalent. Several experiment results are shown in the following passages, to reveal the transformer’s performance on GaN process.

2.2.1. Vertical and Coplanar Transformer’s Feature on GaN Process

In Figure 1c, the transformer has a vertical coupling structure. MET1 and MET2 are drawn in the same shape. In this case, MET2 is for transformer primary winding and MET1 is for the secondary. The vertical transformer has higher coupling coefficient, larger equivalent capacitance, and lower f_srf, while the coplanar transformer is opposite. An experiment was set to illustrate this trend.

In this experiment, both the vertical and coplane transformers had 140 µm inner diameter, 10µm trace width, and the same physical scale of secondary winding. Figure 2 shows the secondary winding equivalent inductance of the two transformers. Obviously, the curves trend shows that the two inductors almost had the same inductance value at low frequency band. As the frequency went high, due to the stronger coupling effect and larger parasite capacitance, the vertical transformer’s inductor quickly met its f_srf. While the coplane transformer’s f_srf was much higher, the vertical transformer’s f_srf was 18.16 GHz, while the coplanar transformer’s f_srf was 51.98 GHz. Additionally, at 10 GHz frequency point, the coupling coefficient was 0.829 for vertical transformer and 0.521 for coplanar transformer. In Figure 2, the blue line shows a sharp inductance value variation trend near the f_srf at a low frequency band that would cause the designed transformer matching network to hardly have stable port impedance within the wide frequency band, which is unacceptable in this work. Generally, the transformer’s f_srf should be at least three times higher than the signal frequency high band. The vertical transformer’s low f_srf makes it an unideal choice.

2.2.2. Coplanar Transformer’s Inductance vs. Trace Width

Figure 3 provides transformer parameter correlated influence among w, L, f_srf. The experiment results are obtained from d = 70 µm, MET2 on-chip octagonal inductor EM simulation. As the Figure shows, the equivalent inductance and f_srf constantly reduce as the winding metal trace goes wider. As trace width increases from 6 to 18 µm, the inductance reduces from 0.315 nH to 0.266 nH, while the f_srf also reduces from 82.05 to 72.83 GHz. This illustrates that winding trace width is correlated with winding equivalent inductance, which means that by changing trace width at primary/secondary winding, we can broaden the transformer matching range.

2.2.3. w vs. s vs. k for Coplanar Transformer

The coupling factor is mainly decided by transformer trace space s, between the primary and secondary winding. The top metal, MET2 with 4 µm thickness, is used to design octagonal coplanar transformer. In 0.25 µm GaN process DRC rules, the MET2 minimum layer space is 6 µm, which constrains the designed transformer available coupling coefficient. As Figure 4 shows, with wider trace space s and metal line width, trace width w, the transformer coupling coefficient k dramatically decreased. Another trend is that, at a constant trace space s, the coupling coefficient slightly increases with trace width. In the majority of cases, the space s is set as narrow as possible for larger transformer coupling coefficient.

Based on the experiment results above, we may safely come to the conclusion that designing a transformer on GaN process is entirely possible. Both vertical and coplanar transformers are possible to be designed on GaN process, but vertical transformers have unacceptable lower f_srf, vertical transformer bottom winding is too close to the subtract in MMIC process and will incur much more loss. A vertical transformer using a thin bottom metal layer will lower f_srf. Thus, coplanar transformer design on top thick metal is a more ideal choice for transformer designing on GaN.

3. Transformer Design and Modeling

Previous research has little concern about asymmetry coplanar transformer distributed modeling, as well as transformer design method on GaN MMIC. In practice, coplanar transformer trace widths at the primary and secondary sides are unequal, and coplanar transformer secondary inductor’s diameter is larger than the primary one. This complex asymmetry coupling structure cannot be analyzed through classical even–odd theory. Thus, a new model is proposed to solve this problem.

3.1. Asymmetry Coupling Transmission Line Theory

In this work, a coplanar asymmetry transformer with a central-tap distributed model is shown in Figure 1c, and we use an asymmetry coupling transmission line to model coupling effect between transformer primary and secondary winding (CLA and CLB in Figure 1c). The parallel asymmetric coupled line is modeled by normal mode (c and π mode) parameters [23]. For accuracy, mutual capacitance and parasite inductance are also added. According to previous research [24], the mutual capacities between the central tape and portended are crucial, so capacitance C₁ and C₂ are added in the model.

The method to grasp all the parameters needed to define c-π mode asymmetry coupling transmission line is listed as follows [23]:

• Obtain the S matrix of the asymmetry coupling transmission line under specific length and the frequency through EM simulation. For this transmission line coupling, the pair has four ports and the corresponding S-parameter matrix’s dimension must be 4 × 4.
• Then, transform the grasped S matrix into an ABCD matrix. Then all the parameters can be calculated through the following equations (note that A,B,C,D are 2 × 2 matrices and their elements are inherited from the transformer matrix in step 1).

  $$A=M_V\left[\begin{array}{cc}\cos \mathrm{h}({\gamma }_{c}l)& 0\\ 0& \cosh ({\gamma }_{\pi }l)\end{array}\right]M_V^{-1}$$

  (1)

  $$B=\left(\left[\begin{array}{cc}\frac{1}{Y_{C1}}& \frac{1}{Y_{\pi 1}}\\ \frac{1}{Y_{C2}}& \frac{1}{Y_{\pi 2}}\end{array}\right]*M_I\right)\times \left[\begin{array}{cc}\sin \mathrm{h}({\gamma }_{c}l)& 0\\ 0& \sinh ({\gamma }_{\pi }l)\end{array}\right]M_I{}^{-1}$$

  (2)

  $$C=\left(\left[\begin{array}{cc}{Y}_{C1}& Y_{\pi 1}\\ Y_{C2}& Y_{\pi 2}\end{array}\right]\ast M_V\right)\times \left[\begin{array}{cc}\sin \mathrm{h}({\gamma }_{c}l)& 0\\ 0& \sinh ({\gamma }_{\pi }l)\end{array}\right]M_V^{-1}$$

  (3)

  $$D=M_I\left[\begin{array}{cc}\cosh ({\gamma }_{c}l)& 0\\ 0& \cosh ({\gamma }_{\pi }l)\end{array}\right]M_I^{-1}$$

  (4)

  $$M_V={\left(M_I^T\right)}^{-1}=\left[\begin{array}{cc}1& 1\\ R_{\mathrm{c}}& R_{\pi }\end{array}\right]$$

  (5)
• The eigenvalue decomposition on matrices A and D is applied to find the values of ${\gamma }_{\mathrm{c}}={\alpha }_c+\mathrm{j}*{\beta }_c$. ${\gamma }_{\pi }={\alpha }_{\pi }+\mathrm{j}*{\beta }_{\pi }$, $R_{\mathrm{c}}$ and $R_{\pi }$, $Z_{\mathrm{c}1}$, $Z_{\mathrm{c}2}$, $Z_{\pi 1}$ and $Z_{\pi 2}$ can be found either by comparing the elements or by matrix operations on matrices B and C.

3.2. Asymmetric Coupling Transmission Line Simulation Model

The normal mode theory calculated every parameter needed for feature coupling line, but that result was incompatible with the EDA simulation platform. In the literature [23], the asymmetry coupling line model is proposed. That model consists of a four port transmission line element and several sets of transformers, which can be applied to both frequency domain and time domain simulation. Two sets of transformers, with the turn ration R_c/π and T_c/π are inserted into the model, are able to convert complex impedance between ports. The transmission line simulation model is shown as follows:

In Figure 5, TLINP4 is a four port transmission line simulation element packaged on the EDA platform. Z_π/c represents characteristic impedance, and Z_π/cmag represents characteristic impedance’s mode. T_π/c represents phase information when signal transmits in the model. The transformer with turning ratio T_π/c provides a way to convert real impedance into a complex form. The correlated parameters can be deducted from the following equations:

$$Z_{\pi }=\frac{1-R_{\pi }/R_c}{Y_{\pi 1}}=Z_{\pi }^{mag}{(l_{\pi }+j{k}_{\pi })}^2$$

(6)

$$T_{\pi }=l_{\pi }+j{k}_{\pi }$$

(7)

$${\epsilon }_{\mathrm{r}\pi }={\left(\frac{c}{2\pi f}{\beta }_{\pi }\right)}^2$$

(8)

$${\gamma }_{\pi }={\alpha }_{\pi }+\mathrm{j}{\beta }_{\pi }$$

(9)

In Equations (6) and (7), Z_π^mag, l_π, k_π are real numbers. In Equation (8), ${\epsilon }_{\mathrm{r}\pi }$ represents relative dielectric constant in π mode, c represents speed of light, ${\beta }_{\pi }$ represents wave number in π mode. In Equation (9), ${\gamma }_{\pi }$ is propagation constant. Similarly, the parameters needed to built mode-C can also be calculated through the this process.

The model is set up on 0.25 µm GaN technology process. We set a parallel asymmetry coupling line on the MET2 layer, with 10 µm and 14 µm wideness respectively, 326 µm length, and 6µm trace space. Transmission line parameters were obtained from f = 10 GHz EM simulation. The calculated model parameters are listed in

Table 2. The calculated parameters of asymmetry coupling transmission line model.

Parameter	Value	Parameter	Value
${\epsilon }_{\mathrm{r}c}$	3.9599	$Z_{\mathrm{c}}^{\mathrm{mag}}$	81.0430
${\epsilon }_{\mathrm{r}\pi }$	5.6313	$Z_{\pi }^{\mathrm{mag}}$	416.2361
$R_C$	−0.7836 + j × 0.0032	$T_{\mathrm{c}}$	0.9998 − j × 0.0215
$R_{\pi }$	1.0194 + j × 0.0011	$T_{\pi }$	1 − j × 0.0015

. Testing simulation results are shown in Figure 6. Obviously, the model performance fits simulation results with high accuracy.

3.3. Transformer Modeling Process

The distributed model modeling a transformer as a transmission line [18]. The proposed coplanar on-chip transformer distributed model is shown in Figure 1c. The central tap, port 3/6 are included in this model. The mutual coupling capacitance C₁, C₂, are important in single turn transformer [25], and inductance L1, L2 are added for modeling asymmetry coupling effect between primary and secondary inductance. The transformer’s Y-parameter matrix is listed in (10).

Each element in the matrix Y* is based on asymmetry coupling transmission line theory, Y_ij is the element we get from the transmission line model. The matrix Y* is symmetric matrix. The central tap provides DC biasing path because it behaves as an AC ground in differential mode [26], and based on experience, the central tap has little impact on the entire transformer performance. Thus, the central-tap-related Y-parameters, Y_ij, are omitted in this calculation. The proposed transformer model equivalent Y matrix is represented as follows:

$$Y^{*}=\left[\begin{array}{ccccc}{Y}_{11}^{*}& Y_{12}^{*}& & \cdots & Y_{16}^{*}\\ Y_{21}^{*}& Y_{22}^{*}& & & \\ ⋮& ⋮& & \ddots & ⋮\\ Y_{61}^{*}& Y_{62}^{*}& & \cdots & Y_{66}^{*}\end{array}\right]$$

(10)

This major conductance element Y_ij^* in matrix Y^* is listed as follows.

$$Y_{11}{}^{*}=Y_{22}{}^{*}=\frac{1}{j\omega ·L_1+[j\omega ·L_2|\left|{(j\omega ·C_1)}^{-1}\right||{\left(Y_{11}\right)}^{-1}]}$$

(11)

$$Y_{44}^{*}=Y_{55}^{*}\approx Y_{44}+\mathrm{j}\omega ·C_2+Y_{14}$$

(12)

$$Y_{52}^{}{}^{*}=Y_{41}^{}{}^{*}\approx Y_{41}·\frac{[{(j\omega ·C_1)}^{-1}||j\omega ·L_2||{(Y_{11})}^{-1}]}{j\omega ·L_1+[{(j\omega ·C_1)}^{-1}||j\omega ·L_2||{(Y_{11})}^{-1}]}$$

(13)

$$Y_{25}^{}{}^{*}=Y_{14}^{}{}^{*}=Y_{14}·\left\{\frac{1}{1+j\omega ·L_1[j\omega ·C_1|\left|Y_{11}\right||{(j\omega ·L_2)}^{-1}]}\right\}$$

(14)

$$Y_{15}^{*}=Y_{51}^{*}=Y_{24}^{*}=Y_{42}^{*}=0$$

(15)

$$Y_{66}{}^{*}=\frac{2}{Y_{22}{}^{-1}\left|\right|[{(\mathrm{j}\omega ·C_1)}^{-1}+{(Y_{11})}^{-1}||j\omega ·(L_1\left|\right|L_2)]}$$

(16)

$$Y_{33}^{*}=\frac{2}{{(\mathrm{j}\omega ·C_2)}^{-1}\left|\right|\{[\mathrm{j}\omega ·L_2\left|\right|{(Y_{13})}^{-1}]+[{(j\omega ·C_1)}^{-1}\left|\right|(j\omega ·L_1)]\}}$$

(17)

3.4. Comparison between the Proposed Model and Transformer Electromagnetic Simulation Results

The comparison of the S-parameters from the EM simulation and the equivalent model is shown in Figure 7a. In this case, a single-turn, coplanar asymmetry transformer is modeled with 206 µm inner diameter, 10 µm trace width at primary winding, 14 µm for the secondary side, and 6 µm trace space. The transformer is designed on MET2 layer for better performance. InFigure 7, S parameters and corresponding impedance at major ports are drown.

A slight modeling error appears at the secondary winding port, S₄₄, in Figure 7b, which may be caused by oversimplified asymmetry coupling effect at the secondary winding. Above all, a six ports device coplanar asymmetry transformer is modeled properly. Up to a millimeter wave band, the model properly fits the transformer’s feature, and all the modeled curves present the same tendency with simulation results.

4. Transformer Based Matching Mechanism

4.1. Proposed Distributed Transformer Output Network Design

With the proposed distributed transformer model in Section 3, a differential to the single-ended transformer is used at the PA output matching part. As Figure 8 shows, differential input signal at port 4/5 is converted into a single-ended load at port 1, and power combine is achieved. The transformer also converts the device’s optimum impedance at port 4/5 into the 50 ohm at port 1. Elements C_mp and C_ms represent the capacitance in the matching network which helps to adjust matching impedance.

$$Y_{41}^{*}·V_1+(Y_{44}^{*}+\mathrm{j}\omega ·C_{ms})V_4+Y_{45}^{*}·V_5=I_4$$

(18)

$$Y_{51}^{*}·V_1+Y_{54}^{*}·V_4+(Y_{55}^{*}+\mathrm{j}\omega ·C_{ms})·V_5=I_5$$

(19)

$$\left(Y_{11}^{*}+\mathrm{j}\omega ·C_{mp}\right)·V_1+Y_{14}^{*}·V_4+Y_{15}^{*}·V_5=I_1$$

(20)

The transformer can be represented via its Y parameter, Y_ij* is the element deducted from the transformer model. The following equations can be deducted via the transformer Y parameter matrix.

Port 1 is connected to the load and port 4/5 are differential input ports. There exists relations: I₄ = −I₅ = I_dev, V₄= −V₅ = V_dev, and I_L= −Y_L × V_L. The deducted transformer current and voltage relationship across the ports can be represented via Y−parameter matrix.

$$\left[\begin{array}{c}{I}_{\mathrm{dev}}\\ I_L\end{array}\right]=\left[\begin{array}{cc}{Y}_{44}^{*}-Y_{45}^{*}+\mathrm{j}\omega ·C_{ms}& Y_{41}^{*}\\ Y_{14}^{*}-Y_{15}^{*}& Y_{11}^{*}+\mathrm{j}\omega ·C_{mp}\end{array}\right]·\left[\begin{array}{c}{V}_{dev}\\ V_L\end{array}\right]$$

(21)

The input impedance Z_in can be deduced from port 4/5, and Z_in is targeted to match device optimum load impedance.

$$Z\mathrm{in}=\frac{1}{{\mathrm{Y}}_{\mathrm{in}}}=\frac{V_{\mathrm{dev}}}{I_{dev}}=\frac{Y_L+Y_{11}^{*}+C_{mp}}{Y_{41}^{*}(Y_{15}^{*}-Y_{14}^{*})+(Y_{44}^{*}-Y_{45}^{*}+\mathrm{j}\omega ·C_{ms})(Y_L+Y_{11}^{*}+\mathrm{j}\omega ·C_{mp})}$$

(22)

4.2. Proposed Distributed Transformer Model for Input Network Design

The proposed distributed transformer model for input matching network analysis is shown in Figure 9. Transformer power distribution and wideband matching is mainly used for input matching circuit. Unlike power distributors, this transformer outputs a differential signal at Port 4/5. Capacitance C_mp and C_ms are loaded for matching impedance accuracy.

As Figure 9 shows, the single ended port 1 is designed to match the optimum input impedance, and port 4/5 to match optimum device impedance. Capacitance C_ms sums up device impedance equivalent capacitance and the matching network capacitance. Ports 4/5 connect to the load, for they output differential signal, there exists relation, V₄ = −V₅ = V_L, I₄ = −I₅ = I_L and I_L = −Y_L × V_L. Then the transformer based matching circuit cross ports voltage/current relationship and input impedance are calculated in Equations (23) and (24), respectively.

$$\left[\begin{array}{c}{I}_{\mathrm{dev}}\\ I_L\end{array}\right]=\left[\begin{array}{cc}{Y}_{11}^{*}+\mathrm{j}\omega ·C_{mp}& Y_{14}^{*}-Y_{15}^{*}\\ Y_{41}^{*}& Y_{44}^{*}-Y_{45}^{*}+\mathrm{j}\omega ·C_{ms}\end{array}\right]·\left[\begin{array}{c}{V}_{dev}\\ V_L\end{array}\right]$$

(23)

$$Z\mathrm{in}=\frac{V_{\mathrm{dev}}}{I_{dev}}=\frac{Y_{45}-Y_{44}-\mathrm{j}\omega ·C_{dev}-Y_L}{(Y_{11}^{*}+\mathrm{j}\omega ·C_{ms})·(Y_{45}^{*}-Y_{44}^{*}-\mathrm{j}\omega ·C_{ms}-Y_L)+(Y_{14}^{*}-Y_{15}^{*})Y_{41}^{*}}$$

(24)

4.3. Proposed Distributed Transformer Model for Interstage Network Design

The proposed distributed transformer model for interstage matching network analysis is shown in Figure 10. R_L and C_eqv parallel units represent the optimum impedance of load device. In this case, the proposed model is extended to a fully differential network for analyzing interstage matching networks. With the differential signal from the previous stage, it can be expressed as V₄ = −V₅ = V_dev, I₄ = −I₅ = I_dev. Current relationship at the load is I_L = −2Y_L × V_L. Based on similar analysis methods, the resulting current and voltage relationship can be deducted as:

$$\left[\begin{array}{c}{I}_{\mathrm{dev}}\\ I_L\end{array}\right]=\left[\begin{array}{cc}{Y}_{44}^{*}-Y_{45}^{*}+\mathrm{j}\omega ·C_{mp}& Y_{41}^{*}\\ Y_{14}^{*}-Y_{15}^{*}& Y_{11}^{*}+\mathrm{j}\omega ·C_{ms}\end{array}\right]·\left[\begin{array}{c}{V}_{dev}\\ V_L\end{array}\right]$$

(25)

Optimum input impedance should match the device port.

$$Z_{\mathrm{in}}=\frac{V_{\mathrm{dev}}}{I_{dev}}=\frac{2Y_L+Y_L^{*}+j\omega ·C_{mp}}{Y_{41}^{*}(Y_{15}^{*}-Y_{14}^{*})+(Y_{44}^{*}-Y_{45}^{*}+\mathrm{j}\omega ·C_{ms})(2Y_L+Y_{11}^{*}+\mathrm{j}\omega ·C_{mp})}$$

(26)

4.4. Transformer Design Procedure

Based on the analysis above, this work provides a practical way to design coplanar asymmetry transformers, and the corresponding procedures are shown in Figure 11. To begin with, the port impedance at transformer matching circuit can be measured. Note that for maximum output power and efficiency, the output active devices in PAs must be loaded by optimum load impedance determined by the large-signal loadpull/loadline simulations, which are typically very different from conjugately matching. This is one of the major differences between small-signal linear amplifier design and PA design [27].

The target impedance acquired through load-pull and source-pull largely decides turning transformer ratio n, in Equation (27) [14]. If the n is set as for the impedance transformation, the maximum current gain can be obtained over infinite bandwidth [21].

L₁ and L₂ represent equivalent inductance of primary and secondary winding respectively. Coupling coefficient is related to bandwidth and gain flatness within the band of interest. In Equation (28), maximum and minimum angular frequency are represented respectively. Based on these equations, transformer schematic parameters can be determined.

$${\mathrm{n}}^2=\frac{L_1}{L_2}=\frac{re(Z_{\mathrm{opt},1})}{re(Z_{\mathrm{opt},2})}$$

(27)

$${\omega }_{L,H}={\omega }_0\sqrt{1\pm \mathrm{k}}$$

(28)

However, these parameters have design limitations within specific processes. At the second step, we need to judge whether the calculated parameters are of practical use in the design. For example, in 0.25 µm-GaN technology process, the inductance value should be limited to below 0.8 nH, and coupling coefficient is better to adjust under 0.5, or some other performances will suffer. Thus, we need to tune parameters and make trade-offs until a set of acceptable parameters are obtained.

The last two steps are layout design process, d represents transformer inner diameter, w1 for primary winding line width and w2 for the secondary. Parameter s represents distance between primary and secondary inductance. The simulation result can be checked via EM simulation. If the designed transformer does not meet the goal, we need to adjust the physical scale of the layout until the final design is formed.

5. Transformer Matching Based Power Amplifier Design on GaN

Using coplanar asymmetry on-chip transformer distributed model in this design has greatly reduced transformer layout iteration design times, and that greatly releases the designer’s pressure. The proposed two-stage drive amplifier based on a transformer matching circuit schematic and layout design are shown in Figure 12 and Figure 13.

The proposed GaN PA with transformer matching circuit is designed on a 0.25 µm GaN technology process. All three matching circuits are based on transformer design. Both the input and output ports are matched to 50 Ohm. The second stage transistors are respective choosing 4 × 120 µm OSV for larger output power, and the first stage transistor, 4 × 100 µm OSV, is chosen for sufficient power gain. They are all based at V_g = −2 V, V_d = 28 V, Class-AB condition, with the source connected to the ground and drain port biased from the transformer central tap. The transformer central tap greatly simplifies the bias circuit design process, and it is insensitive to the entire circuit performance. That enables us to design bias circuits with more freedom and explore a new method for X-band MMIC PA design.

For accuracy, the PAD and bonding wires’ EM effect are included in this design. As Figure 14a shows, from 8 to 13 GHz the small-signal gain varies between 14.555~16.094 dB, and the gain flatness is 1.539 dB. The input matching is better than −11 dB within X band. Correspondingly, −4.145 [email protected] GHz for the S22. The PA output power is above 29.5 dBm within the frequency band, as shown in Figure 14b.

For PA stability consideration, StabFact, Mu, and b are all included and shown in Figure 15a,b. The results shows that for StabFact and Mu > 1, b > 0 in an extended frequency band, the proposed PA is unconditionally stable (the equations for factors StabFact, Mu and b are listed in Appendix A).

Table 3. Performance summary and comparison with related researches [28,29,30,31,32].

Ref.	[28]	[29]	[30]	[31]	[32]	This Work
Process	GaN	GaN	0.25 µm GaN	0.25 µm GaN	0.25 µm GaAs	0.25 µm GaN
Structure	Two-stage	Two-stage	Two-stage	Distributed	Two-stage	Two-stage
Matching Topology	Reactive	Reactive	Reactive	Reactive	Reactive	Transformer matching
Vdd (V)	35	30	28	20	5/8	28
Bandwidth (GHz)	8~12	8.5~14	10~12	8~12	8.5~9.5	8~12
Gain (dB)	16	-	12~15	24~30	19.6	15
IRL (dB)	-	-	−14	<−11	<−9	<−11
P1dB (dBm)	28~29.1	-	-	-	-	24.54~28.16
Psat (dBm)	~32	34.5~38.2	31	30.5~32.5	28.8~29.6	29.64~33.05
Power consumptionsat (W)	19.51	-	5.49~6.71	8.15~11.95	2.03	10.07~14.89
PAEsat (%)	8	-	18~22	10.5~15.4	33.5~44.4	5.3~11.55
Chip Size (mm2)	6	6	4.86	4.67	4	1.151

presents a comprehensive performance comparison of related researches, [28,29,30,31,32] to this work designed transformer matching MMIC PA and a comparison of the latest works of other published PA over the X-band. Obviously, transformer matching topology enables a more compact layout of the circuit.

6. Conclusions

This paper proposed a coplanar asymmetry transformer distributed model for PA design on GaN technology process, and related transformer-based matching circuit designing and analyzing methods are studied. The proposed model can predict the coplanar asymmetry transformers performance up to a millimeter wave band. By using the proposed model, an X-band GaN PA with a transformer matching circuit is designed. According to previous research, this is the first case for transformer-based matching circuit design on GaN MMIC.