Hardware Acceleration of Identifying Barcodes in Multiplexed Nanopore Sequencing

Abstract

In multiplexed sequencing, the identification of DNA sequencing barcodes can effectively reduce the probability of sample misassignment. However, the great quantity of sequence data requires a high-throughput identification method. Therefore, based on a barcode identification scheme combining cyclic shifting with dynamic programming (DP), this paper proposes, implements and tests a hardware accelerator that can accelerate barcode identification. In the accelerator, considering that the computational complexity of the DP algorithm can be expressed as the multiplication of the lengths of both involved sequences, we design a systolic array structure with simplified processing element (PE) and a parallel circuit architecture to identify the insertion and deletion errors based on the traceback. The accelerator is implemented on a field-programmable gate array (FPGA), and its performance is compared with that of software implemented on a general-purpose computer. The experimental results indicate that, compared with the software implementation, the accelerator can achieve speedups of two orders of magnitude for longer barcodes.

1. Introduction

Next-generation sequencing (NGS) technologies can generate up to one billion reads of DNA sequence per slide, which continuously increase at a rapid pace [1,2]. Multiplexed nanopore sequencing has become an essential strategy to effectively utilize the rising sequencing capacity of NGS technologies [3]. In the multiplexing strategy, specific sample tags, also termed barcodes [4,5], are added to DNA fragments from multiple samples and used to separate sequencing reads belonging to different samples after sequencing. However, DNA barcodes are often corrupted by insertions, deletions, and substitutions during DNA synthesis and sequencing, resulting in sample index misassignments [6]. Therefore, some barcode construction and identification methods with different error correction capacity have been proposed in the past.

Conventional construction and identification methods for DNA barcodes are based on Hamming distance [7,8], Levenshtein distance [9,10], watermark code [11], etc. Recently, in [12], a scheme that combines a pseudorandom sequence with a cyclic block code was proposed to construct barcodes while the cyclic shifting and DP algorithm were used to identify barcodes. This scheme had the advantages of a low complexity and high robustness. However, if we still rely on software tools to realize these approaches, it will fail to meet the high-throughput sequencing requirement due to the fact that more and more sequencing reads need to be sorted and separated [13,14,15]. Compared to central processing units (CPUs), FPGAs provide a higher bit-level data parallelism and can customize hardware according to the requirements, which leads to a higher computing speed [16,17]. Therefore, taking the scheme proposed in [12] as an example, this paper designs and implements an FPGA-based hardware accelerator.

The cyclic shifting and DP algorithm are the important components of the accelerator. The cyclic shifting can be realized by a shift register in hardware. As a commonly used algorithm for sequence alignment, the DP algorithm has the computational complexity of the square of the length of the sequences, so it is crucial to accelerate the algorithm [18]. Recently, an FPGA used to realize a linear systolic array (LSA) to accelerate sequence alignment attracted extensive attention, and a series of studies were conducted. The general structures of the LSA were introduced in [19,20,21,22], but there were some deficiencies in these works. On one hand, the iterative equation of the sequence alignment algorithm was directly mapped to the PE. On the other hand, the above works did not describe the implementation of the identification of insertions and deletions in detail.

In this paper, a hardware accelerator for a barcode identification algorithm with a high robustness and low complexity is implemented and evaluated. Aiming at the quadratic complexity of the DP algorithm in the identification scheme, we propose an optimization strategy to improve the mapping efficiency of the PE by simplifying the mapping circuit of the iterative equations. Meanwhile, according to the traceback algorithm, a parallel circuit is designed to simultaneously mark and correct insertion and deletion errors on barcodes. The function simulation and performance verification platform are designed and built, and the comparison between a CPU platform and an FPGA acceleration platform is completed. The hardware results indicate that the accelerator has a significantly higher identification speed of sequencing barcodes than the software version of the same algorithm running on the general-purpose computer.

2. Background

This section reviews the related works, including the barcode identification scheme proposed in [12] and the DP algorithm for identifying an insertion/deletion (indel).

2.1. Sequencing Barcode Identification Method

In multiplexed sequencing, DNA barcodes are added to each DNA fragment as special sample tags. After sequencing, sequencing reads belonging to different samples are separated by identifying barcodes. However, the insertions, deletions, and substitutions may occur randomly on barcodes due to the defects in DNA synthesis and sequencing, as shown in Figure 1. NGS technologies itself have error rates of ${10}^{-3}$∼${10}^{-4}$ [10]. For nanopore sequencing, the sequencing reads are quite long. Correspondingly, its sequencing error rate is very high (15.1%), of which indels are the main error type (10%) and the rest consists of substitutions (5.1%) [23]. These errors confuse the source of samples, which in turn reduces the accuracy of sequencing. Therefore, DNA barcodes need to be designed to resist insertion, deletion, and substitution errors, which is important for improving the sequencing accuracy of NGS.

Aiming at various types of errors introduced during multiplexed nanopore sequencing, a new DNA barcode construction scheme was proposed in [12], which combined a pseudorandom sequence with a cyclic block code and converted them into bases by bit pairs. Here, the pseudorandom sequence acted as a hidden component of sequencing barcodes to identify indels and the cyclic block code was used against the substitution errors. For the barcode generated by the above construction scheme, an identification method using cyclic shifting and DP was proposed. The specific process of decoding barcodes in this scheme is summarized in Figure 2. We took the constructed barcode “GATGCTA” as an example, and it was assumed that a base “C” was inserted into the second position of the barcode and the base “C” at the fifth position of the barcode was deleted during sequencing.

The decoding process of the corrupted barcode is described below. Specifically, we read the corrupted barcode r and the known pseudorandom sequence p from the text files as the input of the identification scheme. First, the corrupted barcode r is demapped into the corrupted sequence s and the corrupted codeword d. Subsequently, we found that when s and d are cyclically shifted to the left i = 2 times, the inserted base is moved to the end. When we cyclically shift the pseudorandom sequence p to the left j = 1 time and use DP to compare the ${\mathbf{p}}^{\left(1\right)}$ and ${\mathbf{s}}^{\left(2\right)}$, it can identify the positions of an indel and modify the codeword ${\mathbf{d}}^{\left(2\right)}$. Then, the modified codeword ${\mathbf{d}}_{\mathbf{c}}^{\left(1\right)}$ is sent to the decoder for decoding. Finally, the decoded codeword ${\mathbf{ĉ}}^{\left(1\right)}$ is cyclically reverse-shifted to obtain the final result ĉ, which was output to a text file. Using the information bits of the codeword ĉ, the sequencing reads are assigned to their respective samples. The above method is summarized in Algorithm 1. (Adapted with permission from ref. [12]. Copyright 2022 Springer Nature.)

Algorithm 1 Barcode identification algorithm in [12]

Input:  the corrupted barcode r and the predetermined pseudorandom sequence p Output:  the decoded codeword ĉ 1: Demap barcode r = $\left(r_0,r_1,\dots ,r_{n-1}\right)$ to sequence s = $\left(s_0,s_1,\dots ,s_{n-1}\right)$ and code d = $\left(d_0,d_1,\dots ,d_{n-1}\right)$; 2: fori = 0; i < n; i++ do 3:    Shift cyclically s and d to the left i times, denoted as ${\mathbf{s}}^{\left(i\right)}$ and ${\mathbf{d}}^{\left(i\right)}$; 4:    for j = 0; $j\le l$; j++ do 5:      Shift cyclically p to the left j times, denoted as ${\mathbf{p}}^{\left(j\right)}$ 6:      Identify indel positions in sequence ${\mathbf{s}}^{\left(i\right)}$ using DP 7:      Modify ${\mathbf{d}}^{\left(i\right)}$ with marked positions, obtaining the modified codeword ${\mathbf{d}}_{\mathbf{c}}^{\left(j\right)}$ 8:      Send ${\mathbf{d}}^{\left(i\right)}$ to cyclic code decoder for decoding, obtaining the codeword ${\mathbf{ĉ}}^{\left(j\right)}$ 9:      Calculate the syndrome ${\mathbf{S}}^{\left(j\right)}$ for ${\mathbf{ĉ}}^{\left(j\right)}$ 10:      if ${\mathbf{S}}^{\left(j\right)}$ = 0 then 11:         Select ${\mathbf{ĉ}}^{\left(j\right)}$ as the final decoded result 12:         Shift cyclically ${\mathbf{ĉ}}^{\left(j\right)}$ to the right j times to obtain ĉ 13:         Goto final 14:      end if 15:    end for 16: end for 17: final

2.2. DP Algorithm for Identifying Indel

The essence of the DP algorithm is to find an optimal path from the target sequence to the reference sequence and judge the position of an indel through this path. The basic process of identifying indels using DP algorithms can be described as follows. First, we build a two-dimensional matrix. Next, we use an iterative equation to calculate the value of the edit distance between the two sequences and store it in the matrix. Then, we use the backtracking algorithm to find an optimal path in the two-dimensional matrix. Finally, we use the optimal path to determine the position of indels in the target sequence.

In the barcode identification scheme, the DP algorithm is exploited to calculate the edit distance and obtain the optimum alignment for the sequences s and p. Based on the optimum alignment, the positions of insertions and deletions can be determined [24]. It can be seen that the edit distance calculation and the optimum path backtracking are the key links that affect the complexity of the DP algorithm [25].

Assuming that the lengths of two sequences A and B are, respectively, m and n, and the elements in the sequence are, respectively, denoted as $A\left[i\right]$ and $B\left[j\right]$ ($1\le i\le m$, $1\le j\le n$), the specific process of using DP to realize the indel identification is as follows.

1.

Calculate the edit distance $D(i,j)$ between sequence elements $A\left[i\right]$ and $B\left[j\right]$; the calculation equation is

$$D(i,j)=\min \left\{\begin{array}{c}D(i-1,j)+w_d,\hfill \\ D(i,j-1)+w_i,\hfill \\ D(i-1,j-1)+w_z,\hfill \end{array}\right.0\le i\le m,0\le j\le n.$$

(1)

where $w_d$ = $w_i$ = 1 and $w_z$ = 0 if $A\left[i\right]$ = $B\left[j\right]$, otherwise $w_z$ = 1 [26]. The initial values of the iterative equation are given by $D(i,0)=i$ and $D(0,j)=j$ for $0\le i\le m$ and $0\le j\le n$.

2.

Backtrack from $D(m,n)$ to $D(0,0)$ to find the optimum path ${\mathbf{I}}_{\mathbf{path}}$(i,j), which can be expressed as

$${\mathbf{I}}_{\mathbf{path}}(i,j)=\left\{\begin{array}{cc}(i-1,j),\hfill & \min =D(i-1,j).\hfill \\ (i,j-1),\hfill & \min =D(i,j-1).\hfill \\ (i-1,j-1),\hfill & \min =D(i-1,j-1).\hfill \end{array}\right.$$

(2)

3.

Use the optimum path ${\mathbf{I}}_{\mathbf{path}}$(i,j) to get the vector ${\mathbf{I}}_{\mathbf{mark}}$(i,j) that marks the indel positions, as follows

$${\mathbf{I}}_{\mathbf{mark}}(i,j)=\left\{\begin{array}{cc}1,\hfill & {\mathbf{I}}_{\mathbf{path}}(i,j)=(i-1,j)\left(\mathrm{deletion}\right).\hfill \\ 2,\hfill & {\mathbf{I}}_{\mathbf{path}}(i,j)=(i,j-1)\left(\mathrm{insertion}\right).\hfill \\ 3,\hfill & {\mathbf{I}}_{\mathbf{path}}(i,j)=(i-1,j-1)\left(\mathrm{mis}/\mathrm{match}\right).\hfill \end{array}\right.$$

(3)

4.

Based on the marker vector ${\mathbf{I}}_{\mathbf{mark}}$(i,j), the insertion and deletion errors on the corrupted sequence can be corrected.

Observing the above iterative equation for calculating edit distance, we can see that the time and space complexity of the DP algorithm are both $O\left(mn\right)$. The general method to reduce the time complexity of the algorithm is to establish the LSA structure [27,28]. Since the performance of the LSA mainly depends on the number of PEs and the clock frequency of the PE [29], a simplified design of the PE can improve the performance of the LSA to a certain extent.

3. Barcode Identification Accelerator

Based on the barcode identification method proposed in [12], the overall architecture of the hardware accelerator designed in this paper is illustrated in Figure 3. The accelerator consists of several modules, including demapping, cyclic shifting, dynamic programming, cyclic code decoder, and so on. The input of the accelerator includes an n-bit predetermined pseudorandom sequence p and a $2n$-bit corrupted barcode r converted from n-nt bases (strings), and the output is the final result $\widehat{\mathbf{c}}$ obtained by cyclically shifting the decoded codeword ${\widehat{\mathbf{c}}}^{\left(k\right)}$ to the right k times.

The specific process of hardware implementation is explained as follows. The working state of each module is controlled by a finite state machine.

1.

The $2n$-bit barcode r = $\left(s_0{d}_0,s_1{d}_1,\dots ,s_{n-1}{d}_{n-1}\right)$ is transformed into the sequence s = $\left(s_0,s_1,\dots ,s_{n-1}\right)$ and code d = $\left(d_0,d_1,\dots ,d_{n-1}\right)$ through the demapping module;

2.

In the cyclic shifting module, it is assumed that the code d and the sequence s have been cyclically shifted to the left l times ($0\le l<n$) to obtain the sequence ${\mathbf{s}}^{\left(l\right)}$ and codeword ${\mathbf{d}}^{\left(l\right)}$. Meanwhile, the predetermined sequence p has been cyclically shifted to the left k times ($0\le k\le l$) to obtain the sequence ${\mathbf{p}}^{\left(k\right)}$;

3.

The shifted sequences ${\mathbf{s}}^{\left(l\right)}$, ${\mathbf{p}}^{\left(k\right)}$, and code ${\mathbf{d}}^{\left(l\right)}$ are input into the dynamic programming module. Through the processing of this module, the indel identification of code ${\mathbf{d}}^{\left(l\right)}$ is realized by calculating the edit distance of the sequences s and p and backtracking the optimal path, and we get the modified codeword ${\mathbf{d}}_{\mathbf{c}}^{\left(k\right)}$;

4.

Subsequently, the remaining substitution errors on the codeword ${\mathbf{d}}_{\mathbf{c}}^{\left(k\right)}$ are decoded by the cyclic code decoder. If the decoded codeword ${\widehat{\mathbf{c}}}^{\left(k\right)}$ meets the condition, that is, all syndromes equal to zero, it is cyclically shifted to the right k times as the final output result. Otherwise, the accelerator returns to the cyclic shifting module.

5.

In the cyclic shifting module, if $(k+1)<l$, we cyclically shift the sequence ${\mathbf{p}}^{\left(k\right)}$ to the left once, and then perform indel identification. When $(k+1)=l$, if $(l+1)<(n-1)$, the sequence ${\mathbf{s}}^{\left(l\right)}$ and the codeword ${\mathbf{d}}^{\left(l\right)}$ are cyclically shifted to the left once, and then indel identification is performed; otherwise, the accelerator directly outputs the final decoding result $\widehat{\mathbf{c}}$.

Considering that the computational complexity of the DP algorithm in this paper is $O\left(n^2\right)$, with the increase of the number of cyclic shifts, the overall operation efficiency of the barcode identification algorithm will be seriously affected. Therefore, the hardware acceleration of the dynamic programming module is described in detail in this paper. Specifically, the hardware circuit of this module includes three submodules: (a) an edit-distance calculation module; (b) an insertion-and-deletion-errors-marking module, called indel-marking module; and (c) an insertion-and-deletion-errors-correction module, called indel-correction module.

3.1. Dynamic Programming Module

This section details the hardware acceleration of the dynamic programming module, mainly including an LSA structure with the simplified PE and a parallel circuit for identifying insertion and deletion errors.

3.1.1. Edit-Distance Calculation Module

To realize hardware acceleration of the DP algorithm, an LSA structure was constructed to implement the parallel computation of the edit distance between the predetermined sequence ${\mathbf{p}}^{\left(k\right)}$ and the corrupted sequence ${\mathbf{s}}^{\left(l\right)}$. All of the edit distance values $D(i,j)$ can be stored in a two-dimensional array of size $(n+1)(n+1)$. Figure 4 describes the LSA structure constructed in this paper. The number of PE in the LSA is determined by the length n of the pseudorandom sequence p. The $n+1$ PEs are placed horizontally, and each PE is responsible for calculating a column of elements in the two-dimensional array.

PE${}_0$ is responsible for the calculation of the first column element in the two-dimensional array, and its accumulation operation can be implemented with a simple accumulator. In the first clock cycle, an initial value is assigned to the $D_{buf}$ port of each PE, which comes from the corresponding first row element in the two-dimensional array. The start and end signals of two adjacent PEs are always separated by one clock cycle. In each clock cycle, all PEs calculate the edit distance in parallel. After $2n$ clock cycles, the minimum edit distance $D(n,n)$ is output by PE${}_n$.

The architecture of the PEs except PE${}_0$ is illustrated in Figure 5. In previous works, researchers directly mapped the iterative equation to PE [19,20]. Such a PE is shown in Figure 5a. Obviously, the directly mapped PE contains three addition operations and two comparison operations. On this basis, we propose a simplified PE architecture, as depicted in Figure 5b. The design of this architecture is also based on Formula (1), but the mapping circuit of the equation is simplified. Specifically, we adjust the execution order of the comparison operation and the addition operation, thereby reducing the number of adders in the circuit when directly mapping the iterative equation and improving the mapping efficiency of the PE. The redesigned PE architecture first performs the comparison operation between $D(i-1,j)$ and $D(i,j-1)$, then performs the comparison operation between $Yout$ and $Xout$, and finally outputs the minimum value $D(i,j)$.

Figure 5b describes the PE${}_j$ responsible for calculating the editing distance of the elements in the $j\mathrm{th}$ column. Two sequences are simultaneously sent to PE${}_j$ for alignment, and all the needed data for the PE${}_j$ come from itself and other PEs in the systolic array. The details are as follows:

• PE${}_1$ sequentially receives ${\mathbf{s}}^{\left(l\right)}\left[i\right]$ in every clock cycle and sends it to PE${}_2$ in the next clock cycle. Similarly, PE${}_j$ receives the 1-bit ${\mathbf{s}}^{\left(l\right)}\left[i\right]$ from PE${}_{j-1}$ and outputs it to PE${}_{j+1}$ in the following clock cycle;
• The elements in every column correspond to one bit, respectively, in the sequence ${\mathbf{p}}^{\left(k\right)}$. In other words, as far as PE${}_j$ is concerned, the corresponding bit in the sequence (i.e., ${\mathbf{p}}^{\left(k\right)}\left[j\right]$) is constant, and it is only read at the beginning of the process;
• At the $t\mathrm{th}$ clock cycle, the input $D(i-1,j)$ of PE${}_j$ is the output result of the same PE${}_j$ in the $(t-1)\mathrm{th}$ clock cycle. Moreover, the input $D(i,j-1)$ and $D(i-1,j-1)$ of PE${}_j$ are the output results of the PE${}_{j-1}$ in the $(t-1)\mathrm{th}$ and $(t-2)\mathrm{th}$ clock cycles, respectively;
• The calculated result $D(i,j)$ is not only the input of PE${}_{j+1}$, but also stored in a random access memory (RAM) with a width of K bits and depth of $(n+1)(n+1)$, where n is the sequence’s length, and it satisfies $2^K\ge n$.

3.1.2. Indel-Marking Module

According to the intermediate calculation results stored in RAM, the indel-marking module searches the optimum path by traceback and marks the position where the indel appears on the sequence ${\mathbf{s}}^{\left(l\right)}$. Contrary to the process of calculating the edit distance, the traceback needs to find the optimal path starting from the lower right corner element of the two-dimensional array. The execution time of this module is related to the length n of the pseudorandom sequence and the number N of indel errors. Since each search for a traceback point takes one clock cycle, the number of clocks required to find the entire traceback path is T = $n+N$.

The hardware architecture of the indel-marking module is shown in Figure 6, and the implementation of this architecture is divided into the following three steps. First, starting from the RAM$\left[n\right]\left[n\right]$ and taking the RAM$\left[i\right]\left[j\right]$ as the reference element, the minimum value of the three elements is selected in the order from the upper left(RAM$[i-1][j-1]$), left(RAM$[i-1]\left[j\right]$), to top(RAM$\left[i\right][j-1]$). Then, the insertion, deletion, and substitution or correct transmission are detected according to the current position where the minimum value is located. Finally, the element with the minimum value is taken as the next reference cell, and the previous two steps are repeated until the traversal reaches RAM[0][0].

Specifically, the rules of the second step are described as follows.

• If $D(i,j-1)$ is the minimum, it means that an insertion error appears in the sequence ${\mathbf{s}}^{\left(l\right)}$ at the position $i-1$ to i. In this case, the shift register sfr1 writes 2-bit data “01” in the upper direction;
• If $D(i-1,j)$ is the minimum, it indicates that a deletion error appears in the sequence ${\mathbf{s}}^{\left(l\right)}$ at the position $i-1$ to i. In this case, the shift register sfr1 writes 2-bit data “10” in the upper direction;
• If $D(i-1,j-1)$ is the minimum, it means that the data are transmitted correctly or there is a substitution error in the sequence ${\mathbf{s}}^{\left(l\right)}$ at position $i-1$. In this case, the shift register sfr1 writes 2-bit data “11” in the upper direction.

The traceback process finishes after T clock cycles. At this time, the shift register sfr1 stores $2T$-bit data. These data contain the position information of insertions and deletions.

3.1.3. Indel-Correction Module

The indel-correction module corrects the insertion and deletion errors on the corrupted codeword ${\mathbf{d}}^{\left(l\right)}$ according to the error locations provided by the indel-marking module. Therefore, the indel-marking module and the indel-correction module can be implemented in parallel on hardware. Figure 7 describes the hardware implementation architecture of the indel-correction module. The locations of the insertion and deletion errors on the sequence ${\mathbf{s}}^{\left(l\right)}$ are stored in the shift register sfr1, and the corrupted codeword ${\mathbf{d}}^{\left(l\right)}$ is stored in the shift register sfr2.

At the same clock pulse, if the output data of the sfr1 are “11”, sfr2 will shift out one bit of the data and these data will be written to the high position of the shift register sfr3. If the output data element of the sfr1 are “10”, sfr2 will stay still, and random data (i.e., “0” or “1”) will be written into the sfr3. If the output data of sfr1 are “01”, sfr2 will shift out one bit of the data to an additional register and sfr3 will stay still. After T clock cycles, the piece of data stored in sfr3 is the corrected codeword ${\mathbf{d}}_{\mathbf{c}}^{\left(k\right)}$.

For the dynamic programming module, the total number of clock cycles required to calculate edit distance, mark indels, and correct indels is $2n+T$. Compared with the serial computation amount of $n^2+2T$ in the software implementation, the computing time is greatly shortened.

3.2. Cyclic Code Decoder

The cyclic code decoder is another key error correction module in the accelerator. Due to the use of cyclic block codes in barcodes, the remaining substitution errors can be corrected. In this paper, the Bose–Chaudhuri–Hocquenghem (BCH) codes consistent with the software program were chosen as the coding scheme. BCH codes have been proven to be excellent error-correcting codes with relatively strong error-correcting capability, which are simple to encode and decode [30]. Figure 8 shows the overall architecture of a BCH decoder, which mainly includes three blocks, namely, the syndrome calculation block, the key equation solver(KES) block and the Chien search block.

In the accelerator, the BCH decoder is responsible for correcting the remaining substitution errors on the codeword ${\mathbf{d}}_{\mathbf{c}}^{\left(k\right)}$. In the meantime, the syndrome output by the syndrome calculation block can be used to judge whether the codeword is correct. If all the syndromes are zero, the judgment condition is satisfied and the codeword is error-free; otherwise, it is not satisfied. The most important and complicated part of the BCH decoder is the KES block. It requires a lot of hardware resources to calculate the error locator polynomial. In this paper, the inversionless Berlekamp–Massey (IBM) algorithm [31] was adopted as the iterative decoding algorithm because it had a relatively low hardware implementation complexity. Meanwhile, its execution speed and device utilization can be improved by parallel processing methods. Thus, this paper adopted and implemented a BCH decoder with a high-speed parallel architecture [32].

4. Results

This section focuses on the implementation results of the accelerator. We comprehensively evaluate the accelerator’s function and performance from three aspects: robustness, resource utilization, and acceleration effect.

4.1. Performance Verification

To verify the accuracy and robustness of the barcode identification accelerator, the same noisy channel model was adopted in hardware. It included two different error scenarios (random scenario and context scenario) and a simplified channel model of insertion/deletion/substitution (IDS) [33,34].

The two scenarios were generalized as follows. For the random scenario, the same number of insertion and deletion occurred on the barcode, so the length of the barcode was unchanged. For the context scenario, the number of insertions or deletions that occurred on the barcode varied, and the length of the barcode was thus changed [6]. To simulate various errors introduced on the barcode, the sequencing process was modeled as a noisy channel model similar to that in communication systems. In this channel, barcodes were inserted, deleted, and substituted with a certain probability. The channel was described by three parameters: insertion probability $P_i$, deletion probability $P_d$, and substitution probability $P_s$. We validated the robustness of the barcode identification scheme by estimating the identification error rate $P_e$ (i.e., the probability that a corrupted barcode is decoded incorrectly).

The software simulation was realized by using the software program in [12]. This program includes the generation of a barcode, the setting of the sequencing channel and the identification of the barcode. In the software program, cyclic codes and predetermined pseudorandom sequences were combined bit by bit to form sequencing barcodes. After the generated barcodes passed through the noisy channel, the corrupted barcodes were obtained. In the sequencing channel, we could choose different error scenarios and set different mutation probability of barcodes. Taking the corrupted barcodes as input, the software simulation and hardware implementation of the barcode identification were performed.

First, we investigated the identification error rate $P_e$ of the hardware implementation and software simulation for the 15-nt sequencing barcode constructed with BCH(15, 5, 3) in the two different scenarios. For each scenario, 200 barcodes were randomly selected from the relevant database for validation. The mutation probability of each base on the barcode was $P_{\mathrm{mut}}\in \left[0.12,0.33\right]\left(P_i=P_d=P_s\right)$, where $P_{mut}$ = $P_i$ + $P_d$ + $P_s$. The simulation results are shown in Figure 9. The experimental results show that the hardware implementation results are consistent with the software simulation results regardless of the random scenario or the context scenario. Therefore, it is verified that the accelerators can be applied to two different error scenarios and achieve the same performance as the software simulation for different error scenarios.

Then, to verify the robustness of the hardware accelerators, two types of barcodes were constructed by BCH codes with the same error correction ability but different lengths. Specifically, the 31-nt barcodes were constructed with BCH(31,16,3) and the 15-nt barcodes were constructed with BCH(15,5,3). For each length, 200 barcodes were randomly selected from the relevant database for hardware and software validation. The simulation experiment was performed under the same error scenario. Figure 10 shows the identification error rate $P_e$ of the sequencing barcodes implemented by hardware and software in the random scenario under different mutation probabilities $P_{\mathrm{mut}}\in \left[0.1,0.33\right]\left(P_i=P_d=P_s\right)$. It is observed that the hardware accelerators built for barcodes of different lengths can also achieve the same robustness as that of software simulations under the same error scenario.

4.2. Hardware Implementation Results

We wrote Verilog codes for accelerators with barcode lengths of 12-nt, 15-nt, and 31-nt. All designs were mapped on a Virtex-6 XC6VLX240T FPGA using the Xilinx ISE 14.7 development suite. This family was only used because of its availability and the fact that we did not need to change the core code to use different chips. Using larger or newer FPGAs should enable longer barcode identification and yield better results. The accelerator took the FPGA chip as the core and realized the communication between a host CPU and the FPGA through the PCIe. The PCIe interface controller was implemented based on Xilinx PCIe IP. On the CPU side, corrupted barcodes and pseudorandom sequences were transferred from the main memory via direct memory access (DMA). On the FPGA side, two asynchronous FIFOs were used to buffer the input data.

Taking the 12-nt, 15-nt, and 31-nt sequencing barcodes constructed from BCH(12, 4, 2), BCH(15, 5, 3), and BCH(31, 16, 3) codes as an example, we observed the implementation results of the three accelerators on the FPGA. Among them, BCH(12, 4, 2) was a shorted cyclic BCH code, which was generated using BCH(15,7,2). The overall on-chip resource utilization and maximum clock frequency of the three accelerators are listed in

Table 1. The implementation results of the three accelerators.

Barcode Length	Registers	LUTs	Slices	${\mathit{f}}_{\mathbf{max}}$/MHz
12-nt	1084 (1%)	2676 (1%)	983 (2%)	226.4
15-nt	1860 (1%)	4583 (3%)	1366 (3%)	228.7
31-nt	7093 (2%)	24,712 (16%)	8171 (21%)	198.6

. It is seen that each of these three types of accelerators occupies a small amount of logic resources of the FPGA, and the maximum frequency of the accelerator designed for barcodes of length 15 can reach 228.7 MHz. However, it is apparent that for larger barcodes, the FPGA resources consumed by the accelerator increase significantly.

In addition, we compared the runtime of software and hardware for barcodes identification. To obtain the runtime of the pure software implementation, the original software code was run on a computer configured with an Intel Core i7-10700 microprocessor (eight-core, sixteen-thread, 4.8 GHz) and main memory with a capacity of 16 GB. The software solution came from the software program in [12], which compiles and runs directly in Visual Studio 2019. The hardware execution time was the time from the hardware startup to the output of the decoded result to the memory. The time required by the CPU and FPGA to identify barcode sequences of different lengths is listed in

Table 2. Comparison of the runtime for different lengths of sequencing barcodes identification based on CPU and FPGA.

Barcode Length	BCH Code	CPU	FPGA	Speedup
12-nt	(12,4,2)	4 m 30.3 s	3.9 s	69×
15-nt	(15,5,3)	6 m 54.5 s	5.3 s	78×
31-nt	(31,16,3)	54 m 16.1 s	17.6 s	183×

, where the FPGA clocked at 100 MHz. For each length, 200,000 barcodes with the mutation probability $P_{\mathrm{mut}}\in \left[0.12,0.33\right]\left(P_i=P_d=P_s\right)$ were randomly selected from the relevant database for identification. To improve the accuracy of the results, the identification of each length was performed three times and the running time was averaged.

It can be observed in Table 2 that the accelerator is approximately 70–180× faster than the C implementation for representative input sizes, and this performance improvement increases with the length of the barcode. As a result, for longer barcodes, hardware-based accelerators outperform the software by two orders of magnitude in terms of the identification speed.

It was also important to compare the current implementation with the methods described in other literature works. In multiplex sequencing, the traditional DNA barcode design and identification methods are mostly realized by software. For example, Costea et al. [35] reported a fully customizable, fast, and accurate software package called TagGD (Tag Generator and Demultiplexer); Tambe et al. [36] proposed a software tool for identifying and correcting barcodes in single cell genomics, etc. The above methods were compared with the work in this paper, as shown in

Table 3. Comparison with other previous approaches.

Approach	Processor Type	Barcode Length	Number of Barcodes	Time	Processing Speed (reads/s)
Tambe et al. (2019) [36]	CPU	12	100,000	6 m 39 s	251
Costea et al. (2013) [35]	CPU	18	200,000	27.8 s	7194
Our Work	FPGA	31	200,000	17.6 s	11,363

. Since different platforms use different processors, algorithms, and datasets, the number of barcode reads that can be processed per second was used to evaluate the processing speed of different software and hardware solutions. It should be noted that for a given method, the longer the barcodes are, the longer the processing time is required. The comparison shows that although the barcodes identified by our hardware accelerator are the longest, the processing speed of the barcodes is the fastest.

5. Conclusions

In this paper, we presented the design and implementation of an FPGA-based hardware accelerator for a highly robust sequencing barcode identification algorithm. Considering that the DP algorithm in the identification scheme had the time complexity of $O\left(n^2\right)$, a systolic array structure was proposed, which improved the mapping efficiency of a PE by simplifying the circuit structure when the iterative equation was mapped to the PE. Moreover, according to the two-dimensional array stored in RAM, a parallel circuit using traceback to identify insertion and deletion errors was designed. The simulation results on an FPGA indicated that the accelerators constructed for sequencing barcodes with different lengths could achieve a speedup of about 70–180× compared to the general-purpose computer platform. Our future work will mainly focus on the hardware acceleration of sequencing barcode identification algorithms based on graphic processing unit (GPU).