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Article
Peer-Review Record

Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory

Electronics 2022, 11(17), 2738; https://doi.org/10.3390/electronics11172738
by Beomsu Kim and Myounggon Kang *
Reviewer 1:
Reviewer 2:
Reviewer 3: Anonymous
Electronics 2022, 11(17), 2738; https://doi.org/10.3390/electronics11172738
Submission received: 31 July 2022 / Revised: 23 August 2022 / Accepted: 29 August 2022 / Published: 31 August 2022
(This article belongs to the Special Issue Development and Application of New CMOS Devices)

Round 1

Reviewer 1 Report

Please see attached file

Comments for author File: Comments.pdf

Author Response

We are sincerely grateful for your thorough consideration and scrutiny of our manuscript, “Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory”. Through the accurate comments made by the reviewers, we better understand the critical issues in this paper. We have revised the manuscript according to the Reviewer’s suggestions. We hope that our revised manuscript will be considered and accepted for publication in the Electronics. We acknowledge that the scientific and clinical quality of our manuscript was improved by the scrutinizing efforts of the reviewers and editors.

The changes within the revised manuscript were highlighted (underlined and in blue). Point-by-point responses to the reviewers’ comments are provided below.

Author Response File: Author Response.pdf

Reviewer 2 Report

This paper analyzed the optimal bias condition of dummy WL for sub-block gate induced drain leakage erase operation in 16-layer 3D NAND flash memory. 

The reviewer generally supports the acceptance of this paper.

Here are a few minor comments that could be addressed to improve the paper.

1. Current 3D flash memory has over 200 layers. Whether the proposed solution could be applied to over 200-layer 3D NAND flash?

2. For 3D flash memory, it may incur thermal and process variation issues [1][2][3]. The authors should cite these related works and discuss whether the proposed solution will affect thermal and process variation issues.

[1] Yi Wang, Jiali Tan, Rui Mao, Tao Li: Temperature-Aware Persistent Data Management for LSM-Tree on 3-D NAND Flash Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4611-4622 (2020)

[2] Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu: Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation. SIGMETRICS (Abstracts) 2018: 106

[3] Yi Wang, Jiangfan Huang, Jing Chen, Rui Mao: PVSensing: A Process-Variation-Aware Space Allocation Strategy for 3D NAND Flash Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1302-1315 (2022)

 

 

Author Response

We are sincerely grateful for your thorough consideration and scrutiny of our manuscript, “Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory”. Through the accurate comments made by the reviewers, we better understand the critical issues in this paper. We have revised the manuscript according to the Reviewer’s suggestions. We hope that our revised manuscript will be considered and accepted for publication in the Electronics. We acknowledge that the scientific and clinical quality of our manuscript was improved by the scrutinizing efforts of the reviewers and editors.

The changes within the revised manuscript were highlighted (underlined and in blue). Point-by-point responses to the reviewers’ comments are provided below.

Author Response File: Author Response.pdf

Reviewer 3 Report

This paper investigates an optimum for the 'dummy WL' bias point in a conventional 3D NAND Flash memory employing a GIDL-based erase scheme with the purpose of enchancing the device reliability. TCAD-based simulations are used to explore the possibilities. In the reviewer's opinion, the paper is inadequate in both the textual descriptions as well as the accompanying figures, and needs major revisions on several fronts. Getting to some of the details:

First and foremost, before stepping into the Simulation Design and Results, please thoroughly elaborate the basic 3D NAND flash program and erase schemes (for this paper GIDL-based) in a new section to fill in the reader on the 'Background' of the research. This should accompany figures and can be even added to the Introduction. Be thorough in this section, describing in detail the program-erase sequence, the voltages involved and the detailed timing diagram. This helps the reader revise the concepts related to this area. 

Next, improvement is needed in all figures, involving timing axis. For instance, in Fig. 3 there are no axis, instead legends are provided. This is very hard to understand or read. Please provide a proper V vs. t axis and show all the signals in details. Figures are also small, recommend making the figures bigger to be easily readable and improve the associated font-size. There is three figures captioned as 'Figure 3'. How does the reviewer identify them, while giving you feedback ? Fonts, e.g. in fig. 2 are small.

Neither the introduction nor the results or the conclusion can be easily understood. Recommend restructuring the sentences and clearly outlining the innovation ('novel work') in this study. Make a comparison table with all prior works describing the techniques employed to improve / enhance reliability in a similar direction as yours and outline the differences in your / other works. 

Note that all these points are just basic preparations to make your paper understandable to the reviewers. The reviewer is yet to comment on the scientific merit of the work. Please thoroughly revise the paper and re-submit.

 

Author Response

We are sincerely grateful for your thorough consideration and scrutiny of our manuscript, “Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory”. Through the accurate comments made by the reviewers, we better understand the critical issues in this paper. We have revised the manuscript according to the Reviewer’s suggestions. We hope that our revised manuscript will be considered and accepted for publication in the Electronics. We acknowledge that the scientific and clinical quality of our manuscript was improved by the scrutinizing efforts of the reviewers and editors.

The changes within the revised manuscript were highlighted (underlined and in blue). Point-by-point responses to the reviewers’ comments are provided below.

Author Response File: Author Response.pdf

Round 2

Reviewer 3 Report

Thank you to the authors for revising the manuscript.

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