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Article

Design and Analysis of a Voltage-Mode Non-Linear Control of a Non-Minimum-Phase Positive Output Elementary Luo Converter

by
Satyajit H. Chincholkar
1,2,*,
Sangmesh V. Malge
3 and
Sanjaykumar L. Patil
3
1
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore
2
Department of Information Technology, Nutan Maharashtra Institute of Engineering and Technology, Pune 410507, India
3
Department of Instrumentation & Control Engineering, College of Engineering, Pune 411005, India
*
Author to whom correspondence should be addressed.
Electronics 2022, 11(2), 207; https://doi.org/10.3390/electronics11020207
Submission received: 1 December 2021 / Revised: 27 December 2021 / Accepted: 5 January 2022 / Published: 10 January 2022
(This article belongs to the Special Issue Advances in Low Power and High Power Electronics)

Abstract

:
The positive output elementary Luo (POEL) converter is a fourth-order DC–DC converter having highly non-linear dynamic characteristics. In this paper, a new dynamic output voltage feedback controller is proposed to achieve output voltage regulation of the POEL converter. In contrast to the state-of-the-art current-mode controllers for the high-order boost converters, the proposed control strategy uses only the output voltage state variable for feedback purposes. This eliminates the need for the inductor current sensor to reduce the cost and complexity of implementation. The controller design is accompanied by a strong theoretical foundation and detailed stability analyses to obtain some insight into the controlled system. The performance of the proposed controller is then compared with a multi-loop hysteresis-based sliding-mode controller (SMC) to achieve the output voltage-regulation of the same POEL converter. The schemes are compared concerning ease of implementation, in particular, the number of state variables and current sensors required for implementation and the closed-loop dynamic performance. Experimental results illustrating the features of both controllers in the presence of input reference and load changes are presented.

1. Introduction

DC–DC converters are widely used in various commercial applications such as electrical vehicles (EVs), hybrid electrical vehicles (HEVs), renewable energy power systems, power supplies for computer periphery and car auxiliary, and so on [1,2,3,4]. For instance, power electronic circuits (PECs), which are an integral part of any modern-day electrical vehicle, usually comprises DC–AC inverters and DC–DC converters. A DC–AC inverter caters to various utility loads, such as air-conditioning systems, whereas a DC–DC converter is used to supply conventional low-power, low-voltage loads such as sensors, controls, entertainment, utility, and safety equipment, etc. [5]. Secondly, most of the renewable energy resources (RERs) produce a DC voltage of a small magnitude. Thus, a high-step-up DC–DC converter can be used before interfacing RERs with the grid. Additionally, considering the growing number of DC loads in various applications such as microgrids and EVs, it preferred to have a DC distribution system including DC–DC converters than its AC counterpart [6,7,8].
In many such applications, DC–DC converters are required to provide a good output voltage regulation against load and line variations, as well as the circuit parameter uncertainties. Among them, the positive output Luo converters are a series of DC–DC converters which were developed from the prototype using the voltage-lift technique [9]. In the main series of Luo converters, the nth stage circuit has a single active switch, n inductors, 2n capacitors, and (3n−1) diodes. Then, the number of diodes and capacitors increase to 2(n+1) and (3n+1), respectively, for its enhanced series which provides further high gain [10]. The advantages of Luo converters over other existing converters include the reduced ripple in the output voltage as well as current, high-power density, the use of fewer switches which leads to reduced switching losses, and simple architecture [9,10,11,12].
Unlike the conventional boost converter, which has only two state variables available for feedback purposes, the newer higher-order converters such as the positive output elementary Luo (POEL) converter present certain challenges. Generally, a higher-order system requires a higher-order controller to meet the transient specifications. Nonetheless, the controller should be of a lower order to reduce the cost and for ease of implementation. The voltage-mode control and current-mode control are two widely used methodologies for regulating the output voltage in DC–DC converters. However, the POEL converter features a dynamic behavior similar to that of the conventional boost converter. As such, the non-minimum phase nature of its control to output transfer function makes it very difficult to design the controller using a single voltage loop. To overcome this problem occurring in boost-derived topologies, the current-mode control has been applied to many DC–DC converter topologies during the past few years [13,14,15]. However, even though it simplifies the feedback design and improves the current accuracy, it has a major limitation. Since the current-mode controller is based on the linearized models of DC–DC converters, the controller is valid only in the neighborhood of the specific operating point. To overcome this problem, a non-linear sliding-mode controller (SMC) has been proposed for the POEL converter [11]. In [12], the sliding-mode control technique and loop-shaping H approach are used together to design a robust dual-loop control for the POEL converter. However, its electronic implementation is rather complex and is based on the pulse width modulation (PWM), so there is also a risk of saturation. In [16], proportional-integral (PI) and sliding-mode controls are combined to regulate the fourth-order Cuk converter, but without presenting experimental results validating the approach. Another approach using the PWM-based double-integral sliding-mode control for the conventional boost converter and other higher-order DC–DC converters has been reported in [17,18,19]. Even though the use of an additional integral term alleviates the steady-state error of the system, its presence, however, increases the order of the controller and also demands the use of more state variables such as two or more currents for feedback [17,18]. Ideally, the least number of current variables should be used for feedback as their use demands a complex current sensing circuitry. A hysteresis-based sliding-mode controller for the cascade boost converter has been proposed in [20,21]. The main advantages offered by the hysteresis-based modulation are no risk of saturation when operating at high values of duty ratio and a fast dynamic response over a wide range of operating conditions [21]. The implementation of most of these state-of-the-art controllers discussed so far demands the inductor current sensor, which increases the cost and complexity of realization. The use of a non-linear output feedback controller for the traditional boost converter has been reported in [22]. In contrast to the conventional current-mode control, such an output feedback strategy is able to regulate the output voltage of the boost-type DC–DC converters without any inductor current feedback.
In this paper, a dynamic output voltage feedback controller is proposed to tackle the problem of regulating the output voltage of a POEL converter using the least number of state variables for feedback purposes. The proposed control strategy uses only the output voltage state variable for feedback purposes. Both proportional and integral actions are incorporated for improved performance of the proposed controller. The controller design is accompanied by a detailed stability analysis and the conditions for the stability and feasibility of the proposed controller are obtained. In contrast to [22], the performance of the proposed controller is compared with a dual-loop hysteresis-based sliding-mode-controller (SMC) to achieve the output voltage-regulation of the same converter parameters. The control scheme mainly consists of a dual-loop controller which is designed to achieve an indirect control of the output voltage via the input inductor current tracking. An inner loop controls the input inductor current, whose reference is modified at the output of a proportional-integral (PI) controller, processing the output voltage error. The theoretical derivation of an equivalent control, as well as the procedure to obtain the existence and stability conditions are discussed in detail. Finally, experimental results showing the features of both controllers are provided. The performance of these controllers is compared with basic criteria such as transient and steady-state response to the step-change in the reference voltage, as well as sensitivity to unknown loads. Additionally, particular emphasis is placed on the ease of implementation in terms of the number of state variables and current sensors required for implementation.

2. Average Model of the POEL Converter

Figure 1 shows the circuit diagram of the POEL converter. When the switch SW is ON, inductor L 1 absorbs energy from the source. At the same time, inductor L 2 obtains energy from the source as well as the capacitor C 1 . When the switch SW is OFF, capacitor C 1 becomes charged through the diode and inductor L 1 transfers its energy to C 1 [9].
The average state-space model of the POEL converter operating in the continuous mode is described as follows [12]:
d i L 1 d t = ( 1 u ) L 1 v C 1 + u E L 1
d i L 2 d t = u L 2 ( E + v C 1 ) 1 L 2 v C 2
d v C 1 d t = ( 1 u ) C 1 i L 1 u C 1 i L 2
d v C 2 d t = 1 C 2 i L 2 1 R C 2 v C 2
where i L 1 , i L 2 , v C 1 and v C 2 = v o are the average current of inductor L 1 , average current of inductor L 2 , average voltage of capacitor C 1 and average voltage of capacitor C 2 , respectively. The scalar u denotes the duty ratio, where 0 u 1 . From (1)–(4), the following equilibrium values are obtained:
I L 1 = V o 2 R E ,   I L 2 = V o R ,   V C 1 = V C 2 = V o ,   V o E = U 1 U
where   I L 1 , I L 2 , V C 1 , V C 2 = V o and U are the equilibrium values of i L 1 , i L 2 , v C 1 , v o , and u , respectively. Setting V C 2 at the desired voltage value V C 2 = V d gives the following desired constant values:
I L 1 = V d 2 R E ,   I L 2 = V d R ,   V C 1 = V d ,   V d E = U 1 U
From (6), the equilibrium value of the control signal u is given by
U = V d E + V d
The problem at hand is to find a suitable dynamic voltage feedback controller to regulate the output voltage of the POEL converter in the presence of an uncertain load.

3. Proposed Dynamic Output Voltage Feedback Controller

This section presents an output voltage feedback controller for the regulation of the POEL converter. The proposed controller structure is influenced by that of the controller for the conventional boost converter in [22]. Both proportional and integral actions are now employed for enhanced performance of the controller.

3.1. Proposed Control Law

The proposed dynamic output voltage feedback control law for the POEL converter can be described as follows:
u = 1 E + K p ( v o V d ) + K i ( v 0 ( τ ) V d ) d τ x d + E
d x d d t = 1 C 2 { ( K 1 + K 2 ) x d + K 2 v 0 + K 1 V d }
where K 1 , K 2 , K p , and K i are the controller gains specified by the designer. (8) is obtained from the expression of U in (7), i.e., u = 1 E ( x d + E ) , where x d is the solution of (9). Both integral and damping actions are now incorporated in u = 1 E ( x d + E ) to give (8).

3.2. Stability Analysis

To analyze the closed-loop system, the following error variables are defined:
e 1 = i L 1 V d 2 R E ,   e 2 = i L 2 V d R ,   e 3 = v C 1 V d ,   e 4 = v o V d
Using (8)–(10) in (1)–(4) yields the following set of equations:
e ˙ 1 = 1 L 1 ( E + K P e 4 + σ x d + E ) ( e 3 + V d ) + E L 1 ( x d K P e 4 σ x d + E )
e ˙ 2 = 1 L 2 ( x d K P e 4 σ x d + E ) ( e 3 + V d + E ) 1 L 2 ( e 4 + V d )
e ˙ 3 = 1 C 1 ( E + K P e 4 + σ x d + E ) ( e 1 + V d 2 R E ) 1 C 1 ( x d K P e 4 σ x d + E ) ( e 2 + V d R )
e ˙ 4 = 1 C 2 ( e 2 + V d R ) 1 R C 2 ( e 4 + V d )
x d ˙ = ( K 1 + K 2 ) C 2 x d + K 2 C 2 v 0 + K 1 V d C 2
σ ˙ = K i e 4
The equilibrium point of (11)–(16) can be obtained by equating them with zero. This equilibrium point is:
( e 1 , e 2 ,   e 3 ,   e 4 ,   x d ,   σ ) = (   0 ,   0 ,   0 ,   0 , V d ,   0   )
Now, linearizing (11)–(16) about the equilibrium point (17) yields the following system:
z ˙ = N z
where, z = [ z 1   z 2   z 3   z 4   z 5   z 6 ] T , and z 1 = e 1 e 1 ,   z 2 = e 2 e 2 ,   z 3 = e 3 e 3 ,     z 4 = e 4 e 4 ,     z 5 = x d x d ,   z 6 = σ σ  
N = [ 0 0 E L 1 ( V d + E ) K P L 1 E L 1 ( V d + E ) 1 L 1 0 0 V d L 2 ( V d + E ) ( 1 + K P ) L 2 2 E   L 2 ( V d + E ) 1 L 2 E C 1 ( V d + E ) V d C 1 ( V d + E ) 0 K P V d C 1 R E V d C 1 R ( V d + E ) V d C 1 R E 0 1 C 2 0 1 R C 2 0 0 0 0 0 K 2 C 2 ( K 1 + K 2 ) C 2 0 0 0 0 K i 0 0 ]
The stability analysis can now be performed by finding the eigenvalues of matrix N , i.e., the roots of | s I N | = 0 , where s is a complex variable. The system will be stable if, and only if, all eigenvalues lie in the open left-half complex plane. The root locus method can be used to analyze the system stability as shown below.
Consider the POEL converter with following circuit parameter values:
E = 5   V , V d = 10   V ,   L 1 = L 2 = 1   mH , C 1 = 100   μ F ,   C 2 = 100   μ F ,   R = 56   Ω
The characteristic polynomial | s I N | is thus given by
| s I N | = s 6 + ( 10 4 ( K 1 + K 2 ) + 178.5 ) s 5 + ( 178.5 × 10 4 ( K 1 + K 2 ) + 10 7 K P   + 1.5 × 10 7 ) s 4 + ( 1.5 × 10 11 K 1 + 8.8 × 10 10 K 2 + 1 × 10 7 K i 2.3 × 10 9 K P   + 10 11 K p   ( K 1 + K 2 ) + 9.9 × 10 8 ) s 3 + ( 9.9 × 10 12 K 1 + 1.78 × 10 13 K 2 2.3 × 10 9 K i + 3.3 × 10 13 K P   + 10 11 K i   ( K 1 + K 2 ) 2.3 × 10 13 K p   ( K 1 + K 2 ) + 1.1 × 10 13 ) s 2 + ( 1.1 × 10 17 K 1 3.70 × 10 16 K 2 + 3.3 × 10 13 K i 2.3 × 10 13 K i   ( K 1 + K 2 ) + 3.3 × 10 17 K p   ( K 1 + K 2 ) ) s + ( 3.3 × 10 17 K i   ( K 1 + K 2 ) )
Figure 2a shows the root locus plot for K 1 = 1 ,   K 2 = 1 ,   K P = 0.01 and 0 < K i < 15 and Figure 2b shows the root locus plot for K 1 = 1 ,   K 2 = 1 ,   K i = 5 and 0 < K p < 0.2 . The arrow shows how the poles are moving from K i = 0 and K p = 0 , respectively. The system is stable for all values of K i and K p in this range. More on the selection of controller gains will be illustrated in Section 4.

3.3. Feasibility of the Proposed Controller

Next, the feasibility of the proposed controller (8) and (9) for the POEL converter is demonstrated. The expressions for u ˙ and x d can be obtained from (8). Using (10) gives:
u ˙ = x d ˙ K p e 4 ˙ σ ˙ ( x d + E ) x d ˙ ( x d K p e 4 σ ) ( x d + E ) 2
x d = E u + K p e 4 + σ 1 u
Using (4), (9), (10), (16), (20) and (21) yields
d u d t = ( ( K 1 + K 2 ) C 2 { E u + K p e 4 + σ ( 1 u ) } + K 2 C 2 v 0 + K 1 C 2 V d ) K p { 1 C 2 i L 2 1 R C 2 v 0 } K i ( v o V d ) E u + K p ( v o V d ) + σ 1 u + E u ( ( K 1 + K 2 ) C 2 { E u + K p e 4 + σ ( 1 u ) } + K 2 C 2 v 0 + K 1 C 2 V d ) E u + K p ( v o V d ) + σ 1 u + E
Now, by letting i L 2 , v 0 , and σ coincide with their desired values, namely, i L 2 = V d R , v o = V d and σ = 0 , the ‘remaining dynamics’ can be obtained as:
d u d t = ( K 1 + K 2 ) ( V d + E ) C 2 E ( u 1 ) ( u V d V d + E )
Figure 3 shows the phase-plane diagram of (23) and the equilibrium points are given by
  u 1 = 1 ,   u 2 = V d V d + E
It is evident that   u 2 = V d ( V d + E ) is a locally stable equilibrium point whereas   u 1 = 1 is unstable. Additionally, u 1 = 1 corresponds to V d = . Thus, the proposed controller is stable for 0 u < 1 .
In summary, it can be stated that, the controller described by (8) and (9) with suitably chosen values of   K 1 ,   K 2 ,   K p , and K i such that the eigenvalues of matrix N lie in the open left-half complex plane, locally asymptotically stabilizes the POEL converter to the equilibrium point ( i ¯ L 1 ,   i ¯ L 2 , v ¯ C 1 , v ¯ C 2 ) = ( V d 2 R E , V d R , V d , V d ) for any 0 < R < .
Remark: It is worth noting that the proposed methodology to derive the structure of the output feedback controller is quite generic and thus, it can be easily extended to other types of DC–DC converters. The only point is that the exact controller structure may slightly vary for different types of dc-dc converters depending upon the expression of the open-loop duty ratio.

4. Empirical Approach of Selecting the Controller Gains

Since there are four controller gains associated with the proposed controller given by (8) and (9), it is required to know their effect on the output response. To relieve the difficulty of their design, computer simulations were carried out using PSim software to find the optimum values of the gains for controller implementation. Additionally, for simplicity, K 1 = K 2 is used. The converter parameter values as used in Section 3 will be used here as well.
First, the effect of K i is investigated. The analysis is carried out for K 1 = K 2 = 1 and K p = 0.01 . The integral gain is mainly introduced in the control law to reduce the output voltage steady state error. However, even though an increment in K i may improve the steady-state regulation, it is found that it also causes the response to become more oscillatory with a higher overshoot (see Figure 4a). As a result, the settling time increases with increase in K i . Additionally, since integral action is destabilizing, an increment in K i above a certain value leads to instability. The root locus method can be used to find the maximum value of K i , as was performed in Section 3 (see Figure 2a). For K p = 0.01 , the poles move to the right hand side (R.H.S.) of the s-plane for K i 19 . However, when K p is increased to 0.1, the range of stability for K i increases to 0 < K i < 26 as shown in Figure 5. Thus, the range of stability for K i increases with the increase in K p value.
Next, the effect of K p is investigated. An increment in K p reduces the steady-state oscillations and also reduces the settling time as shown in Figure 4b. However, the range of stability for K p is very small. For K 1 = K 2 = 1 and K i = 1 , system is stable for K p 0.2 (see Figure 2b).
Based on these observations, a heuristic but practical approach is chosen for the controller gain design. First, the values of K 1 and K 2 are fixed at 1. Then, an arbitrary low value of K i and a high value of K p are chosen. As in traditional controllers, such tuning of controller gains is necessary in the initial prototype stage to attain the desired response after the implementation of the controller.

5. Hysteresis-Based Sliding Mode Controller

In this section, a hysteresis-based sliding-mode controller for the POEL converter is presented. The detailed analysis provided helps give good insight into the behavior of the sliding-mode controlled POEL converter. The control scheme is shown in Figure 6.

5.1. Sliding Surface and Its Equivalent Control Law

The proposed sliding surface for the POEL converter defined using its input inductor current is given as:
s ( x ) = i L 1 I r e f ( t )  
where i L 1 is the average value of the current flowing through inductor L 1 and I r e f ( t ) is the reference inductor current trajectory generated at the output of the PI compensator processing the output voltage error. It is given by
  I r e f ( t ) = K p s ( V d v C 2 ( t ) ) + K I s ( V d v C 2 ( τ ) ) d τ
The sliding motion can then be defined using the switching function u s which can be expressed as below:
u s = 0   w h e n   s ( x ) > 0 u s = 1   w h e n   s ( x ) < 0
For the successful operation of the sliding-mode control action to occur, an existence condition must be satisfied. The fulfillment of the existence condition confirms that the state trajectory in the neighborhood of the sliding surface will always be directed towards the sliding surface. Therefore, evaluating lim s 0 s ( x ) s ˙ ( x ) < 0   , and using (25) and (27) gives the necessary existence condition as:
v C 1 < L 1 d I r e f d t < E
Next, equating s ˙ = 0 and using ( 1 ) and (25), the equivalent control signal can be obtained as:
u s e q = 1 v C 1 + E ( v C 1 + L 1 d I r e f   ( t ) d t ) = 1 1 v C 1 + E ( E L 1 d I r e f   ( t ) d t )
where   u s e q is continuous and 0 < u s e q < 1 should be satisfied.

5.2. Ideal Sliding Dynamics and Linearized Model

Now, substituting (29) into (2)–(4) yields the following ideal sliding dynamics of the converter:
d i L 2 d t = 1 L 2 ( v C 1 + L 1 d I r e f   ( t ) d t ) 1 L 2 v C 2
d v C 1 d t = 1 v C 1 + E ( E L 1 d I r e f   ( t ) d t ) i L 1 C 1 1 v C 1 + E ( v C 1 + L 1 d I r e f   ( t ) d t ) i L 2 C 1
d v C 2 d t = i L 2 C 2 1 R C 2 v C 2
Assuming that i L 1   has the constant value I r e f , the equilibrium point of (30)–(32) is given by
I L 1 = I r e f ,   I L 2 = I r e f E R   ,   V C 1 = I r e f E   R ,   V C 2 = I r e f E R
Linearizing (30)–(32) about equilibrium point (33) and considering only the AC terms gives the following linearized system representing the current loop:
  x 1 ˜ ˙ = A x 1 ˜ + B k ˜ + E d k ˜ d t y ˜ = C x 1 ˜
where k ˜ = I ˜ r e f is the linearized system input, x 1 ˜ represents the small signal variations in the state variables, i.e., x 1 ˜ = [   i ˜ L 2 v ˜ c 1   v ˜ c 2 ] T and y ˜ = [   v ˜ c 2   ] is the corresponding output. Matrices A , B , E   a n d   C are given by
A = [ 0   1 L 2 1 L 2   V C 2 C 1 ( V C 2 + E ) V C 2 C 1 R ( V C 2 + E )   0   1 C 2   0 1 R C 2   ] , B = [ 0   E C 1 ( V C 2 + E )   0   ] ,   E = [ L 1 L 2 L 1 V C 2 C 1 R E   0   ] ,   C = [ 0   0   1   ]
Now, the transfer function of the current loop v ˜ c 2 ( s ) I ˜ r e f ( s ) can be obtained from the state-space model (34) and is given by:
G c l ( s ) = v ˜ c 2 ( s ) I ˜ r e f ( s ) = q ( s ) p ( s ) = a 2 s 2 + a 1 s + a 0 b 3 s 3 + b 2 s 2 + b 1   s + b 0
where the small ac perturbations are represented by “~” and
a 2 = L 1 C 2 L 2 ,   a 1 = V C 2 C 1 C 2 R [ L 1 L 2 ( E + V C 2 ) 1 ] , a 0 = E C 1 C 2 L 2 ( E + V C 2 ) b 3 = 1 , b 2 = 1 C 2 R + V C 2 C 1 R ( E + V C 2 ) ,   b 1 = V C 2 C 1 C 2 R 2 ( E + V C 2 ) + 1 C 2 L 2 + V C 2 C 1 L 2 ( E + V C 2 ) , b 0 = 2 . V C 2 C 1 C 2 L 2 R ( E + V C 2 )

5.3. Voltage Loop Analysis

Next, the PI controller for the voltage loop is considered, and its form is given by:
G v ( s ) = K p s + K I s s
After introducing this PI controller in the control scheme as shown in Figure 6, the voltage loop transfer function G c v ( s ) = v ˜ c 2 ( s ) v ˜ r e f ( s ) is given by:
G c v ( s ) = v ˜ c 2 ( s ) v ˜ r e f ( s ) = G c l ( s ) G v ( s ) 1 + G c l ( s ) G v ( s )
Substituting (35) and (37) into (38) yields the following transfer function:
G c v ( s ) = v ˜ c 2 ( s ) v ˜ r e f ( s ) = ( K p s · s + K I s ) q ( s ) p ( s ) · s + ( K p s · s + K I s ) q ( s )
The corresponding characteristic equation is given by
c ( s ) = p ( s ) · s + ( K p s · s + K I s ) q ( s ) = 0
Using p ( s ) = b 3 s 3 + b 2 s 2 + b 1   s + b 0 and q ( s ) = a 2 s 2 + a 1 s + a 0 , the characteristic equation can be obtained as:
c ( s ) = c 4 s 4 + c 3 s 3 + c 2 s 2 + c 1   s + c 0
where c 4 = b 3 = 1   , c 3 = b 2 + K p s a 2 , c 2 = b 1 + K p s a 1 + K I s a 2 , c 1 = b o + K p s a 0 + K I s a 1 , c 0 = K I s a 0 .
Now, by applying the Routh–Hurwitz stability criteria to the characteristic polynomial (41), the closed-loop system will be stable if, and only if, the following conditions are satisfied:
  c 0 > 0 ,   c 3 > 0 ,   c 3 c 2 > c 1 c 4 ,   c 1 c 2 c 3 c 1 2 c 4 c o c 3 2 > 0
Thus, the PI compensator can be designed to satisfy the above condition given the converter specifications and the satisfaction of the existence condition (28).

6. Experimental Results and Discussions

An experimental setup of the POEL converter system was built to test the effectiveness of the proposed control strategies. The set of converter parameters used in Section 3 and Section 4 will be used here as well.

6.1. Voltage-Based Feedback Controller

The proposed dynamic output voltage-feedback controller (8) and (9) was implemented using simple analog components. The block diagram and experimental set-up of the controller are shown in Figure 7a,b, respectively. For implementation purposes, a voltage feedback factor β was used and the modified control law is written as follows:
u = 1 E s + K p ( v o s V d s ) + K i ( v 0 s V d s ) d τ x d s + E s
d x d s d t = 1 C 2 { ( K 1 + K 2 ) x d s + K 2 v 0 s + K 1 V d s }
where E s = β E , V d s = β V d , v o s = β v o , x d s = β x d and 0 < β < 1 is imposed. The voltage feedback factor was set as β = 1 10 . The division function was implemented using the AD633 chip. The controller gains of the proposed voltage-feedback controller were chosen as K 1 = K 2 = 1 ,   K p = 0.01 and K i = 1 .
Figure 8a shows the transient response of the system when a step reference voltage,   V d = 10   V was applied. A good output tracking was obtained with little overshoot and settling time of ~0.5 s. Figure 8b shows the corresponding control signal. Next, the ability of the proposed controller to handle the load disturbances is evaluated. Figure 8c shows the output response in the presence of load change from R = 56   Ω to R = 112   Ω ( 100 % increase) and then back to R = 56   Ω . Figure 8d shows the output response in the presence of load change from R = 56   Ω to R = 145   Ω ( 160 % increase) and then back to R = 56   Ω . The disturbances are rejected in around 1 s with a maximum voltage deviation of ~ 1.5   V . Figure 9a shows the response to a step change in the reference voltage from   V d = 5   V to V d = 10   V and then back to V d = 5   V . A slight output ripple is observed at the steady state, with little or no overshoot. Figure 9b shows the inductor current i L 1 during start-up.

6.2. Hysteresis-Based Sliding-Mode Controller

The controller of the form (25) and (26) was implemented using simple devices with the following modification:
u s = 0   w h e n   s ( x ) > δ u s = 1   w h e n   s ( x ) < δ
Such a modification is required because an implementation of an ideal comparator demands the use of an infinite switching frequency which is quite impossible considering the inherent limitation of the power devices to operate at such a high frequency. Additionally, an ideal comparator may produce false switching signals in case noisy input signals are present. Considering this, the limits of the hysteresis band were set as I r e f + δ and I r e f δ where a value of δ = 0.1   V was selected. Figure 10a shows the output response of the converter when a step reference voltage V d = 10   V was applied. Here, K p s = 2 and K I s = 100 were used. It should be noted that the settling time is now reduced to ~0.1 s as compared to ~0.5 s needed in Figure 8a. This improvement in the settling time can be attributed to the use of a faster current loop in the sliding-mode controller. Figure 10b,c show the output responses in the presence of a load change from R = 56   Ω to R = 112   Ω ( 100 % increase) and R = 56   Ω to R = 145   Ω ( 160 % increase), respectively. It is observed that these disturbances produce a maximum overshoot of ~2V which is rejected in less than 0.1 s in the worst case. Figure 10d shows the output response in the presence of a reference voltage change from V d = 5   V to V d = 10   V and then back to V d = 5   V .

7. Conclusions

In this paper, the problem of regulating the POEL converter using the least number of state variables for feedback was addressed. To this end, a novel voltage-mode controller is proposed for the output voltage regulation. It can be concluded that even though the dynamic output voltage feedback controller is designed using only one state variable feedback, the controller demonstrates good tracking properties over a wide range of operating conditions with a negligible overshoot. The performance of the proposed controller is compared with a widely used hysteresis-modulation based sliding-mode controller. It was observed that the sliding-mode control leads to a better transient response of the system. However, it requires an additional current sensor which may increase the cost and complexity of implementation. Moreover, a variable frequency is needed for the implementation of a sliding-mode controller. In contrast to this, the proposed controller only requires output voltage feedback, which eliminates the need for a current sensor. Additionally, it uses a constant switching frequency. In general, it can be stated that there is a trade-off between the number of state variables used for the implementation, and the quality of the output transient response in the presence of load and reference voltage variations. As such a suitable control scheme must be chosen as per the demands of the application.

Author Contributions

Conceptualization, S.H.C.; methodology, S.H.C.; software, S.H.C.; validation, S.H.C.; formal analysis, S.H.C.; investigation, S.H.C.; resources, S.H.C.; writing—original draft preparation, S.H.C.; writing—review and editing, S.HC. and S.V.M.; supervision, S.L.P. All authors have read and agreed to the published version of the manuscript.

Funding

The research received no external funding.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Circuit diagram of the POEL Converter.
Figure 1. Circuit diagram of the POEL Converter.
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Figure 2. Root locus plot of closed loop characteristics equation. (a) Root locus for varying K i when K 1 = 1 ,   K 2 = 1 ,   K P = 0.01 , and 0 < K i < 15 ; (b) Root locus for varying K p when K 1 = 1 ,   K 2 = 1 ,   K i = 5 and 0 < K p < 0.2 .
Figure 2. Root locus plot of closed loop characteristics equation. (a) Root locus for varying K i when K 1 = 1 ,   K 2 = 1 ,   K P = 0.01 , and 0 < K i < 15 ; (b) Root locus for varying K p when K 1 = 1 ,   K 2 = 1 ,   K i = 5 and 0 < K p < 0.2 .
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Figure 3. Remaining dynamics of the voltage-controller converter.
Figure 3. Remaining dynamics of the voltage-controller converter.
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Figure 4. Output response for varying controller gains. (a) Output response for varying K i ; (b) Output response for varying K p .
Figure 4. Output response for varying controller gains. (a) Output response for varying K i ; (b) Output response for varying K p .
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Figure 5. Root locus plot of closed loop characteristics equation. (a) 0 < K i 19 ,   K p = 0.01 ; (b) 0 < K i 26 ,   K p = 0.1 .
Figure 5. Root locus plot of closed loop characteristics equation. (a) 0 < K i 19 ,   K p = 0.01 ; (b) 0 < K i 26 ,   K p = 0.1 .
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Figure 6. A dual-loop sliding-mode control scheme.
Figure 6. A dual-loop sliding-mode control scheme.
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Figure 7. Control schemes for POEL converter. (a) Block diagram of voltage-based feedback controller; (b) Experimental set-up.
Figure 7. Control schemes for POEL converter. (a) Block diagram of voltage-based feedback controller; (b) Experimental set-up.
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Figure 8. System response (a) Transient output response ( V d = 0   V to V d = 10   V ); (b) Control signal for transient output response; (c) Output voltage in the presence of load change from R = 56   Ω to R = 112   Ω and then back to R = 56   Ω ; (d) Output voltage in the presence of load change from R = 56   Ω to R = 145   Ω and then back to R = 56   Ω .
Figure 8. System response (a) Transient output response ( V d = 0   V to V d = 10   V ); (b) Control signal for transient output response; (c) Output voltage in the presence of load change from R = 56   Ω to R = 112   Ω and then back to R = 56   Ω ; (d) Output voltage in the presence of load change from R = 56   Ω to R = 145   Ω and then back to R = 56   Ω .
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Figure 9. System response, (a) Step change in the reference voltage from   V d = 5   V to V d = 10   V ; (b) Inductor current i L 1 waveform.
Figure 9. System response, (a) Step change in the reference voltage from   V d = 5   V to V d = 10   V ; (b) Inductor current i L 1 waveform.
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Figure 10. System responses of the sliding-mode controlled system, (a) Transient output response for   V d = 10   V ; (b) Output response when R = 56   Ω was changed to R = 112   Ω and then back to R = 56   Ω ; (c) Output response when R = 56   Ω was changed to R = 145   Ω and then back to R = 56   Ω ; (d) Output response when the reference voltage was changed from   V d = 5   V to V d = 10   V .
Figure 10. System responses of the sliding-mode controlled system, (a) Transient output response for   V d = 10   V ; (b) Output response when R = 56   Ω was changed to R = 112   Ω and then back to R = 56   Ω ; (c) Output response when R = 56   Ω was changed to R = 145   Ω and then back to R = 56   Ω ; (d) Output response when the reference voltage was changed from   V d = 5   V to V d = 10   V .
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Chincholkar, S.H.; Malge, S.V.; Patil, S.L. Design and Analysis of a Voltage-Mode Non-Linear Control of a Non-Minimum-Phase Positive Output Elementary Luo Converter. Electronics 2022, 11, 207. https://doi.org/10.3390/electronics11020207

AMA Style

Chincholkar SH, Malge SV, Patil SL. Design and Analysis of a Voltage-Mode Non-Linear Control of a Non-Minimum-Phase Positive Output Elementary Luo Converter. Electronics. 2022; 11(2):207. https://doi.org/10.3390/electronics11020207

Chicago/Turabian Style

Chincholkar, Satyajit H., Sangmesh V. Malge, and Sanjaykumar L. Patil. 2022. "Design and Analysis of a Voltage-Mode Non-Linear Control of a Non-Minimum-Phase Positive Output Elementary Luo Converter" Electronics 11, no. 2: 207. https://doi.org/10.3390/electronics11020207

APA Style

Chincholkar, S. H., Malge, S. V., & Patil, S. L. (2022). Design and Analysis of a Voltage-Mode Non-Linear Control of a Non-Minimum-Phase Positive Output Elementary Luo Converter. Electronics, 11(2), 207. https://doi.org/10.3390/electronics11020207

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