A Design of a Thermoelectric Energy Harvester for Minimizing Sensor Module Cost

Abstract

This paper discusses a relationship between thermoelectric generator (TEG) electrical parameters, power efficiency of converters, and power consumption of loads in autonomous sensor modules. Based on the method discussed, one can determine the total number of TEG units together with the number of TEG arrays and the number of TEG units connected in series per array when the characteristics of TEG unit, the minimum temperature difference in operation, the power conversion efficiency of the converter and the load condition are given. A practical design flow to minimize TEG cost is proposed and demonstrated, taking the maximum open circuit voltage of TEG and the dependence of the power conversion efficiency of the converter on the input voltage of the converter into consideration. The entire system including TEG and a Dickson charge pump converter, which were designed through the proposed flow, was validated with SPICE.

1. Introduction

A thermoelectric generator (TEG) is a device generating electric power based on temperature differences, which is known as the Seebeck effect [1,2,3]. A TEG is a key device for energy harvesting among many alternatives such as photovoltaic generators and electrostatic, electromagnetic, magnetostrictive or piezoelectric vibration devices [4]. Given that a nominal TEG can only generate an output voltage on an order of 10–100 mV with a few K temperature difference, a power converter is needed to operate integrated circuits (ICs) including sensor and RF at a higher voltages such as 3 V in autonomous sensor modules [5,6,7,8,9], as shown in Figure 1, where V_OC (R_TEG) is the open circuit voltage (output resistance) of TEG, η is the power conversion efficiency of the converter, and V_PP (I_PP, P_OUT) is the output voltage (average output current, average output power) of the converter to drive sensor and RF blocks.

Characteristics of the output current (I_OP) and voltage (V_OP) of TEGs are described in Figure 2a with an equivalent circuit with V_OC and R_TEG as shown in Figure 2b, where I_SC is the short circuit current of the TEG and P_IN is the output power of the TEG or the input power of the converter.

As a result, P_IN is described by a parabola where the peak power is given at the interface voltage V_OP = V_OC/2. Based on the equivalent circuit of a TEG system as shown in Figure 2b, the converter is designed to operate TEG at the maximum power point with a given I_OP-V_OP characteristic of TEG [10,11]. When TEG cannot operate at the maximum power point due to low input voltage, the converter needs to control the input voltage as well as the output voltage [12]. Once the application is determined, the required output current of the converter (I_PP) can be estimated by using (1),

I_PP = (I_PPA T_A + I_PPS T_S)/T_C

(1)

where I_PPA, T_A, I_PPS, T_S, and T_C are an average current in operation, an operation period per sense and data transmission, an average stand-by current, a stand-by period, and a cycle time per operation, respectively, as shown in Figure 1. Note that a rechargeable battery or a large capacitor is usually connected at the input terminal of the loading device to stabilize the input voltage of the sensor/RF IC against large I_PPA. Figure 3 shows the average power as a function of T_C in case of V_PP of 3 V, I_PPS of 1 μA, I_PPA of 10 mA, a bit rate of 1 Mbps, and 1 k-bytes/packet with Bluetooth low energy [13]. At a duty of 10⁻⁴ or lower, I_PP can be as low as 10 μW. Thus, the requirement for the output power of the converter is determined. From a system viewpoint, one may want to design a TEG structure in such a way that the output power of the converter is maximized under a given load condition.

Table 1. Electrical parameters depending on TEG array structure.

	NS × NP	TEG Array Structure	VOC	RTEG	ISC
(a)	8 × 1		8	8	1
(b)	4 × 2		4	2	2

illustrates a TEG composed of multiple pairs of n- and p-type thermocouples (TC). N_S (N_P) is the number of TCs connected in series (parallel). In this example, 8 TCs are connected in series (a) or arranged with two arrays of 4 TCs serially connected (b). The former configuration has higher V_OC and larger R_TEG than the latter does, as shown by (a) and (b) of Figure 4.

Thus, even though the area is given, one has a degree of freedom in a combination of N_S and N_P while the multiple of them is constant. In [14], a design technique was proposed to extract the maximum power over a wide V_OC range in case of a lack of converter by varying a combination of N_S and N_P. However, to the author’s knowledge, there have been no design considerations for TEG with converters under given load conditions in the literature to answer the question of how one can determine N_S and N_P under given system conditions. For example, as shown in Figure 4, the operating point given by the cross point of the V_OP − I_OP curves for the TEG and the converter depends on the slope of the V_OP − I_OP curve for the converter of smaller (c) or larger (d) than −1. Since TEG is one of the most significant devices in terms of sensor module cost, its size or area must be minimized to enable massively distributed sensor modules.

This paper discusses a relationship between TEG electrical parameters, power efficiency of the converter, and power of the load toward minimizing TEG cost. How V_OC or R_TEG should be determined is shown. In addition, a design flow is proposed to minimize TEG area when the load condition is given, a Dickson charge pump (CP) [15] as converter is used to be integrated in the sensor, with an RF chip as a cost-effective solution.

2. Equations between TEG, Converter, and Load

By definition, as described in Figure 1,

P_OUT = η P_IN

(2)

To extract power from TEG as much as possible, the converter needs to be operated to match the input impedance of the converter with the output impedance of TEG for impedance matching, as illustrated in Figure 2b. Under the maximum-output-power condition, P_IN is given by (3).

P_IN = (V_OC/2)²/R_TEG

(3)

From (2) and (3), TEG device parameters and circuit parameters are related by (4).

V_OC²/R_TEG = 4 V_PP I_PP/η

(4)

V_OC is proportional to ΔT [2]. V_OC and R_TEG can be varied proportionally by changing TEG structure as described in Table 1. As a result, when specific TCs are characterized, V_OC and R_TEG are related as in (5).

V_OC = N_S V_TC, R_TEG = N_S/N_P R_TC

(5)

where V_TC and R_TC are an open circuit voltage and an output impedance of a TC, respectively. The area of TEG can be estimated by the area of TC (A_TC) from (5),

A_TEG = N_S N_P A_TC = (V_OC²/R_TEG)/(V_TC²/R_TC) A_TC

(6)

V_OC can be also shown with R_TEG, instead of N_S from (5), as below.

V_OC = (V_TC/R_TC) N_P R_TEG

(7)

Finally, TEG with minimum area and the maximum operating point are determined by the filled circle rather than the blank one on the curve (c) or (d) in Figure 4, depending on the converter characteristic with a slope of <−1 or >−1. A trajectory of the maximum power point of TEG with a given area on log(I_OP) − log(V_OP) plane has a slope of −1. The trajectory of smaller TEG becomes closer to the origin. When the converter has a slope of <−1 as described by the curve (c) in Figure 4, the maximum power point is located at a relatively higher V_OP and a relatively lower I_OP than the case of using a converter whose slope is greater than −1.

Several conditions for TEG design are studied as follows. When the TEG area and structure are given, V_OC can be varied only by increasing ΔT. The minimum ΔT is determined by (4). V_OC depends on the square root of V_PP, I_PP, R_TEG, and η. Among them, V_PP and η are expected to not change significantly, at least in a short term. Figure 5 shows V_OC vs. η with I_PP = 30 μA or 3 μA and R_TEG = 300 Ω or 1 kΩ at V_PP = 3 V based on (4). When η is nominally 50%, an improvement in η by 10% only gives 10% reduction in V_OC. Similar goes to V_PP. As a result, it is considered that V_PP and η are not effective design parameters to mitigate the requirement for reducing V_OC.

On the other hand, when applications allow 10X longer cycle time as shown in Figure 3, the required V_OC can be significantly reduced, resulting in reduction in TEG cost with reduced N_S. Next, let’s look at the relationship between V_OC and R_TEG when η and the load condition are assumed. Figure 6 shows V_OC vs. R_TEG with different I_PP, η = 0.5, V_PP = 3 V, based on (4). If R_TEG needs to increase for small form factor by a factor of 10, V_OC has to increase by a factor of 3.2. Alternately, if T_C can be relaxed by a factor of 10 by reducing the frequency of sense and data transmission to 1/10 in a certain application, I_PP can decrease by a factor of 10, which allows the system to work with V_OC unchanged.

How can one determine R_TEG when V_OC is limited by the minimum operation voltage of the converter V_DD^MIN? Figure 7 shows R_TEG vs. I_PP with V_OC = 0.4 V or 0.8 V, η = 0.5, V_PP = 3 V. Even if V_DD^MIN of the converter can be reduced from V_OP = V_OC/2 = 0.4 V in case of V_OC = 0.8 V to V_OP = 0.2 V with converter designers’ effort, R_TEG also has to be reduced by a factor of 4 with the same ΔT and I_PP, or I_PP also has to be reduced by a factor of 4 with the same ΔT and R_TEG, instead. Thus, the effort of improving the converter with respect to reduction in V_DD^MIN requires more effort of reducing R_TEG for TEG designers or of reducing I_PP for system designers.

Figure 8 shows a relationship between (4) and (7). The cross points of them express the values of R_TEG and V_OC for a given condition of V_TC/R_TC = 0.45 mA, I_PP =30 μA, η = 0.5, V_PP = 3 V. Given that η is assumed to be constant over V_OP for simplicity in this section, one cannot determine N_S and N_P to minimize TEG area. Therefore, in order to design TEG with minimum cost, a converter needs to be optimally designed by V_OP precisely.

3. Design Flow of TEG with Minimum Area

In the above section II, η was assumed to be constant to overview the relationship between TEG electrical characteristics, converter power efficiency, and the load condition of the sensor module. In this section, a more practical design flow is proposed to determine both N_S and N_P of TEG and the design parameters of CP whose η can vary as V_OP at the same time.

(Assumption) The following parameters are given: V_TC, R_TC, and the target I_{PP_TGT} at V_PP.

(Parameters to be determined) N_S, N_P, in such a way that TEG area, i.e., the product N_S N_P, is minimum, as well as the number of stage N_CP, capacitance per stage C_CP and clock frequency f_CP to design CP.

(Step 1) Design CP with the maximum power conversion efficiency for each V_OP when the target I_PP is given at a specific V_PP, based on [16] as below.

It is assumed that (1) CP to be designed is a Dickson type [15], (2) it operates in slow switching limit (SSL) where the clock frequency is low enough to transfer the charges from one stage to the next one through a switching MOSFET in the subthreshold region or namely a switching diode, a unit of the diode has a voltage(V_D)–current(I_D) relationship specified by (8), and the oscillator cell consumes much lower power than the CP. Design flow in fast switching limit is open for the future work.

$$I_D=I_S{e}^{V_D/V_T}$$

(8)

The output voltage(V_OUT)–current(I_OUT) relationship of the CP is given by (9) where the output impedance R_PMP and the maximum attainable voltage V_MAX are given by (10) and (11), respectively. The top plate parasitic capacitance ${\alpha }_T$is assumed to be given by (12), where N_D, A_D, and C_J are the number of unit diodes, the junction area of a unit diode, and the junction capacitance of a unit diode. V_TH^EFF is an effective threshold voltage given by (13) [17], which is defined by the voltage difference between the adjacent capacitors at the negative clock edge, indicating the voltage loss per stage.

$$I_{OUT}=(V_{MAX}-V_{OUT})/R_{PMP}$$

(9)

$$R_{PMP}=\frac{N_{CP}}{f_{CP}{C}_{CP}\left(1+{\alpha }_T\right)}$$

(10)

$$V_{MAX}=\left(\frac{N_{CP}}{1+{\alpha }_T}+1\right)V_{OP}-\left(N_{CP}+1\right)V_{TH}{}^{EFF}$$

(11)

$${\alpha }_T=N_D{A}_D{C}_J/C_{CP}$$

(12)

$$V_{TH}{}^{EFF}=V_T\ln (4^{\frac{1}{N_{CP}+1}}\frac{\left(1+{\alpha }_T\right)f_{CP}{C}_{CP}{V}_T}{N_D{A}_D{I}_S})+\frac{N_{D{A}_D}{I}_S}{2f_{CP}{C}_{CP}\left(1+{\alpha }_T\right)}$$

(13)

The input current I_OP of the CP is given by (14) as a function of the output current I_PP and the input voltage V_OP. The last term comes from the reverse leakage of switching diodes.

$$I_{OP}=\left(\frac{N_{CP}}{1+{\alpha }_T}+1\right)I_{PP}+\left(\frac{{\alpha }_T}{1+{\alpha }_T}+{\alpha }_B\right)N_{CP}{f}_{CP}{C}_{CP}{V}_{OP}+\frac{N_{CP}{N}_{D{A}_D}{I}_S}{2}$$

(14)

The power conversion efficiency is defined by (15).

$$\eta =\frac{V_{PP}{I}_{PP}}{V_{OP}{I}_{OP}}$$

(15)

The optimum number of stages N_OPT to maximize the power efficiency is estimated by (16) using the minimum number of stages to output V_PP with zero output current given by (17) [18,19], where [X] indicates a rounded integer number of X.

$$N_{OPT}=\left[1.4N_{MIN}\right]$$

(16)

$$N_{MIN}=\frac{V_{PP}-V_{OP}+V_{TH}{}^{EFF}}{V_{OP}/\left(1+{\alpha }_T\right)-V_{TH}{}^{EFF}}$$

(17)

CP design flow starts with an initial condition on the target I_{PP_TGT} at V_PP, V_OP, CP area A_CP^INIT. I_PP and V_PP are specified by the loading devices such as sensor and RF ICs. The goal is determining the TEG configuration and the circuit parameters of the CP such that TEG and CP areas are minimized.

Consequently, N_D and V_TH^EFF are treated as variables. One can calculate the flowing parameters step by step: N_MIN by (17), N_OPT by (16), C_CP by (18), and ${\alpha }_T$by (12). It is assumed in (18) that the CP area is occupied by the capacitors and switching diodes, where C_OX is the capacitance density of each capacitor.

$$C_{CP}=\left(A_{CP}{}^{INIT}/N_{OPT}-\left(1+1/N_{OPT}\right)N_D{A}_D\right)C_{OX}$$

(18)

One can numerically solve (13) for f_CP because the remaining parameters are determined. From (10) and (11), R_PMP and V_MAX are calculated. Then, I_PP is determined by (19).

$$I_{PP}=(V_{MAX}-V_{PP})/R_{PMP}$$

(19)

When I_PP is not equal to I_{PP_TGT}, C_CP and N_D need to be scaled up or down by the scaling factor S_F given by (20). When both C_CP and N_D are scaled proportionally, the optimum f_CP can stay the same value because (13) has C_CP and N_D only as their ratio. Thus, the required CP area to output I_{PP_TGT} at V_PP is determined by (21).

$$S_F=I_{PP\_TGT}/I_{PP}$$

(20)

$$A_{CP}=S_F{A}_{CP}{}^{INIT}$$

(21)

This flow can be done with various combinations of V_TH^EFF and N_D. One can determine the best combination of all the CP parameters such as V_TH^EFF, N_D, N_CP, C_CP, and f_CP to have the maximum η for a given V_OP. One then needs to repeat the above procedure for various V_OP. The resultant V_OP − I_OP and V_OP − A_CP curves will be used together with those for TEG to determine the target configurations of TEG and CP with minimum areas as presented below.

(Step 2)

2-1: When V_OP < V_{OC_MAX}/2 where V_{OC_MAX} is V_OC with N_P = 1, find the operating point (V_OP, I_OP) in such a way that V_OC = 2 V_OP and R_TEG = V_OP/(2 I_OP) which meets the maximum power condition (3), as shown by the line (a) in Figure 9.

Hence, one can determine

N_S = 2 V_OP/V_TC, N_P = 4 R_TCI_OP/V_TC

(22)

Then, A_TEG is estimated by (23), based on (6).

A_TEG = (8 V_OPI_OP)/(V_TC²/R_TC) A_TC

(23)

2-2: When V_OP > V_{OC_MAX}/2, one cannot design TEG to run at the maximum operating point even with N_P = 1, as shown by the line (b) in Figure 9. Instead, TEG needs to have the following parameters:

V_OC = V_{OC_MAX} = N_S V_TC, R_TEG = (V_{OC_MAX} − V_OP)/I_OP

(24)

Then, A_TEG is estimated by (25), based on (6).

A_TEG = (V_{OC_MAX}/V_TC) A_TC

(25)

where N_S and N_P are given by (26).

N_S = 2 V_OP/V_TC, N_P = 1

(26)

(Step 3) Find V_OP to minimize A_TEG among the values found in Step 2 in the V_OP range. One can also determine the design parameters of CP such as N_CP, C_CP, and f_CP at the same time.

Let’s see how the above flow works using the parameters in

Table 2. Design and device parameters for demonstration.

Parameter	Symbol	Value
Output voltage of CP	VPP [V]	3.0
Output target current of CP	IPP_TGT [μA]	30
Thermal voltage of switching diodes	VT [mV]	25
Saturation current density of the diodes	IS [nA/μm2]	0.1
Junction capacitance density of the diodes	CJ [fF/μm2]	3.5
Capacitance density of CP capacitors	COX [fF/μm2]	10
Junction area of a unit diode	AD [μm2]	10
Bottom plate parasitic cap ratio to the CP cap	αB [a.u.]	0.1

, which were presented in [16], for demonstration.

Figure 10a–e show η vs. CP area when V_TH^EFF is varied between 0.02 V and 0.15 V and N_D is varied among 10, 30, 100, 300, 1000 at V_OP of 1.25 V in (a) through 0.25 V in (e), respectively. In this work, η is the highest priority, but a very strict constraint could need too large a CP area. Considering a trade-off between η and CP area, the best combination of the CP design parameters is determined, in order to have 2% lower η than its peak value, which is shown by an arrow in each figure. There were two groups in Figure 10b. One has η > 0.55 and the other has η < 0.5. The former has N_CP of three whereas the latter has N_CP of four. As V_OP decreases, the number of groups with different numbers of N_CP increases. Smooth variations on η—CP area curves come from variations in V_TH^EFF or N_D while N_CP is unchanged.

Figure 11 show how smooth the functions of η, f_CP, CP area over N_D and V_TH^EFF are when V_OP is 0.25 V. V_TH^EFF is 0.03 V in Figure 11a–c. N_D is 30 in Figure 11d–f. The arrows in Figure 11a,c indicate the optimum design plotted in Figure 10e. As N_D increases, CP can run faster to keep V_TH^EFF, as shown in Figure 11b. To obtain a target output current at a target output voltage, capacitors can be scaled with f_CP in SSL, resulting in scaled CP area with larger N_D, as shown in Figure 11c. Faster operation increases the current for top and bottom parasitic capacitances, resulting in less power efficiency, as shown in Figure 11a. Similar tendencies are valid for the sensitivities of η, f_CP, CP area on V_TH^EFF. To reduce the voltage difference between the next neighbor stages at the falling edge, f_CP needs to be lower, as shown in Figure 11e. As a result, η and CP area decreases as V_TH^EFF increases, as shown in Figure 11d,f, respectively.

Figure 12a shows the relative design parameter values normalized by the values at Vop = 0.75 V, which are N_D = 300, N_CP = 5, C_CP = 1.1 nF, f_CP = 113 kHz, α_T = 2.9 %, V_TH^EFF = 40 mV, A_CP = 0.62 mm², I_OP = 240 μA, η = 0.50. Capacitance per stage and CP area have strong Vop dependence except for the glitches at Vop = 1.0 V, as explained above on Figure 10b. Higher Vop is generally required to have small CP for cost reduction. Figure 12b shows the input current of CP, I_OP, when the CP is designed to run at the input voltage of V_OP to output I_PP at V_PP with the high η. The slope was about −1.16 like the curve (c) of Figure 4, which indicates that a higher V_OP basically allows a smaller TEG.

Figure 13a shows η of CP vs. V_OP. CP1′s were the optimized designs as shown by the bold arrows in Figure 10a–e. CP2 indicates another design with 6% lower η and 90% smaller area at V_OP = 1 V shown by the broken arrow in Figure 10b. η tends to increase as V_OP. Figure 13b shows TEG area as a function of V_OP by using (9) or (11) for the CPs depending on whether a variable V_OC range is unlimited or limited. Equation (9) is valid across the entire V_OP range in case of V_{OC_MAX} ≥ 3 V whereas (11) is used when V_OP ≥ 0.8 V in case of V_{OC_MAX} = 1.6 V. TEG can be minimized at a higher V_OP when V_{OC_MAX} ≥ 3 V because CP nominally has a higher η at a higher V_OP. On the other hand, when V_{OC_MAX} is limited, V_OP around V_{OC_MAX}/2 provides the minimum area for TEG. In this demonstration, V_OP to have TEG area as small as minimum is 1.0 V with CP1 or between 0.5 V and 0.75 V with CP1 or 1.0 V with CP2. Figure 13c shows CP area as a function of V_OP. Basically, CP area exponentially increases as V_OP decreases. When V_{OC_MAX} is limited at 1.6 V, the minimum TEG cost is realized with CP1 operated at 1.0 V. CP1 area is about 1.0 mm². If 10% larger TEG cost is acceptable, CP2 with 0.1 mm² would be another option. Thus, once the actual operating point V_OP and I_OP are determined based on such graphs as Figure 13b,c, one can design TEG based on (22) or (26) under the condition that R_TC and the minimum V_TC of a unit TEG are given, depending on the V_{OC_MAX} condition as discussed above.

In summary, CP design flow is as follows:

(1)

The minimum required output current I_{PP_TGT} at the target output voltage V_PP are specified by the load.

(2)

The optimum CP is designed to have the minimum input power as a function of the input voltage V_OP based on equations (9) through (21).

(3)

The results provide the required TEG output current I_OP at every V_OP.

• TEG design flow is then as follows:

(4)

The minimum temperature difference in operation is specified, which determines the output impedance RTC and open circuit voltage VTC of a TEG unit.

(5)

The number of TEG arrays NP and the number of TEG units connected in series per array NS are determined to minimize the TEG area, i.e., the TEG cost, based on equations (22) through (26).

To see if the CP design flow using Table I is sufficiently valid, the gate-level CP2 circuit to operate at V_OP of 1.0 V was designed in 65 nm CMOS. Ultra-low-power diodes [20] were used for switching diodes. The CP was simulated together with TEG whose V_OC and R_TEG were 1.6 V and 2.5 kΩ, respectively. The V_PP–I_PP curve of the model was in good agreement with SPICE simulation as shown in Figure 14.

When the parasitic resistance of the interconnection to connect multiple TEG units is not negligibly small or the oscillator cell consumes substantial power, proper corrections would need to be done to accurately design the TEG–CP system with minimum cost.

4. Conclusions

A practical design flow for minimizing TEG energy harvester was proposed and demonstrated taking interaction between the TEG electrical parameters such as the open circuit voltage and output resistance of TEG and the load conditions such as the input voltage and current of sensor/RF chip and the power conversion efficiency of the Dickson charge pump converter in autonomous sensor modules into consideration. By using the proposed design flow, one can determine the total number of TEG units together with the number of TEG arrays and the number of TEG units connected in series per array for minimum TEG cost.