A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs
, Francesco Centurelli, Giuseppe Scotti *, Pasquale Tommasino and Alessandro TrifilettiRound 1
Reviewer 1 Report
The authors have designed a new converter based on a body-driven current mirror. The paper is well-written and provides a detailed comparison with already published designs. However, I suggest the main contributions of the design should be clearly mentioned in the introduction section. Moreover, the paper only contains simulation results of the design. The reviewer could not find information about the hardware implementation of the design. The hardware model should also be designed and provided.
Author Response
Reviewer 1
The authors have designed a new converter based on a body-driven current mirror. The paper is well-written and provides a detailed comparison with already published designs.
REPLY: We thank the reviewer for this positive comment.
However, I suggest the main contributions of the design should be clearly mentioned in the introduction section.
REPLY: The main advantages of the proposed topology have been highlighted in the introduction of the revised manuscript as follows:
“In this paper we propose a body-driven current mirror whose performance is enhanced exploiting an auxiliary amplifier which allows to lower the input impedance and to accurately match the drain-source voltages of the two transisotrs of the current mirror. When the enhanced body-driven current mirror is used to design a D2S stage, these features result in improved CMRR, which becomes one order of magnitude higher than the one provided by a conventional body-driven current mirror. Furthermore, the proposed topology improves the linearity performance of the D2S under large signal swing and increase the robustness with respect to PVT variations. A simple 2-stage OTA, composed by a D2S exploiting the proposed mirror and a body-driven inverter, is designed and simulated in a commercial 130nm CMOS technology to highlight the advantages of the novel topology over the conventional one.”
Moreover, the paper only contains simulation results of the design. The reviewer could not find information about the hardware implementation of the design. The hardware model should also be designed and provided.
REPLY: Surely, an ULV OTA exploiting the proposed enhanced D2S will be tested on chip in future works, but, at present, we are not able to provide experimental results.
However, we believe that, PVT and Monte Carlo simulations (which we provide and discuss) are sufficient to prove the effectiveness of the approach. In fact, Monte Carlo results prove that, at least with good models (and we have used reliable statistical models provided by the IC manufacturer for a well established 130nm CMOS process), the two stage amplifier can be expected to work in the range predicted by PVT and Monte Carlo simulations after production.
In the revised manuscript we have also added a picture of the layout of the OTA and provided post layout simulations and an accurate estimation of the area footprint.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
In this manuscript A Differential-To-Single-Ended Converter based on Enhanced
Body-Driven Current Mirrors targeting Ultra-Low Voltage OTAs is proposed. The following comments should be considered:
1-Abstract should be revised and quantitative results with numbers and performance improvement percentages should be provided.
2-In the introduction, Kindly avoid using “I” and “We” in the manuscript and provide passive voice sentences in the manuscript for example:
In line 59: In this paper we propose a body-driven …
In line 127: We decided to design the…
3- The applied bias voltage values for the both NMOS and PMOS transistors (Vbiasp and Vbiasn) should be provided and sufficient explanations about applied voltage values and comparisons of these values with VDD should be added.
4- In the proposed designed circuit, obtained value for “W” in some cases 48.33um, 16.11um, 193.32um are reported. Are these values are valid in layout and fabrications. Is it possible to implement with these precision? Is post layout simulation is preformed?
5-In line 131 mentioned that, the amplifier area was estimated with the Cadence Layout XL 131 tools and result to amount to about 3500 um2 and in Table 5, is reported 3540 um2. But the layout is not depicted. Provide layout of the designed amplifier.
6-In footnote of Table 5 both of Simulated and Measured has star (*). *Simulated; *Measured. Correct this issue.
7- in Fig 8, reported that s dc gain is about 41.28dB, at 7.95kHz and phase margin is around 52°. For better clearness emphasize these tow values with marker and line in the figure.
8- The font of written label for both Y and X axes in figures 8-13 should be modified.
9- Tables 1-5 should be written according to the journal template.
10- In line 169 caption of figure 14 is written with red color should be modified.
11- The BD=Body driven voltage values should be provided.
12- The novelty of the proposed design should be clearly emphasized.
13- The proposed design consumes 120 nW which is largest value compared with other related reported work in Table.5. What is the justification for this high power consumption?
Author Response
Reviewer 2
In this manuscript A Differential-To-Single-Ended Converter based on Enhanced Body-Driven Current Mirrors targeting Ultra-Low Voltage OTAs is proposed. The following comments should be considered:
1-Abstract should be revised and quantitative results with numbers and performance improvement percentages should be provided.
REPLY: We thank the reviewer for this comment. We have provided quantitative results in the abstract of the revised manuscript as follows:
“Simulation results have shown that the proposed enhanced D2S allows achieving ULV OTAs with a CMRR and a PSRR which are 18dB and 9dB higher than the ones obtained with the conventional D2S topology respectively. Also linearity performance results improved as shown by the THD which is passed by -24.95 dB to -30.03 dB, thus decreasing of about 5dB.”
2-In the introduction, Kindly avoid using “I” and “We” in the manuscript and provide passive voice sentences in the manuscript for example:
In line 59: In this paper we propose a body-driven …
In line 127: We decided to design the…
REPLY: We thank the reviewer for this comment. All the sentences containing “I” or “We” have been modified as suggested in the revised manuscript.
3- The applied bias voltage values for the both NMOS and PMOS transistors (Vbiasp and Vbiasn) should be provided and sufficient explanations about applied voltage values and comparisons of these values with VDD should be added.
REPLY: Voltages Vbiasp and Vbiasn are derived through conventional current mirrors in order to accurately set the bias current in each branch. Their values are both set at about 150mV (VDD/2).
4- In the proposed designed circuit, obtained value for “W” in some cases 48.33um, 16.11um, 193.32um are reported. Are these values are valid in layout and fabrications. Is it possible to implement with these precision? Is post layout simulation is preformed?
REPLY: We thank the reviewer for this comment. We have successfully implemented the layout of the OTA and performed post-layout simulations. Post layout simulation results have been found to be quite similar to the results of schematic level simulations.
5-In line 131 mentioned that, the amplifier area was estimated with the Cadence Layout XL 131 tools and result to amount to about 3500 um2 and in Table 5, is reported 3540 um2. But the layout is not depicted. Provide layout of the designed amplifier.
REPLY: We thank the reviewer for this comment. For the first submission the Area footprint was roughly estimated by just placing the components without any optimization. For the revised version we have implemented the layout of the OTA and a picture has been added in Fig. 8 of the revised manuscript. When implementing the layout we have been able to reduce the area which now results to be 2350 um2.
6-In footnote of Table 5 both of Simulated and Measured has star (*). *Simulated; *Measured. Correct this issue.
REPLY: We thank the reviewer for this comment. The issue has been corrected.
7- in Fig 8, reported that s dc gain is about 41.28dB, at 7.95kHz and phase margin is around 52°. For better clearness emphasize these tow values with marker and line in the figure.
REPLY: We thank the reviewer for this comment. Fig. 8 (Fig. 9 in the revised manuscript) has been modified as suggested by the reviewer.
8- The font of written label for both Y and X axes in figures 8-13 should be modified.
REPLY: We thank the reviewer for this comment. Figs. 8-13 (9-14 of the revised manuscript) have been modified as suggested by the reviewer.
9- Tables 1-5 should be written according to the journal template.
REPLY: We thank the reviewer for this comment. Tables 1-5 has been modified as suggested in the revised manuscript.
10- In line 169 caption of figure 14 is written with red color should be modified.
REPLY: We thank the reviewer for this comment. Color has been changed in the revised manuscript.
11- The BD=Body driven voltage values should be provided.
REPLY: All body terminals are biased at about 150mV (i. .e VDD/2).
12- The novelty of the proposed design should be clearly emphasized.
REPLY: The main novelty and advantages of the proposed topology have been highlighted in the introduction of the revised manuscript as follows:
“In this paper we propose a body-driven current mirror whose performance is enhanced exploiting an auxiliary amplifier which allows to lower the input impedance and to accurately match the drain-source voltages of the two transisotrs of the current mirror. When the enhanced body-driven current mirror is used to design a D2S stage, these features result in improved CMRR, which becomes one order of magnitude higher than the one provided by a conventional body-driven current mirror. Furthermore, the proposed topology improves the linearity performance of the D2S under large signal swing and increase the robustness with respect to PVT variations. A simple 2-stage OTA, composed by a D2S exploiting the proposed mirror and a body-driven inverter, is designed and simulated in a commercial 130nm CMOS technology to highlight the advantages of the novel topology over the conventional one.”
13- The proposed design consumes 120 nW which is largest value compared with other related reported work in Table.5. What is the justification for this high power consumption?
REPLY: The chosen power consumption is related to the desired GBW and load capacitance. We have designed the OTA targeting biomedical (more specifically neural recording) applications in which often a GBW around 7.5KHz is required. However we believe that for a safe comparison between different designs FOMS and FOML have to be used.
Author Response File: Author Response.pdf
Reviewer 3 Report
Della Salla et al. proposed an ultra-low voltage (ULV) technique to improve body-driven current mirrors. It was found that the proposed enhanced D2S allows achieving ULV OTAs with improved performance, in particular in terms of 12 CMRR and linearity. Overall, the article is well-written and structured. If the research gap can be better defined and the contributions to scholars and practioners can be highlighted, this study will be more completed.
Author Response
Reviewer 3
Della Salla et al. proposed an ultra-low voltage (ULV) technique to improve body-driven current mirrors. It was found that the proposed enhanced D2S allows achieving ULV OTAs with improved performance, in particular in terms of CMRR and linearity. Overall, the article is well-written and structured.
REPLY: We thank the reviewer for this positive comment.
If the research gap can be better defined and the contributions to scholars and practioners can be highlighted, this study will be more completed.
REPLY: The main novelty and advantages of the proposed topology have been highlighted in the introduction of the revised manuscript as follows:
“In this paper we propose a body-driven current mirror whose performance is enhanced exploiting an auxiliary amplifier which allows to lower the input impedance and to accurately match the drain-source voltages of the two transisotrs of the current mirror. When the enhanced body-driven current mirror is used to design a D2S stage, these features result in improved CMRR, which becomes one order of magnitude higher than the one provided by a conventional body-driven current mirror. Furthermore, the proposed topology improves the linearity performance of the D2S under large signal swing and increase the robustness with respect to PVT variations. A simple 2-stage OTA, composed by a D2S exploiting the proposed mirror and a body-driven inverter, is designed and simulated in a commercial 130nm CMOS technology to highlight the advantages of the novel topology over the conventional one.”
Round 2
Reviewer 1 Report
No comments
Reviewer 2 Report
The authors have cited most of my concerns the paper can be accepted.
