A Gain-Enhanced Low Hardware Complexity Charge-Domain Read-Out Integrated Circuit Using a Sampled Charge Redistribution Technique

Abstract

A gain-enhanced low hardware complexity charge-domain read-out integrated circuit is implemented. By adopting a sampled charge redistribution technique, low hardware complexity is achieved, which in turn saves 10% of the die area and provides 33% gain enhancement compared to the conventional topology. In particular, a charge-domain discrete-time filter with inherent reconfigurability is a key building block, which can also act as an anti-aliasing filter before the analog-to-digital converter. The measurement results show good agreement with the intended frequency response. The proposed filter is implemented using a 0.11 μm CMOS process and occupies 0.15 mm².

1. Introduction

In today’s internet of things (IoT) era, more than 20 billion sensor systems are being used [1]. Sensor systems include a sensor and a read-out integrated circuit. In order to reduce the development time and cost, there are demands for a read-out integrated circuit that can be reconfigurably applied to various and multiple sensors [2,3]. As shown in Figure 1, a read-out integrated circuit usually consists of an instrumentation amplifier and a noise reduction filter, which amplifies the output signals of the sensor and attenuates noises. In particular, the analog noise reduction filter used in the conventional read-out integrated circuit has a limitation of being reconfigurably used for the sensor system. That is, there is a disadvantage: the size of passive components such as resistors or capacitors should be changed or transconductance must be adjusted in a wide range [4]. For this reason, a charge-domain discrete-time filter with inherent reconfigurability is being spotlighted, since the filtering characteristic can be adjusted by changing the sampling period, capacitance ratio, and transconductance of the g_m-cell [5,6,7,8,9,10,11,12,13,14]. For the implementation of a charge-domain discrete-time filter, input sample weights are realized by using the capacitance ratio. However, if the order of the filter is increased for high attenuation characteristics, the number of required capacitors is increased [5,6,7,8,9,10,11]. This leads to considerable area consumption and thus aggravates the cost efficiency.

There have been many approaches to reducing the number of capacitors. For example, [13] adopted the successive charge accumulation method. However, the number of required g_m-cells increases in proportion to the tap number, and complex clock phases are also needed. Hence, a large power consumption and high complexity are inevitable. Furthermore, transconductance mismatch among g_m-cells causes additional non-linearity. On the other hand, Ref. [14] uses an IIR filter structure, so fewer capacitors are used compared to the fir filter structure. However, there is a constraint to the filter coefficient that can be implemented, so the desired frequency response may not be obtained. In addition, since multiple nulls cannot be implemented in the IIR filter structure, there is a restriction to obtaining high attenuation characteristics in a specific frequency range.

In this paper, a gain-enhanced low hardware complexity charge-domain read-out integrated circuit with a charge-domain discrete-time filter is proposed and verified with input sample weights of {1,2,1}. It has reduced number of capacitors by adopting a sampled charge redistribution technique, which provides gain enhancement. Only a single g_m-cell and clock phase are utilized.

2. Conventional Architecture

The conventional architecture for the implementation of a charge-domain discrete-time filter with input sample weights of {1,2,1} is shown in Figure 2 [6]. Because the charge-domain discrete-time filter operates based on charge sampling, the voltage input signal is converted to a current input signal by the g_m-cell. The unit sampling capacitors are all of the same value, and a five-phase clock is also used.

The conventional architecture has three operating phases: charge sampling, read-out, and discharging. During the on-state of switch S₀, the current input signal x[0] is accumulated in four unit sampling capacitors—C₁, C₂, C₃, and C₄—with the same ratio. Hence, C₁, C₂, C₃, and C₄ contain a charge corresponding to x[0]/4, respectively. In the same manner, during the on-state of switches S₁ and S₂, the current input signals x[1] and x[2] are accumulated into C₅, C₆, C₇, and C₈ and C₉, C₁₀, C₁₁, and C₁₂ with an amount of x[1]/4 and x[2]/4, respectively. During the on-state of switch S₃, stored charges in C₁, C₆, C₇, and C₁₂, which correspond to x[0]/4, x[1]/4, x[1]/4, and x[2]/4, are read-out, and, thus, the input sample weights of {1,2,1} can be implemented. After the read-out operation, C₁, C₆, C₇, and C₁₂ are discharged during the on-state of switch S₄ for the purpose of the next sampling operation.

In other words, five groups of sampling capacitors are used to implement input sample weights {1,2,1}. For sampling capacitor group-1 (C₁, C₆, C₇, C₁₂), the charge sampled at C₁ during S₀, the charge sampled at C₆ and C₇ during S₁, and the charge sampled at C₁₂ during S₂ are used. The same operations are repeated in other groups, and through this, the input sample weights {1,2,1} are implemented. The operation diagram of the conventional architecture for the input sample weights of {1,2,1} is shown in

Table 1. Operation diagram of the conventional architecture for the input sample weights of {1,2,1}. CS, RO, and D stand for charge sampling, read-out, and discharging, respectively.

Operation Diagram		Clock State
		S0	S1	S2	S3	S4
Sampling capacitor group-1	C1	CS	-	-	RO	D
	C6	-	CS	-	RO	D
	C7	-	CS	-	RO	D
	C12	-	-	CS	RO	D
Sampling capacitor group-2	C2	CS	-	RO	D	-
	C3	CS	-	RO	D	-
	C8	-	CS	RO	D	-
	C17	-	-	RO	D	CS
Sampling capacitor group-3	C4	CS	RO	D	-	-
	C13	-	RO	D	CS	-
	C18	-	RO	D	-	CS
	C19	-	RO	D	-	CS
Sampling capacitor group-4	C5	D	CS	-	-	RO
	C10	D	-	CS	-	RO
	C11	D	-	CS	-	RO
	C16	D	-	-	CS	RO
Sampling capacitor group-5	C9	RO	D	CS	-	-
	C14	RO	D	-	CS	-
	C15	RO	D	-	CS	-
	C20	RO	D	-	-	CS

.

3. Proposed Architecture

The proposed architecture is implemented with input sample weights of {1,2,1}, and its circuit and clock generation are shown in Figure 3. The current input signal is generated by the g_m-cell. The clock generator consists of D flip-flops and logic gates for the generation of the required six-phase clock. The unit sampling capacitors are all of the same value.

The proposed architecture has four operating phases: charge sampling, charge redistribution, read-out, and discharging. During the on-state of switch S₀, the current input signal x[0] is accumulated in two unit sampling capacitors—C₁ and C₂—with the same ratio. Hence, C₁ and C₂ contain a charge corresponding to x[0]/2, respectively. During the on-state of switch S₁, C₂ and C₃ are connected in parallel, and then the existing sampled charge of C₂ is shared with C₃ with a ratio of 1:1. This is sampled charge redistribution technique. Therefore C₂ and C₃ have the same amount of charge as x[0]/4. In the same manner, during the on-state of switches S₁ and S₂, the input signal x[1] is divided into C₄, C₅, and C₆ with an amount of x[1]/2, x[1]/4, and x[1]/4, respectively. Likewise, during the on-state of switches S₂ and S₃, the input signal x[2] is accumulated on C₇, C₈, and C₉ with an amount of x[2]/2, x[2]/4, and x[2]/4, respectively. During the on-state of switch S₄, stored charges in C₃, C₄, and C₈, which correspond to x[0]/4, x[1]/2, and x[2]/4, are read-out, and, thus, the input sample weights of {1,2,1} can be implemented. After the read-out operation, C₃, C₄, and C₈ are discharged during the on-state of switch S₅ for the purpose of the next sampling operation.

The operation diagram of the proposed architecture for the input sample weights of {1,2,1} is shown in

Table 2. Operation diagram of the proposed architecture for the input sample weights of {1,2,1}. CS, CR, RO, and D stand for charge sampling, charge redistribution, read-out, and discharging, respectively.

Operation Diagram		Clock State
		S0	S1	S2	S3	S4	S5
Sampling capacitor group-1	C1	CS			RO	D
	C5		CS	CR	RO	D
	C18	CR			RO	D
Sampling capacitor group-2	C2	CS	CR	RO	D
	C15			RO	D		CR
	C16			RO	D		CS
Sampling capacitor group-3	C3		CR			RO	D
	C4		CS			RO	D
	C8			CS	CR	RO	D
Sampling capacitor group-4	C6	D		CR			RO
	C7	D		CS			RO
	C11	D			CS	CR	RO
Sampling capacitor group-5	C9	RO	D		CR
	C10	RO	D		CS
	C14	RO	D			CS	CR
Sampling capacitor group-6	C12		RO	D		CR
	C13		RO	D		CS
	C17	CR	RO	D			CS

. Six groups of sampling capacitors are used to implement the input sample weights {1,2,1}. In the case of group 1 (C₁, C₅, C₁₈), the charge sampled in C₁ during S₀, the charge stored in C₅ during S₁ and then redistributed to C₆ during S₂, and the charge redistributed from C₁₇ during S₀ and stored in C₁₈ are used. The charge stored in C₁₇ was sampled during S₅. The same operations are repeated in other groups, and through this, the input sample weights {1,2,1} are implemented.

4. Performance Analysis

In comparison with conventional architecture, which requires 40 unit sampling capacitors to implement input sample weights of {1,2,1}, the proposed architecture only requires 36 unit sampling capacitors and thus saves 10% of the sampling capacitors area. The voltage gain of the charge-domain discrete-time filter is proportional to the transconductance of the g_m-cell, the sampling period, and the sampling capacitance. Furthermore, the voltage gain equations of the conventional and proposed architecture are expressed as

$$Gai{n}_{Conventional}=\frac{1}{4}\cdot \frac{1}{4}\left(\frac{g_m\Delta t}{C_s}+\frac{2g_m\Delta t}{C_s}+\frac{g_m\Delta t}{C_s}\right)=\frac{1}{16}\left(\frac{g_m\Delta t}{C_s}+\frac{2g_m\Delta t}{C_s}+\frac{g_m\Delta t}{C_s}\right)$$

(1)

$$Gai{n}_{Proposed}=\frac{1}{2}\cdot \frac{1}{2}\cdot \frac{1}{3}\left(\frac{g_m\Delta t}{C_s}+\frac{2g_m\Delta t}{C_s}+\frac{g_m\Delta t}{C_s}\right)=\frac{1}{12}\left(\frac{g_m\Delta t}{C_s}+\frac{2g_m\Delta t}{C_s}+\frac{g_m\Delta t}{C_s}\right)$$

(2)

where g_m is the transconductance, Δt is the sampling period, and C_s is the unit sampling capacitance. In Equation (1), constants 1/4 and 1/4 are derived from the charge sampling and read-out operation, respectively. Likewise, in Equation (2), constants 1/2, 1/2, and 1/3 originate from charge sampling, charge redistribution, and read-out operation, respectively. Under the condition that the values of g_m, Δt, and C_s of the conventional and proposed architectures are equal, the proposed architecture shows about 33% gain enhancement. Moreover, the proposed charge-domain discrete-time filter has non-decimation property given by time-interleaving operation. Thus, compared to the architecture [8] with a decimation property, it is relatively free from the folding noise issue [11]. The additional requirement of sampling capacitors implementing non-decimation architecture is mitigated by adopting the proposed sampled charge redistribution technique. It also has a reconfigurability that enables the change in null locations through the control of the sampling frequency. The performance comparisons are summarized in

Table 3. Performance comparison between the proposed and conventional architectures.

	Proposed Architecture	Conventional Architecture
Input sample weights	{1,2,1}	{1,2,1}
Decimation	None	None
The number of sampling capacitors	36	40
The number of clock phases	6	5
The number of gm-cells	1	1
DC gain	$\frac{1}{3}\cdot \frac{g_m\Delta t}{C_S}$	$\frac{1}{4}\cdot \frac{g_m\Delta t}{C_S}$

.

The implementation of the finite impulse response filter in an analog domain by using a charge-domain discrete-time filter gives an additional sinc type filtering characteristic. Figure 4 shows the unit configuration of a charge-domain discrete-time filter. During the on-state of switch S₀, the input signal is stored in the sampling capacitor C_S. While the switch S₁ is turned on, the value stored in C_S is read-out. Likewise, during the on-state of switch S₂, C_S is discharged. The output voltage and magnitude of transfer function are expressed as

$$\begin{array}{cc}\hfill V_{out}(t_1)& =\frac{g_m}{C_s}{\displaystyle {\int }_{t_0}^{t_1}{V}_{in}}\hfill \\ & =\frac{g_m}{C_s}{\displaystyle {\int }_{t_0}^{t_1}\sin \omega t dt}\hfill \\ & =\frac{g_m\Delta t}{C_s}\sin \pi f(t_0+t_1)\frac{\sin \pi f\Delta t}{\pi f\Delta t}\hfill \end{array}$$

(3)

$$\left|H(f)\right|=\frac{g_m\Delta t}{C_s}\left|\frac{\sin \pi f\Delta t}{\pi f\Delta t}\right|$$

(4)

where g_m is the transconductance, Δt is the sampling period, and C_s is the unit sampling capacitance. That is, as the input signal is accumulated in the sampling capacitor during the sampling period, the charge-domain discrete-time filter has a sinc type frequency response. The positions of nulls of the sinc type frequency response are determined by the sampling period. That is, the location of the nulls can be adjusted by changing the sampling period. DC gain is determined by the transconductance, sampling period, and sampling capacitor. In addition, since nulls are located at every integer multiple of the sampling frequency, there is an advantage in that anti-aliasing is possible before passing through the analog-to-digital converter (ADC).

Figure 5 presents the frequency response of the proposed charge-domain discrete-time filter, and its expression is given by

$$\left|H(f)\right|=\left|\frac{\sin \left(\pi f/f_s\right)}{\pi f/f_s}\right|\cdot {\left|\frac{\sin \left(2\pi f/f_s\right)}{\sin \left(\pi f/f_s\right)}\right|}^2$$

(5)

where f_s is the sampling frequency and is set to 30 MHz in this measurement. By the charge integration, the charge-domain discrete-time filter has an inherent sinc type frequency response. In the case of input sample weights being equal to {1,2,1}, nulls are located on the integer multiples of f_s/2. Since the null is periodically repeated, it is effective in interferer rejection. The proposed charge-domain discrete-time filter shows good agreement with the theory and simulation ones. The difference in the attenuation level mainly comes from the mismatch among sampling capacitors, the finite output resistance of the g_m-cell, and the parasitic capacitance of routing lines. Thus, it is considered that ratio changes among the filter coefficients of {1,2,1} have occurred. Therefore, the attenuation characteristics at the null position are deteriorated. Moreover, the attenuation characteristics of the nulls generated by the sinc type filtering response are degraded, and it is considered that the finite output impedance of the gm-cell had a major effect [7]. That is, if the output impedance of the transconductance amplifier is not infinite, it has a limitation in obtaining infinite attenuation characteristics at the nulls.

As shown in Figure 6, sampling capacitors are connected to sampling switches through routing lines. However, the length difference among routing lines causes parasitic capacitance ununiformity, which causes capacitance ratio variation among the sampling capacitors, as listed in

Table 4. Parasitic capacitance of routing lines connected to sampling capacitors in the positive path.

Routing Line Connected to Sampling Capacitor CN	Parasitic Capacitance (fF)
N = 1	21.84
N = 2	9.21
N = 3	19.89
N = 4	21.2
N = 5	9.09
N = 6	19.7
N = 7	21.34
N = 8	9.21
N = 9	21.34
N = 10	21.21
N = 11	9.09
N = 12	19.71
N = 13	21.34
N = 14	9.21
N = 15	19.89
N = 16	21.20
N = 17	9.11
N = 18	19.67

. An 800 fF unit sampling capacitance is adopted in this architecture. Moreover, the parasitic capacitance of clock routing lines causes duty disproportion among individual clock phases.

The chip photomicrograph is shown in Figure 7. The proposed filter has been implemented in a 0.11 μm CMOS process. MIM capacitors are used for sampling capacitors. The output buffer is added for measurement. The chip occupies 0.15 mm² and consumes 7.86 mW, including the output buffer. Compared to the conventional architecture, the die area can be reduced because the required sampling capacitances are reduced. Additionally, since the DC gain of the charge-domain discrete-time filter is inversely proportional to the sampling capacitance, the proposed architecture can achieve DC gain enhancement.

On the other hand, since the proposed architecture requires an additional clock phase for charge redistribution, the number of clock phases is increased compared to the conventional architecture. To implement an additional clock phase, a D flip-flop should be added to the clock generator. However, considering that the capacitance area is reduced through the use of the proposed architecture, the increase in the D flip-flop area does not have a significant effect on the die area. Additionally, digital circuits such as a D flip-flop can be implemented with a small die area according to the scaling down of the CMOS process. On the other hand, in the case of the MIM capacitor, which is mainly used in the CMOS process, the area does not significantly decrease, even if the CMOS process is scaled down. Therefore, reducing the number of required capacitors, as in the proposed architecture, is very effective when considering the scaling down of the CMOS process.

5. Conclusions

A novel topology for the implementation of a charge-domain discrete-time filter is presented, which is well suited for a read-out integrated circuit in an IoT sensor system. The proposed sampled charge redistribution technique provides die area saving and gain enhancement compared to a conventional implementation. The measured frequency response is in good agreement with the theoretical expectation and simulation result, demonstrating the effectiveness of the proposed technique.