A 5.42~6.28 GHz Type-II PLL with Dead-Zone Programmability and Charge Pump Mismatch Trimming

Round 1

Reviewer 1 Report

The proposed PLL design looks simple and flexible. However, I have some comments:

1)      Revising the abstract and results discussion will appeal your work and help reader understand better the outcome of your design compared to other existing ones.

2)      The reference clock of the proposed PLL (120MHz) is quite high compared to other deign. Please explain the reason of such a high reference clock. How the refence clock is generated on the testing PCB board. Do you have any concern about noise and performance if the reference clock is noisy?

3)      Based on the fabrication process, all design included in the comparison table1 seems to have comparable performance. How do you qualify your design to be better performances?

4)      Professional Proofreading is advised to address some typos and grammar errors.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

This is a sound work, which needs minor improvements

 

1. English proof editing is suggested

2. Abstract lacks a description of the novelty of the proposed design

3. literature survey , explaining the need of the work

4. Why do the authors aim for the specific carrier they chose?

5.Fig.2: why is the input DIV shorted to the 3bit dead zone programmer?

6. when explaining any sub block , pls outline its purpose

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

The quality of the edited drafted improved compared to the first draft.

Authors answered promptly all my concerns.