High-Speed Grouping and Decomposition Multiplier for Binary Multiplication

Abstract

In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The proposed multiplier aims to achieve competency in processing algorithms over existing multiplier architectures through a combination of the parallel grouping of partial products of the same size and the decomposition of each grouped partial-product bit, with the final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic reduces the number of computation steps and hence achieves a higher speed in multiplication. The front-end and physical design implementation of the proposed GD multiplier have been executed in the 180 nm technology library using the Cadence^® Virtuoso and Cadence^® Virtuoso Assura tools. From the front-end design of the 8 × 8 proposed GD multiplier, it was observed that the GD multiplier achieves a reduction of approximately 56% in computation time and a reduction of 53% in power–delay product when compared to existing multiplier architectures. A further reduction in the power–delay product is achieved by the physical design implementation of the proposed multiplier due to the internal routing of subsystems with the shortest-path algorithm. The proposed multiplier works better with higher-order multiplication and is suitable for high-end applications.

1. Introduction

Applications for multimedia, image processing, and the Internet of Things not only require extensive computing, but they also require a quick response while using minimal power. Digital logic circuits are the backbone of most computer arithmetic applications, making them highly reliable and accurate. The multiplier [1,2] is one of the most important arithmetic building blocks, and it is frequently employed in many applications, particularly those related to signal processing. Fast multipliers [3] come in a variety of forms, and each form has its advantages and disadvantages. Most researchers are currently concentrating mainly on improving performance metrics such as power, area consumption, and computational time [4]. The multipliers have sequential and parallel architectures as their two main design options. Sequential designs have a minimal power requirement, but a relatively high delay. Conversely, Wallace tree and Dadda are fast parallel designs with significant levels of power consumption [5,6].

Because both power consumption and processing speed are essential considerations in the layout of digital circuits, optimizing these aspects of multipliers is of the utmost significance. It is a quite common practice to optimize one parameter while simultaneously taking into account a constraint imposed on another parameter. Specifically, the task is difficult because of the minimal power capacity of portable devices, which must be considered when trying to achieve optimum performance. Having a certain level of reliability may also hinder the system’s desired level of performance. There are numerous techniques at various design abstraction levels that can be used to achieve both the power and speed requirements. A common type of multiplier is an array multiplier, which implements multiplication as a shift-and-add operation. However, because it performs more computations, it uses more energy, takes up more space, and takes more computational time [7]. The Vedic multiplier is the main focus of current research since it has advantages over array multipliers, such as having a high speed and requiring less area [8,9,10]. Inexact computing techniques seek to meet objective parameters while sacrificing computation accuracy [11]. The basic foundation for inexact arithmetic computation is the minimization of the arithmetic unit circuits [12]. The strategy can be employed when there is no unique solution and/or a set of near-accurate results is acceptable [13].

The 16-bit Dadda multiplier has been approached in a novel way, employing new compressor designs, by Sebastian, Alen, et al. These brand-new compressors include two 4–2 compressors [14] along with an updated higher-order compressor. Three proposed multiplier designs were compared with existing multiplier designs. In terms of delay and area, the proposed design was determined to be closer to ideal than the previous designs, and it can be applied to exact multiplier applications. This approach produces a minimum delay of 20.612 ns and an area of 84 slices. However, the power reduction was not considered.

A unique Wallace tree multiplier structure designed by Devi Ykuntam, et al. has been suggested as a method for decreasing the delay time of the Wallace tree multiplier without compromising its area parameter. In the suggested arrangement, parallel prefix adders [15] complete the addition process of the partial products (PPAs). Using the Kogge–Stone adder, Sklansky adder, Brent–Kung adder, Ladner–Fischer adder, and Han–Carlson adder, five Wallace tree multiplier architectures were presented. The suggested multiplier designs’ areas (number of LUTs) and delays (ns) are compared with the conventional multiplier design. Among them, a 16-bit Wallace tree multiplier using the Kogge–Stone adder had a delay of 29.44 ns and an area of 634 LUTs.

Approximation methods [16] have the advantage of reducing device usage for high-computation applications, which eventually results in a reduction in both power consumption and delay. Both the redundant bit and the amount of storage required to keep the data will be reduced in the end. The computational complexity of arithmetic circuits can be reduced through approximation without significantly affecting the coding efficiency. The approximate, almost-full adder-based Dadda multiplier that is suggested ultimately increases speed and requires less energy and a fewer number of devices. The present work evaluates the analysis of several multipliers using an approximation of a nearly full adder. An 8-bit Dadda multiplier with an almost-full adder consumes 11.409 W of power and 0.20 LUTs of area.

In order to reduce multiplier power consumption, a redesigned full adder [17] with a multiplexer was developed by Jaiswal, Kokila Bharti, et al. The traditional Wallace tree multiplier design was used to evaluate the effectiveness of the suggested structure. Comparing the suggested multiplier to a traditional structure, the ASIC synthesis results revealed an average reduction of 37.45% in power requirements, 45.75% in area, and 17.65% in delay. Using the proposed full adder to make a 16-bit Wallace multiplier takes 6.5534 mW of power and 8.81 ns of time.

Wallace and Dadda multipliers [18] were created using a brand-new hybrid 3–2 counter by Devnath, et al. The suggested method used several AND gates to make partial products, and a good model of an AND gate only needs two transistors. The multipliers were developed using the 65 nm PTM (full form) transistor model. A thorough evaluation and comparison of both multipliers’ system results with other models already in use were conducted. The delay of a 4-bit Dadda multiplier with a hybrid full adder was 220.9 ps, and the power consumption was 20.34 μW.

Ram, et al. examined the Wallace multiplier with the conventional array multiplier and the Dadda multiplier regarding the delay. Additionally, the Carry-select adder (CSLA) [19] and binary to excess-1 converter (BEC) adders were used to construct the 16-bit Wallace multiplier that was suggested. The Wallace multiplier with a CSLA requires less computational time than the Wallace multiplier with a BEC. The 16 × 16-bit Wallace multiplier for the binary to excess code converter has a delay of 24.948 ns and consumes 86.48 mW of power.

Momeni, Amir, et al. examined and designed two new approximate 4–2 compressors [20] to employ them in a multiplier. These designs utilize various compression aspects, and as a result, the inaccuracy in computation can be accommodated with regard to the circuit-based figures of merit of a design. They suggested and examined four distinct approaches to implementing the approximation compressors with a Dadda multiplier. The delay of an 8-bit Dadda multiplier with an approximate 4–2 compressor is 44.35 ps, and the power consumption is 1.14 μW.

Akbari, Omid, et al. proposed four 4:2 compressors that can toggle between accurate and approximate modes of operation [21]. These 2D compressors offer increased speed and decreased power consumption in the approximation mode at the expense of increased error. In addition to varying delay times and power consumption between approximate and accurate modes, each of these compressors also varies in how accurate it is when operating in the approximate mode. A 16-bit Dadda Multiplier with dual-quality 4:2 mixed compressors has a delay of 1.19 ns, and the power consumption is 2339 μW.

The performance parameters of the existing binary multipliers based on the Wallace/Dadda/parallel processing algorithm are mentioned in

Table 1. Comparison of parameters of different existing literature works.

	Title	Multiplier	Computational Time	Power Consumption/ Area Consumption	Implementation Tool/ Technological Node
1.	Design and Implementation of an Efficient Dadda Multiplier Using Novel Compressors and Fast Adder	16-bit Dadda multiplier with 4–2	20.612 ns	84 slices	Xilinx ISE
2.	Design and Analysis of High speed Wallace Tree Multiplier Using Parallel Prefix Adders for VLSI Circuit Designs	16-bit Wallace tree multiplier using Kogge–Stone adder compressors	29.44 ns	634 LUT	Xilinx ISE
3.	An Efficient Dadda Multiplier using Approximate Adder	8-bit Dadda multiplier using almost full adder	NA	11.409 Watt/ 0.20 LUT	Xilinx ISE
4.	Low-Power Wallace Tree Multiplier Using Modified Full Adder	16-bit Wallace tree multiplier using full adder	8.81 ns	6.5534 mW/ 12,627.71 μm2	Synopsys design compiler using SAED 90 nm CMOS technology
5.	4-bit Wallace and Dadda Multiplier Design Using Novel Hybrid 3–2 Counter	4-bit Dadda multiplier with hybrid full adder	220.9 ps	20.34 μW	65 nm technology
6.	Design of Delay Efficient Modified 16-bit Wallace Multiplier	16 × 16-bit Wallace multiplier binary to excess code converter	24.948 ns	86.48 mW / 1019 LUT	Xilinx
7.	Design and Analysis of Approximate Compressors for Multiplication	8-bit Dadda multiplier with approximate 4–2 compressor	44.35 ps	1.14 μW	32 nm HSPICE simulation
8.	Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers	8-bit Dadda multiplier with dual-quality 4:2 compressors mixed	0.25 ns	424 μW/ 423 μm2	45 nm technology node

. All of the existing architectures either have less speed or more power consumption, and hence, they have more power–delay product. The present research aimed to propose an architecture for binary multiplication to achieve an improved power–delay product without affecting the other parameters much. This has been achieved through the introduction of the concept of the grouping of partial products with the same size and decomposing each grouped partial product in a parallel manner. The parallel processing and decomposition logic introduced in this novel architecture reduces the number of computation steps and hence achieves high speed in computation. The GD multiplier uses a 4 × 4 conventional Wallace and Dadda binary multiplier for the decomposition logic.

2. Methodology

2.1. Conventional Wallace Multiplier (4 × 4)

Wallace’s method is a binary multiplier. The final result is obtained by the reduction of the partial products [22,23] generator (shown in Figure 1) through a single-bit full adder [2,24] and a half adder, as shown in Figure 2a,b, respectively.

After generating the partial products, each column with the at most height of h = 3 is considered, and the reduction of layers [25] takes place. The schematic design of conventional 4 × 4 Wallace multiplier is shown in Figure 3. Depending on the number of entries in the column, either single-bit half adders [26] or full adders are used to process the layers, i.e., if a single bit is passed on to the next layer as a carry over, and if two or three partial products are present in the column as entries, then they are passed through the half adder and the full adder, respectively. The sum and carry generated from the previous layer are passed on to the next set of entries. This process is repeated until it reaches the terminal layer, which consists of only a pair of entries in each column.

In the Wallace multiplier, the computational time is reduced due to the parallel reduction of bits in layers by the single-bit half adder and full adder, but the logical levels required to perform the summation can be reduced further (i.e., the number of layers). The physical design implementation of the Wallace multiplier is complex, with the higher-order multiplication of bits.

2.2. Conventional DADDA Multiplier (4 × 4)

The Dadda multiplier is a binary multiplier design invented by Luigi Dadda. This multiplier design consists of single-bit full adder and a half adder, as shown in Figure 2a,b, to process the partial products and give the final product.

Dadda multiplication starts by forming the partial products into a tree structure of a height that varies according to the products. The progression of the reduction layer is controlled by d_j (maximum height sequence), where d_j = 2, 3, 4, 6, 9, 13, etc. The value of d_j is obtained using the condition d_j < min (n,m), where n and m are the sizes of the multiplier and multiplicand. The 4 × 4 schematic of the Dadda multiplier is shown in Figure 4. The sizes of n and m are both 4. With the minimum of both n and m being 4, the maximum height sequence is determined to be 3 (as per the sequence d_j 3 < 4). With d_j determined, the reduction of layers proceeds. Tree columns formed using partial products are reduced if h > 3. Summation is achieved by producing partial products as inputs for half and full adders. Reduction layers are performed progressively i.e., h = 4 → 3 → 2 until h = 2 for producing the final products of the Dadda multiplier.

The Dadda multiplier consumes less power because it requires a minimum amount of hardware. The main drawbacks of the Dadda multiplier are that it is more complex to proceed with and to compute for a higher number of bits, and it reduces the number of bits at the early stages of reduction, which results in passing on numerous bits to the next stage.

2.3. Proposed GD Multiplier (8 × 8)

The proposed GD multiplier is a high-speed multiplier with a parallel multiplication and grouping technique, which is shown in Figure 5. The GD multiplier follows the below-described steps for 8 × 8 binary multiplication:

• Partial products generation.
• Parallel grouping of partial products and decomposition of grouped bits using a 4 × 4 Wallace and a 4 × 4 Dadda multiplier.
• Final summations of bits performed using 5LA.

After the generation of the partial products, they are divided into groups of equal size. Each group is processed through the Dadda and the Wallace multiplier alternatively; this process is called “decomposition”. It uses both Wallace and Dadda multipliers parallelly in order to reduce the computational time produced during the summation of partial products. The byproducts from each group are then passed on to the 5LA [27,28,29], shown in Figure 6, and the half adders to obtain the final results. The 5LA is a combination of two full adders to minimize carry-over steps. The GD multiplier is a hybrid multiplier incorporating both Wallace and Dadda, and it aims to combine the unique advantages of both the Wallace and Dadda multipliers. The overall working principle of the GD multiplier is shown in Figure 7, with a test input of 8 × 8.

2.4. Back-End Design Implementation of Proposed and Existing Multiplier Design

The physical design implementation of both the existing and the proposed multiplier designs has been implemented according to the conventional process flow. After the schematic design of the multiplier, the physical design implementation was carried out using the Cadence^® Virtuoso Layout Suite XL tool with a fixed place and route boundary. The interconnection of the transistors was achieved using various metal layers by following the rule deck provided by the vendor. The Design Rule Check (DRC) and the Layout Vs. Schematic (LVS) physical verifications of the back-end design were performed using the Cadence^® Assura tool. The width and spacing rules of the design were checked through the DRC, and the open-end short errors were checked through LVS. The violations were fixed manually to improve the quality of the layout. Parasitic values were extracted from a post-layout simulation of the design.

3. Results and Discussion

The proposed GD multiplier architecture has the advantage of performing higher-order bit multiplication with less computational time than the existing multiplier architectures. This has been achieved in the proposed multiplier by grouping the partial products equally and applying the decomposition procedure along with parallel computation. The proposed architecture has been implemented in the 180nm technology library. The front-enddesign of the circuit was performed using Cadence^® Virtuoso, the physical design of the circuit was performed using the Cadence^® Layout Editor, and physical verification of the layout was carried out using the Cadence^® Assura tool. Wallace and Dadda are the two main multiplier architectures used to compare the working of our proposed multiplier architecture. Both Wallace and Dadda use parallel multiplication, whereas the proposed multiplier applies parallel computation in grouped partial products.

3.1. Proposed GD Multiplier Implementation

The proposed GD multiplier architecture produces the same product result as the Wallace or Dadda multiplier for any set of binary input patterns chosen. The obtained GD multiplier product result for the sample input patterns, x = 10110110, y = 10011100 and x = 11110000, y = 00001111, are shown in Figure 8. The logic high value is mentioned as 1.8 V, and the logic low value is mentioned as 0 V. The time duration for each bit is 50 ns.

3.2. Front-End Design Performance Comparison of the Proposed GD Multiplier Architecture with Existing Multiplier Architectures

Table 2. Front-end design performance comparison between proposed GD architecture with existing multiplier architectures.

Parameters	Wallace Multiplier (4 × 4)	Dadda Multiplier (4 × 4)	GD Multiplier (4 × 4)
Delay (ns)	1.7518	1.7518	1.2274
Power (nW)	1.604	1.567	1.659
Power–Delay Product (PDP) (10−15)	0.00280	0.00274	0.00203
Hardware Requirements	2 i/p AND gate = 16	2 i/p AND gate = 16	2 i/p AND gate = 16
	FA = 8	FA = 8	FA = 4
	HA = 4	HA = 4	HA = 11

FA = single-bit full adder, HA = single-bit half adder.

shows the comparative analysis of the front-end designs of the 4 × 4 proposed GD multiplier against those of existing architectures in terms of delay and power consumption. From Table 2, it can be inferred that the GD multiplier requires a 29.93% reduction in computational time over the existing multiplier architectures without compromising power consumption. The same has been achieved through parallel computation, which is introduced during the decomposition of the groups of partial products. In the GD multiplier, full adder logic is reduced, and half adder logic is increased to balance the power consumption. The proposed GD multiplier architecture has a power–delay product that is 33.18% less than that of the Wallace multiplier and 25.91% less than that of the Dadda multiplier.

Table 3. Front-end performance analysis between GD and existing techniques with power and delay as parameters.

Parameters	Wallace Multiplier (8 × 8)	Dadda Multiplier (8 × 8)	GD Multiplier (8 × 8)
Delay (ns)	13.527	12.631	5.5199
Power (nW)	7.082	7.0370	7.9955
Power–Delay Product (PDP) (10−15)	0.0950	0.0888	0.0413
Hardware Requirements	2 i/p AND gate = 64	2 i/p AND gate = 64	2 i/p AND gate = 64
	FA = 53	FA = 48	FA = 54
	HA = 8	HA = 8	HA = 18

shows the comparison of the front-end design parameters of the GD multiplier (8 × 8) against those of the existing architectures. When compared with the existing multiplier designs, the GD multiplier shows 59.19% and 56.29% decrease in computational time with respect to the Wallace and Dadda multipliers, respectively. The power consumption of the proposed multiplier is higher than that of the existing multiplier. The proposed multiplier consumes 13.76%and 13.62% more power compared to the Dadda and Wallace multipliers, respectively. Even though there is a tolerable increase in the power consumption of the proposed multiplier which is compensated by achieving less power–delay product in the GD multiplier against the existing architectures. PDP percentage reductions of 56.52% and 53.491% are achieved in the GD multiplier with respect to the Wallace and Dadda multipliers.

The bar graph shown in Figure 9 shows the percentage improvement of the proposed GD multiplier with respect to the existing multipliers in terms of power–delay product (PDP) and computational time. It can be inferred that with higher-order multiplication, the proposed multiplier shows a better improvement in terms of PDP and computational time. From the graph, one can see that the 8 × 8 architecture has an improvement of approximately 30% in performance parameters over the 4 × 4architecture of the proposed architecture.

3.3. Physical Design Implementation and Comparison Results against the Existing Multipliers

The physical design implementation of the 4 × 4 Wallace multiplier shown in Figure 10 is achieved through the interconnection of the schematic-driven layout of a two-input AND gates, a half adder, and a full adder cellas per the front-end design.

The physical design implementation of the 4 × 4 Dadda multiplier is shown in Figure 11. This is achieved through the interconnection of the schematic-driven layout of a two-input AND gate, a half adder, and a full adder cell, as per the front-end design.

The physical design implementation of the 8 × 8 GD multiplier is shown in Figure 12. This is achieved through the interconnection of the schematic-driven layout of 4 × 4 Wallace and Dadda multipliers, a half adder, and a full adder cell, as per the front-end design.

Table 4. Back-end design performance comparison between the proposed multiplier and existing multiplier techniques.

Parameters	Wallace Multiplier (8 × 8)	Dadda Multiplier (8 × 8)	GD Multiplier (8 × 8)
Computational time (ns)	10.511	9.824	5.5159
Power consumption (nW)	7.1336	7.1390	8.1154
Area consumption (mm2)	2.1304	2.0092	2.3638
Power–delay product (PDP) (10−15)	0.0749	0.0713	0.0249

shows the back-end design comparison between the proposed GD multiplier and the existing Wallace and Dadda multipliers. The back-end design shows that a computational time reduction of 43.85% compared to the Dadda and a 47.52% reduction compared to the Wallace is achieved with the proposed GD multiplier. Also from the results, it can be observed that the post-layout design of both the proposed and existing architecture consume approximately 1.5% more power compared to the front-end design of the same, which is due to the routing of interconnecting nets. The power–delay product of the proposed GD multiplier shows 66.7% and 65.07% improvement with respect to the Wallace and Dadda multipliers, respectively. The Dadda multiplier consumes less silicon area compared to the other two multipliers due to the requirement for fewer single-bit adders in the design. The GD multiplier consumes more silicon area, approximately 15%, as compared to other two multipliers. This is caused by the greater amount of logic involvement required by the grouping and decomposition stage. However, if the order of the multiplication increases, the other two multipliers may consume more silicon area as compared to the proposed architecture since a greater amount of layer-reduction is required, whereas the proposed architecture always has a fixed amount of layer-reduction, irrespective of the order of the multiplication.

4. Conclusions

This research work proposes a high-speed binary multiplier that uses a grouping and decomposing algorithm. The proposed multiplier was implemented in a 180nm CMOS process. The comparative analysis of the front-end architecture of the proposed multiplier shows that it consumes 56.29% less computational time and 53.49% less power–delay product as compared to the existing parallel architectures. The proposed multiplier can parallelly execute the reduction of bits, regardless of the total number of partial products, using the grouping and decomposition algorithm. The physical design implementation of the proposed GD multiplier shows a reduction of 47.52% and 43.85% in computational time when compared to the Wallace and Dadda multipliers, respectively. A comparative analysis of the proposed architecture with existing multipliers shows that the parallel working of the grouping and decomposition algorithm makes the proposed multiplier outperform existing multipliers, such as Wallace, Dadda, etc. Therefore, it is preferable for high-speed VLSI applications.