The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology

Abstract

In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.

1. Introduction

Electrostatic discharge (ESD) remains a challenge in terms of the reliability and robustness of integrated circuits (ICs). The scaling down of dimensions, the increasing integration density, and the new production process make the circuits more sensitive to ESD stress [1]. An ESD device is needed to protect a pin in ICs. To protect the internal circuits and avoid latch-up issues, the trigger voltage (V_t1) of the ESD device must be greater than the supply power and lower than the breakdown voltage; the holding voltage (V_h) of the ESD device must be greater than the power supply voltage [2,3]. The silicon-controlled rectifier (SCR) device has been widely used as an efficient ESD protection structure for its high ESD robustness within a small silicon footprint, however, the high trigger voltage and a low holding voltage have limited use. The RC trigger circuit has been coupled to the SCR component, allowing the trigger voltage of the SCR to be decreased [4]. And the diode-triggered SCR (DTSCR) can adjust the trigger voltage by using a chain of diodes to trigger [5,6,7], however, the leakage current is at a high level. The low-voltage triggered SCR (LVTSCR) [8,9,10] has been proposed, which involves integrating a MOS configured in a grounded-gate N-channel metal-oxide-semiconductor (GGNMOS) across the P+/N-well junction. Similarly, a pMOS component can also be integrated. A dual-direction SCR (DDSCR) is suited to protect circuits from the two polarities of ESD stress [11,12,13]. The same scheme to reduce V_t1 by embedding the MOS in SCR can be used for DDSCR. The optimized pMOS-triggered bidirectional SCR (PTBSCR) fabricated in a 0.18 μm CMOS process uses symmetrical stacked SCR and pMOS to reduce the trigger voltage and improve the holding voltage [14]. The ESD design concept of ESD on the CMOS process can be applied to that on the silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process. Compared with the integrated protection network based on diodes, the localized protection approach that relies on devices is more suitable for the multiple power supply ICs in the SOI BCD process. The protection structures applied for a localized protection net should be bidirectional to provide protections from the two polarities of the discharge [15]. Thus, a dual-direction SCR is suited for a localized protection net.

However, most ESD protection structures fabricated in the SOI BCD process are designed for high-voltage applications [16,17,18], while the protection structures for a low-voltage applications’ process are rarely discussed. Embedding a pMOS in DDSCR can reduce V_t1 and increase the V_h, however, the effect of gate voltage on critical parameters for DDSCR is not investigated in detail. In addition, the influence of inserting shallow trench isolation (STI) in DDSCR has not been discussed.

In this paper, the PTBSCR is fabricated in a 0.18 μm SOI BCD process. This structure aims to protect the I/O pins of ICs in the SOI BCD process, and it shows a low trigger voltage and a high holding voltage in the transmission line pulsing (TLP) I-V curve. In addition, the device can protect a pin with an operating voltage varying between positive and negative values. The multi-snapback phenomenon of the device and the effects of gate voltage, layout parameter, and STI on the variation of V_t1 and V_h are discussed in detail. The technological computer-aided design (TCAD) simulation is carried out to obtain physical insight into the distributions of current density, the impact of ionization rate, the electric field, and the electrostatic potential of PTBSCR.

2. Test and Simulation Structure

The PTBSCR (with/without STI) is studied in this work. Figure 1 shows the cross-sectional view of the PTBSCR with STI. It consists of a bidirectional SCR, an embedded pMOS, and parasitic resistors. The DNW is a high-voltage isolation well. The NW1, NW2, NW3, PW1, and PW2 are low-voltage wells. The TR is the dielectric isolation ring. The STI is used to isolate the PN junction. The device is designed by using the existing layer. Therefore, the fabrication process of the device is fully compatible with the SOI BCD process. Some parameters of the PTBSCR are summarized in

Table 1. Some parameters of PTBSCR.

Parameters	Volume
TSi (μm)	1.5
TBOX (μm)	1.0
Tgate (nm)	14
TSTI (μm)	0.4
DNW/DPW (μm)	1.0
L1 (μm)	0.6
L2 (μm)	0.6

. The device can discharge an ESD current in dual directions and it is completely symmetrical. Figure 1 illuminates the equivalent circuit when terminal 1 (T1) is subject to a positive ESD stress and terminal 2 (T2) is grounded. When T1 of the PTBSCR is subject to a positive ESD stress and T2 is grounded, the voltage applied on the pMOS drain (P2+) will cause the trigger current to flow via the channel, and such a current flow will trigger the internal parasitic device. The poly-silicon gate on top of the NW2 region is the third terminal, which provides additional voltage to turn the pMOS on/off.

The concentrations, depths, and dimensions of the simulation structure are the same as the test structure. Through 2D simulation, the distribution of current, electric field, and avalanche impact ionization under an ESD current pulse can be used to analyze the ESD mechanism of PTBSCR.

3. Experimental Results and Analysis

3.1. The Multiple Snapback Characteristic

The measurements are targeted to the human body model (HBM) and conducted using the TLP test system HOXI-I with a pulse width of 100 ns and a rise time of 5 ns. The TLP test system measures I-V characteristics of the device when T1/T2 is subject to a positive ESD stress, the T2/T1 and G are grounded. As shown in Figure 2, the test curve presents a multi-snapback phenomenon, and the holding point after the second snapback reaches the lowest voltage. The double snapback has been observed in a double-snapback silicon-controlled rectifier (DSSCR) [19] and a GGNMOS triggered silicon-controlled rectifier (GGSCR) [20], where both of the structures have introduced the MOS-trigger mechanism. The double snapback in these two structures was caused by a progressive turn-on sequence of parasitic nMOS and an SCR, which were investigated by analyzing the current distribution of structures at different current levels. The same method can be used to analyze the multi-snapback phenomenon in PTBSCR.

To support and analyze the experimental phenomenon, TCAD simulation is carried out. The simulation method is named the multi-current pulse simulation method. In the method, a customized piecewise linear function (PWL) is used to generate the TLP current pulse which is applied to the T1 electrode. Other electrodes, including the T2 and G, are connected to the ground (0 V). The same mechanism applies to the ESD stress zapping at T2 when T1 and G are grounded. The underlying physical mechanism can be explained by the current distribution of PTBSCR under an increasing simulated pulsing current.

As shown in Figure 3, the PTBSCR passes through four different conduct phases as the pulsing current increases. Figure 3a illuminates before the other parasitic structure is triggered by the current that flows through the parasitic pMOS (composed of P2+, NW2, and P3+) when T1 is subject to positive ESD stress. The holes are injected into NW2 by PW1 and picked up by P3+. As shown in Figure 3b, current flows, and more broadly, the parasitic PNP BJT is triggered. Thus, the first snapback is caused by the trigger of PNP BJT. As the current increases, the current path is widened, as shown in Figure 3c. The holes drift the PW2 towards the N2+, which generates a voltage drop across the PW2 resistance R4. The voltage drop raises the local potential in PW2 and leads the PNPN structure (composed of P1+, NW2, PW2, and N2+) to trigger on. According to the avalanche impact ionization distribution of Figure 4, the impact ionization rate appears to be largest at the junction of NW2/PW2 on the current flow path, where the holes accelerate and a collision impact occurred. Then holes accumulate at PW2 until the parasitic NPN BJT (composed of NW2, PW2, and N2+) turn-on, then the NPN BJT forms positive feedback with PNP BJT (composed of P2+, NW2, P3+). Thus, it can be concluded that the NPN (composed of NW2, PW2, and N2+) is triggered earlier. Thus, the second snapback is caused by the turn-on of the PNPN structure. As shown in Figure 3d, the current flow through R2 generates a voltage drop across the PW1 and turns on the parasitic NPNP structure, (composed of N1+, PW1, NW2, and P3+), Thus, the third snapback happens due to the turn-on of the NPNP structure.

The physical failure analysis (PFA) was carried out after the TLP test. Three metal layers have been removed to locate the failure spots. As shown in Figure 5, the failure spots caused by silicon melting appear in the junctions of the NW2/PW2 and N1+/PW1. As shown in Figure 4, the electric field at the reverse-biased NW2/PW2 junction is larger than other positions (impact ionization is related to the electric field), and the current almost flows through these reverse-biased PN junctions, as shown in Figure 3d. The heat generated at the reverse-biased junction is the product of high-voltage dropping on the junction and a high ESD current, which causes temperature rises until silicon melting. The distributions of failure spots have indirectly verified the accuracy of simulated results in Figure 3 and Figure 4.

3.2. The Effect of Gate Voltage on Snapback Voltage

3.2.1. The Measured TLP Results

To investigate the effect of gate voltage on the ESD characteristics of the structure, the I-V curves of PTBSCR are measured when T1 is subject to a positive ESD stress, G is subject to a different voltage, and T2 is grounded. The multi-snapback phenomenon exists in curves with different gate voltages (gate voltage means the DC voltage applied on the G electrode) in Figure 6. Therefore, the voltage that applies to the gate has no effects on the work scheme of PTBSCR in ESD stress. In addition, it can be seen that the V_t1 and V_h of the device decrease regularly with decreasing gate voltage.

Figure 7 presents the effects of L and gate voltage on the V_t1/V_h. The value of V_t1 (V_G = 0 V) can decrease from 8.1 V to 6.2 V with L decreasing from 1.5 μm to 0.5 μm. The total reduction is about 1.9 V, and accounting exceeds 23.0% of V_t1 (L = 1.5 μm, V_G = 0 V). The value of V_h (V_G = −1 V) can increase from 4.5 V to 4.9 V with L increasing from 0.5 μm to 1.5 μm. The total rise is about 0.4 V, and accounting exceeds 9.6% of V_h (L = 0.5 μm, V_G = −1 V). The value of V_t1 (L = 0.5 μm) can reduce from 6.2 V to 4.6 V with gate voltage decreasing from 0 V to −5 V. The total reduction is about 2.0 V, and accounting exceeds 25.8% of V_t1 (V_G = 0 V, L = 0.5 μm). The value of V_h (L = 1 μm) can increase from 4.3 V to 5.2 V with gate voltage increasing from −5 V to 0 V. The total rise is about 0.8 V, and accounting exceeds 19.5% of V_h (V_G = −5 V, L = 1 μm). The above results indicate that the values of V_t1/V_h can be adjusted via gate voltage and the length of L in a large range.

3.2.2. The Influence of Gate Voltage on V_t1 and V_h

The influence mechanism of gate voltage on trigger characteristics of nMOS has been analyzed in [21,22]. Because the first trigger behavior of PTBSCR is governed by the pMOS, the same analysis scheme of nMOS can be used to study the trigger behavior of pMOS. The I_ds of pMOS play a crucial part in reducing the V_t1 because the I_ds is the main contributor to the increase of the incident current I_p for the avalanche multiplication at the NW2/PW2 junction. The avalanche generation current I_gen is related to the incident current I_p and the avalanche multiplication factor M by:

I_gen = (M − 1)I_p

(1)

Before the turning on of BJT, body current I_Body = I_gen. A gate voltage V_G greater than the pMOS threshold voltage V_th will result in a pMOS current I_ds. The I_p is strengthened by I_ds, and a lower M can sustain the same I_Body. The increasing I_ds make the V_t1 decrease. Thus, the V_t1 of pMOS is initiated reducing with decreasing gate voltage. For the same reason, the V_t1 of PTBSCR is decreasing with the decreasing gate voltage.

According to the analysis before, the second triggering is caused by the turn-on of the PNPN structure (composed of P1+, NW2, PW2, N2+), and the holding point appears after the second triggering. Before the third snapback, the current flows through P1+, PW1, NW2, PW2, and N2+ and the voltage drop on the reverse-biased NW2/PW2 junction contributes the most to the holding voltage. We chose the same pulsing current to analyze the distribution of electric field and electrostatic potential when applying the different gate voltages. As shown in Figure 8a–d, gate voltage has an evident influence on the electric field distribution in NW2/PW2. The gradually weakened electric field in the NW2/PW2 junction will induce the undermined electrostatic potential with reducing gate voltage. In Figure 9a–d, the electrostatic potential in NW2/PW2 is gradually decreasing with reducing gate voltage, and the V_h of PTBSCR is decreasing with the decreasing electrostatic potential in NW2/PW2.

3.3. The Results Difference Caused by STI Isolation

To investigate the influence of STI on critical parameters, the TLP I-V curves of structures (with/without STI) are measured. Figure 10 shows the test curves of different devices. The TLP test system measures I-V characteristics of the devices when T1 is subject to a positive ESD stress, the T2 and G are grounded. The multi-snapback phenomenon of the I-V curve exists in structures with or without STI. In addition, inserting STI decreases the V_t1 and increases the V_h. The first snapback is caused by the turn-on of PNP BJT. The STI inserted in the device is used to isolate the PN junction. The P1+/N1+ junction of PTBSCR without STI consumes the voltage drop on the current flow path, which reduces the voltage drop on the NW2/PW2. Thus, the device without STI triggers with more difficulty. Thus, the V_t1 of PTBSCR with STI is smaller. After being triggered completely, the STI increases the current path, and thus, the V_h is larger.

Figure 11 shows the effect of gate voltage on the V_t1 and V_h of PTBSCR (with/without STI). As expected, the V_t1 and V_h of the device have decreased regularly with a decreasing gate voltage. The V_t1 decreases from 6.2 V/7.0 V to 4.6 V/4.8 V. The V_h decreases from 5.1 V/4.6 V to 4.3 V/3.8 V when gate voltage decreases from 0 V to −5 V.

4. Conclusions

The multi-snapback phenomenon of PTBSCR in the 0.18 μm SOI BCD process was investigated in this work. The ESD characteristics of PTBSCR were verified by the TLP measurement and TCAD simulator. The structure offered a low trigger voltage and a high holding voltage to satisfy the ESD design window. The multi-snapback phenomenon of the device can be explained by the non-simultaneous trigger of the parasitic structure in the current path. The decreasing gate voltage increased channel current and weakened the electric field, therefore decreasing V_t1, V_h. Inserting STI reduced the voltage drop on the P1+/N1+ junction, and increased the current flow path. Thus, inserting STI decreased the V_t1, and increased V_h. The effects of gate voltage, inserting STI, and channel length on ESD characteristics of PTBSCR is useful to design low-voltage ESD protections in SOI BCD ICs.