A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Round 1

Reviewer 1 Report

Very good idea and work has been presented by the authors. In my opinion, some corrections are needed as follows:

• There exist some grammatical errors in the manuscript that can be easily corrected by the authors. For example, in the last paragraph of Section 1, the words “the proposed the differential …” must be changed to “the proposed differential …”.
• As it is stated in the beginning of Section 2, bridge DAC capacitor array consisting of 8-bit MSB and 4-bilt LSB arrays are utilized in this work. Could the authors explain about this decision? What is the main reason for designing the circuit with 8-bit MSB and 4-bit LSB arrays?
• I suggest to redraw Figure 1 for more visibility. I think the illustration of capacitor DACs can be redrawn in such a way that can improve the overall architecture.
• Can the authors provide more explanation regarding the effect of Cp1 on the linearity of proposed ADC and as well as solution to overcome this issue?
• It is better to provide transistor dimensions as well value of resistors in Figs. 12, 13, 16, and 18.
• Regarding resistors R1-6, I am worried about the circuit realization as well as their mismatches.
• Although measurement results are reported in the work, I am eager to see some simulation results including process corners, Monte Carlo analysis, as well as behavior of designed circuit versus different temperatures.
• Although the FOM for ADCs is well-known, but I suggest to put the FOM relation in the manuscript.
• I suggest to compare the presented work with more similar designs that can be found in the literature. Please also report the linearity, INL, DNL, die area, and total amount of capacitors used in each work in Table 2.

 

Author Response

Please see the attachment

Author Response File: Author Response.pdf

Reviewer 2 Report

The level of novelty of the paper is limited and referred to the DAC capacitor array. Anyway, the presence of a test chip and respective measurements make the work highly valuable for publication in MDPI Electronics after the following points are addressed.

1)  The comparison with the state-of-art is limited and so,  and the number of references too. Please, at least double the number of citing papers according to a proper state-of-art definition.
For instance, the authors may refer to SAR ADC having similar performance (in terms of ENOB) a from Electronic MDPI (i.e. https://doi.org/10.3390/electronics9010199 and  https://doi.org/10.3390/electronics9071100 ) and IEEE  (i.e. 10.1109/ACCESS.2020.2986949 )

2) Please, after having extended the comparison with the state of art, please extend accordingly the comparison table.
Also, revise it including other valuable (and missing) parameters 
(i.e. area and THD among the others) 

Author Response

Please see the attachment

Author Response File: Author Response.pdf