A Design Methodology for Wideband Current-Reuse Receiver Front-Ends Aimed at Low-Power Applications

This work gives a design perspective on low-power and wideband RF-to-Baseband current-reuse receivers (CRR). The proposed CRR architecture design shares a single supply and biasing current among both LNTA and baseband circuits to reduce power consumption. The work discusses topology selection and a suitable design procedure of the low noise transconductance amplifier (LNTA), down-conversion passive-mixer, active-inductor (AI) and TIA circuits. Layout considerations are also discussed. The receiver was simulated in 130 $\mathrm{n}$$\mathrm{m}$ CMOS technology and occupies an active area of 0.025 ${\mathrm{mm}}^2$. It achieves a wideband input matching of less than $-10$ $\mathrm{d}$$\mathrm{B}$ from $0.8$ $\mathrm{G}$$\mathrm{Hz}$ to $3.4$ $\mathrm{G}$$\mathrm{Hz}$. A conversion-gain of $39.5$ $\mathrm{d}$$\mathrm{B}$, IIP3 of $-28$ $\mathrm{d}$$\mathrm{Bm}$ and a double-sideband (DSB) NF of $5.6$ $\mathrm{d}$$\mathrm{B}$ is simulated at a local-oscillator (LO) frequency of $2.4$ $\mathrm{G}$$\mathrm{Hz}$ and an intermediate frequency (IF) of 10 $\mathrm{M}$$\mathrm{Hz}$, while consuming $1.92$ mA from a $1.2$ $\mathrm{V}$ supply.