Experimental Analysis of Oxide-Based RAM Analog Synaptic Behavior

Round 1

Reviewer 1 Report

Neural network was used in the study. The results of the study have not been proven to be successful. There is no performance comparison with different approaches. When evaluated from these perspectives, it is not innovative. It does not make a significant contribution to the literature. The introduction section is very short and inadequate. This study is as a conference paper. That's why I think it's unacceptable.

Author Response

Neural network was used in the study. The results of the study have not been proven to be successful. There is no performance comparison with different approaches. When evaluated from these perspectives, it is not innovative. It does not make a significant contribution to the literature. The introduction section is very short and inadequate.

Thank you for the feedback.

This paper addresses neuromemristive systems which are based on a design approach with closely coupled resistive memory and processing. Neuromemristive are meant to go beyond non-Von Neumann (non-VN) architectures. Building neuromemristive systems relies on the emulation of a synapse in the form of a two-terminal device and this paper analysis this specific aspect. To the authors' knowledge, the topic sounds and is currently and extensively addressed in the community.

We add the following paragraphs to complete the introduction and replace it in the context:

A recent advance in the field of OxRAM memories is related to the possibility of Multi Level Cell (MLC) conductance, needed for the implementation of synaptic weight quantization. According to this approach, more than two data conductance states are made possible, simply by finely controlling the programming of the cell. Thus, OxRAMs can be considered as a time variable resistor, which makes the technology a potential candidate for implementing conventional ANNs.

 At a circuit level, different conductance modulation techniques can be adopted. Conductance modulation can be achieved by: (i) applying an increasing number of identical voltage pulses across the OxRAM. In this case, conductance levels are function of the number of pulses [1], (ii) directly modulating  the programming voltage levels [2], (iii) modulating the compliance current of the memory cell during programming operations [3]. The first approach requires an embedded pulse generator while the two others require analog voltage levels generated from a specific circuitry.

Despite the advances made in this field, there are still open issues that are currently under investigations. The most important one is related to the variability of the OxRAM technology, which leads to synaptic weight precision reduction [4][5].

[11] H. Aziza, A. Perez, J.M. Portal, “RAMs as Analog Trimming Elements” – Journal of Solid-State Electronics, vol. 142, pp. 52-55, 2018.

[12] Cong Xu, Dimin Niu, N. Muralimanohar, N. P. Jouppi and Yuan Xie, "Understanding the trade-offs in multi-level cell ReRAM memory design," 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, pp. 1-6.

[13] W. Chen et al., “Switching characteristics of W/Zr/HfO2/TiN ReRAM devices for multi-level cell non-volatile memory applications”, Semiconductor Science and Technology.

[14] Zhang, Y.; Cui, M.; Shen, L.; Zeng, Z. Memristive Quantized Neural Networks: A Novel Approach to Accelerate Deep Learning On-Chip. IEEE Trans. Cybern. 2019, 51, 1875-1887.

[15] Yu, S.; Jiang, H.; Huang, S.; Peng, X.; Lu, A. Computing-in-memory chips for deep learning: Recent trends and prospects. IEEE  Circuits Syst. Mag. 2021, 21, 31-56

This study is as a conference paper. That's why I think it's unacceptable.

This paper evaluates the capability of a Resistive RAM technology (OxRAM) to be used as a synapse. Chips have been fabricated and experimental data are provided after extensive measurements. An interesting angle is adopted by evaluating the impact of variability on the OxRAM conductance, which lead the authors to perform an important amount of measurements in order to propose a statistical analysis.

The amount of data provided, combined with the variability study makes our contribution far from a conference paper, provided that we are talking about low-level conferences.

Reviewer 2 Report

The work titled “Experimental Analysis of Oxide-based RAM Analog Synaptic Behavior” by Aziza et al. reports experimental analysis of the multi-level conductance tunability of oxide-based memristive devices and its variability both in cycle-to-cycle and device-to-device. Although, for neuromorphic application, the write operations should be conducted in pulse mode, this work uses dc voltage sweep mode. Nevertheless, the data and analysis provided in in work are important repository that can be useful for many researchers in this field. I would like to recommend the work to be accepted providing several issues could be addressed.

1.     In Figure 2 for illustrating the use of memristive crossbar array to implement the neural network layer operations, the authors oversight an important issue that the conductance of the memristive device are always positive while the weights are singed numbers. This issue has mature solution, like using differential pair of memristors for a single weight (see, iScience, 23, 101809, 2020; H. Li et al., Adv. Intell. Syst., 3, 2100017, 2021).

2.     Write methods using DC voltage sweep are not convenient in integrated circuits. There are many other methods that uses voltage pulse to conduct the writing or weight update process. These methods should be discussed and compared (see F. Alibart, Nanotechnology, 23, 075201, 2012; V. Milo et al., IEEE Trans. Electron Devices, 68, 3832, 2021.)

3.     It is not clear what are the circles in Figure 9c and 9D.

4.     It is clear that the resistance follows logarithmic distribution as shown in Figure 5. Thus, when analyzing the resistance distribution as well as its trend with different write conditions (in Figure 9 and Figure 11), it is suggested to use the logarithmic scale of the resistance.

5.     There are some scrambled codes in Figure 1b.

Author Response

The work titled “Experimental Analysis of Oxide-based RAM Analog Synaptic Behavior” by Aziza et al. reports experimental analysis of the multi-level conductance tunability of oxide-based memristive devices and its variability both in cycle-to-cycle and device-to-device. Although, for neuromorphic application, the write operations should be conducted in pulse mode, this work uses dc voltage sweep mode. Nevertheless, the data and analysis provided in in work are important repository that can be useful for many researchers in this field. I would like to recommend the work to be accepted providing several issues could be addressed.

 

1. In Figure 2 for illustrating the use of memristive crossbar array to implement the neural network layer operations, the authors oversight an important issue that the conductance of the memristive device are always positive while the weights are singed numbers. This issue has mature solution, like using differential pair of memristors for a single weight (see, iScience, 23, 101809, 2020; H. Li et al., Adv. Intell. Syst., 3, 2100017, 2021).

Thanks for the feedback. We have already identified this limitation and figure out how to overcome it. Two options are available to this aim:

• Use the technique presented in [CHA] where the “signed weights” are handled at the CMOS neuron level. In [CHA], the neuron entry point is a differential OpAmp and the synapse is made by the combination of two Resistive RAM, each one feeding the inverting and non- inverting input of the OpAmp.
• There is an option in the Pytorch framework which allows to generate only positive weights during the training of a neural network. This option is convenient as the technique proposed in [CHA], which generates an area overhead, can be avoided.

 

[CHA]Chakrabarti, Bhaswar & Kataeva, Irina & Strukov, Dmitri. (2017). Memristor-based perceptron classifier: Increasing complexity and coping with imperfect hardware. 549-554. 10.1109/ICCAD.2017.8203825.

 

2. Write methods using DC voltage sweep are not convenient in integrated circuits. There are many other methods that uses voltage pulse to conduct the writing or weight update process. These methods should be discussed and compared (see F. Alibart, Nanotechnology, 23, 075201, 2012; V. Milo et al., IEEE Trans. Electron Devices, 68, 3832, 2021.)

Indeed, voltage pulses are more efficient (speed) compared to a DC voltage sweep approach. However, to track accurately the resistance changes (i.e., synapse conductance change), authors find out that the DC voltage sweep approach is more reliable.

 

In order to address the first and second points, we complete the introduction with the following paragraphs and references:

A recent advance in the field of OxRAM memories is related to the possibility of Multi Level Cell (MLC) conductance, needed for the implementation of synaptic weight quantization. According to this approach, more than two data conductance states are made possible, simply by finely controlling the programming of the cell. Thus, OxRAMs can be considered as a time variable resistor, which makes the technology a potential candidate for implementing conventional ANNs.

 At a circuit level, different conductance modulation techniques can be adopted. Conductance modulation can be achieved by: (i) applying an increasing number of identical voltage pulses across the OxRAM. In this case, conductance levels are function of the number of pulses [1], (ii) modulating directly the programming voltage levels [2], (iii) modulating the compliance current of the memory cell during programming operations [3]. The first approach requires an embedded pulse generator while the two others require analog voltage levels generated from a specific circuitry.

In spite of the advances made in this field, there are still open issues that are currently under investigations. The most important one is related to the variability of the OxRAM technology, which leads to synaptic weight precision reduction [4][5].

[1] H. Aziza, A. Perez, J.M. Portal, “RAMs as Analog Trimming Elements” – Journal of Solid-State Electronics, vol. 142, pp. 52-55, 2018.

[2] Cong Xu, Dimin Niu, N. Muralimanohar, N. P. Jouppi and Yuan Xie, "Understanding the trade-offs in multi-level cell ReRAM memory design," 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, pp. 1-6.

[3] W. Chen et al., “Switching characteristics of W/Zr/HfO2/TiN ReRAM devices for multi-level cell non-volatile memory applications”, Semiconductor Science and Technology.

[4] Zhang, Y.; Cui, M.; Shen, L.; Zeng, Z. Memristive Quantized Neural Networks: A Novel Approach to Accelerate Deep Learning On-Chip. IEEE Trans. Cybern. 2019, 51, 1875-1887.

[5] Yu, S.; Jiang, H.; Huang, S.; Peng, X.; Lu, A. Computing-in-memory chips for deep learning: Recent trends and prospects. IEEE  Circuits Syst. Mag. 2021, 21, 31-56

 

3. It is not clear what are the circles in Figure 9c and 9D.

The circles can be associated with “outliers”. We decided to keep these values for the analysis, as the study targets the impact of the variability of the technology on the OxRAM conductance.

The following sentence is added in the legend of Figure 9: The circles represent outliers showing the strong variability.

 

4. It is clear that the resistance follows logarithmic distribution as shown in Figure 5. Thus, when analyzing the resistance distribution as well as its trend with different write conditions (in Figure 9 and Figure 11), it is suggested to use the logarithmic scale of the resistance.

Thanks for feedback. We try to plot our results in log scale but the range of resistance values is quite low so the figure was not clear to represent our results. Moreover, we have detected that Figure 9 and Figure 11 curves are really pseudo-linear, that’s why we have decided not to go with a log scale.

 

5. There are some scrambled codes in Figure 1b.

 

In our version, there is no scrambled code. Could you specify what is wrong?

Reviewer 3 Report

My comments are as follows:

This paper shows the experimental analysis of oxide-based RAM analog synaptic behavior using various test schemes. These experimental results are so interesting covering from semiconductor device to electrical measurement. Also, it should be considered that the array level electrical test is highly important issues for oxide-based RAM neuromorphic system. However, the presented data cannot fully support the claim. This work can be accepted after addressing the following issues.

 

(1) In this experiment, the author used the HfO2-based RAM vertical device. And, this device shows the bipolar switching properties by external electric field. However, in set region, the abrupt change of current is observed, which means that the existence of analog switching behavior is very difficult to obtain. It is should be mentioned.

 

(2) In Fig. 5, the variability of HRS is huge compared than that of LRS. What is the reason for that.

Author Response

My comments are as follows:

This paper shows the experimental analysis of oxide-based RAM analog synaptic behavior using various test schemes. These experimental results are so interesting covering from semiconductor device to electrical measurement. Also, it should be considered that the array level electrical test is highly important issues for oxide-based RAM neuromorphic system. However, the presented data cannot fully support the claim. This work can be accepted after addressing the following issues. 

 

(1) In this experiment, the author used the HfO2-based RAM vertical device. And, this device shows the bipolar switching properties by external electric field. However, in set region, the abrupt change of current is observed, which means that the existence of analog switching behavior is very difficult to obtain. It is should be mentioned.

Indeed, during the SET operation, an abrupt change of the current is observed. However, we have identified a region of variation (between 12.5 kohms and 40 kohms, see Figure 11a and   Figure 11b), where the conductance modulation in LRS state can be exploited. Beyond this resistance range, the resistance variation slope is too important to consider conductance modulation.

Text Added in Section 4.2: “A region of resistance variation has been identified (between 12.5 kohms and 40 kohms, see Figure 11a and Figure 11b), where the conductance modulation in LRS state can be exploited. Beyond this resistance range, the resistance variation slope is too important to consider conductance modulation.”

(2) In Fig. 5, the variability of HRS is huge compared than that of LRS. What is the reason for that.

This is a common feature of the technology and reported in many studies. This is attributed to a partial dissolution of the conductive filament responsible of the HRS/LRS state resistances values [LUL]. From a physical point of view, when a voltage is applied across the OxRAM cell (i.e., between the TE and BE electrodes), depending upon the voltage polarity, one or more Conductive Filaments (CFs) made out of oxygen vacancies are either formed or ruptured. Once the CFs are formed inside the metal oxide to bridge the top and bottom electrodes, current can flow through the CFs, to switch the cell in a low resistance state. On the other hand, the rupture of the CF stops the current flow. At this level, the high HRS variability is explained as an incomplete destruction of the CFs. In other words, the formation process of the CFs is more “robust” compared to the destruction process of the CFs.

[LUL]Salaoru, Iulia & Khiat, Ali & Berdan, Radu & Li, Qingjang & Papavassiliou, C. & Prodromakis, Themis. (2014). Origin of the OFF state variability in ReRAM cells. Journal of Physics D Applied Physics. 10.1088/0022-3727/47/14/145102.

Round 2

Reviewer 1 Report

No corrections have been made to address my criticisms. This article is not acceptable.

Reviewer 2 Report

The authors have addressed all raised issues in previous review round. I don't have further comments.