A Low-Voltage Class-D VCO with Implicit Common-Mode Resonator Implemented in 55 nm CMOS Technology

Round 1

Reviewer 1 Report

In this paper, the authors are propose a Class-D voltage-controlled oscillator (VCO) using power-supply noise rejection techniques that generate high resistance at the second harmonic of the output frequency. In this study, suppressing the second harmonic by implicit common-mode resonator technology not only improves the phase noise of the VCO, but also saves the redundant area brought by the additional inductance. For the experimental evaluation, we perform a comparative analysis with the experience of previous use.

1. The industrial applicability of this paper is rather shallow, based on the fact that the proposed VCO has lower phase noise compared to the original class-D VCO.

2. The VCO design proposed by the authors for a 55-nm CMOS process is used to represent their contribution.

3. The keywords "VCO" and "Class D" mentioned in this article are not clear enough. It is suggested that the keywords for abbreviation should be listed as full nouns. For example, FoM should list "figure of merit (FoM)".

4. In general, I think the experimental system proposed by the author is consistent with the experimental results of the reference values. I think the abstract of the manuscript need to be written and revised for clarity before being accepted for publication in “electronics” of journal.

In this paper, the authors are propose a Class-D voltage-controlled oscillator (VCO) using power-supply noise rejection techniques that generate high resistance at the second harmonic of the output frequency. In this study, suppressing the second harmonic by implicit common-mode resonator technology not only improves the phase noise of the VCO, but also saves the redundant area brought by the additional inductance. For the experimental evaluation, we perform a comparative analysis with the experience of previous use.

1. The industrial applicability of this paper is rather shallow, based on the fact that the proposed VCO has lower phase noise compared to the original class-D VCO.

2. The VCO design proposed by the authors for a 55-nm CMOS process is used to represent their contribution.

3. The keywords "VCO" and "Class D" mentioned in this article are not clear enough. It is suggested that the keywords for abbreviation should be listed as full nouns. For example, FoM should list "figure of merit (FoM)".

4. In general, I think the experimental system proposed by the author is consistent with the experimental results of the reference values. I think the abstract of the manuscript need to be written and revised for clarity before being accepted for publication in “electronics” of journal.

Author Response

Dear Reviewer:

Thank you for your thoughtful reading and professional advice. Your opinions give me a lot of inspiration to improve my article. We have carefully considered all comments from the reviewers and revised our manuscript accordingly. The manuscript has also been double-checked, and the typos and grammar errors we found have been corrected. Next is my manuscript revision of your comments or my response to your questions.

Point 1

The industrial applicability of this paper is rather shallow, based on the fact that the proposed VCO has lower phase noise compared to the original class-D VCO.

Response to point 1

Please forgive our shallow knowledge of the current industry. The original intention of designing with this innovative point is to see that in recent years, well-known journals/conferences such as JSSC and ISSCC have become more and more popular in the application of multi-peak resonance technology in the field of VCO. We hope to use this popular technology in the field of low-voltage VCO as well. However, we also understand that the circuit structure has some advantages, but it is still too early to achieve the widely recognized advantages of the industry. On this basis, we will further improve our design.

Point 2

The VCO design proposed by the authors for a 55-nm CMOS process is used to represent their contribution.

Response to point 2

Due to the limitation of our own conditions, SMIC 55-nm process is the closest to other low-voltage VCO technology processes that we refer to. We believe that similar processes can also increase the persuasion of the superiority of the structural design. However, we also understand that this result can be recognized by more people if the TSPC 65-nm process is used. When opportunity matures, we plan to use the TSPC 65-nm process for design .

Point 3

The keywords "VCO" and "Class D" mentioned in this article are not clear enough. It is suggested that the keywords for abbreviation should be listed as full nouns. For example, FoM should list "figure of merit (FoM)".

Response to point 3

Thank you for your reminding. We checked the manuscript again to make sure that the abbreviation of the professional term came with his complete statement when it first appeared in the body. At the same time, to ensure the conciseness of the full text, the professional terms after it remains abbreviated.

Point 4

In general, I think the experimental system proposed by the author is consistent with the experimental results of the reference values. I think the abstract of the manuscript need to be written and revised for clarity before being accepted for publication in “electronics” of journal.

Response to point 4

Thank you for your approval. Since you did not specify where the abstract needs to be modified, we have made appropriate changes after referring to the abstracts of several other Electronics articles. If you have any specific comments on the changes, please contact us.

Thank you for your time and effort. We hope that our responses and modifications will address your concerns well and our revised manuscript can be accepted for publication.

Yours sincerely,

Haotang Xu

14 May. 2023

Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

Email: [email protected]

Reviewer 2 Report

The authors claim to report the design of an oscillator with miniaturized area and superiror performance. y,the proposed VCO exhibits lower phase 5

noise compared to the original Class-D VCO, and also has many different advantages compared to 6

low-voltage VCOs produced by similar technology processes. The results look promising and will be of interest to readers. However, some more details on metrology should be provided.

The calibration methodology and criteria should be provided. Further, some more notes on the tuning range should be provided. What can be done to improve it further? 

Author Response

Dear Reviewer:

Thank you for your thoughtful reading and professional advice. Your opinions give me a lot of inspiration to improve my article. We have carefully considered all comments from the reviewers and revised our manuscript accordingly. The manuscript has also been double-checked, and the typos and grammar errors we found have been corrected. Next is my manuscript revision of your comments or my response to your questions.

Point 1

some more details on metrology should be provided.The calibration methodology and criteria should be provided.

Response to point 1

Thanks for your advice. EMX simulation results of inductance value L and quality factor Q for two inductances of the transformer are added in section 3. At the same time, we add a part to explain why transformers need to be designed in this form and how the EMX parameters of the final transformer can help the overall performance of VCO. For VCO performance parameters, we think that tuning range, phase noise, DC power consumption and FoM/FoMT can basically fully represent the performance of the VCO. If you have more advice on it, please contact us.

Point 2

some more notes on the tuning range should be provided. What can be done to improve it further?

Response to point2

In the case of inductance determination, if we want to increase the slope of each tuning curve, this requires us to increase the ratio of the variable capacitance to the total capacitance and the effect of the variable capacitance on the total capacitance. However, in order to maintain band stability, increasing the variable capacitance necessarily means reducing the capacitance at each end of the switched capacitor array, which results in each tuning curve pulling in each other and possibly decreasing the overall tuning range. Therefore, the direct way to increase the tuning range is to increase the Bit number of the switched capacitor array, but the VCO with more bits of the switched capacitor array also needs the cooperation of automatic frequency calibration(AFC) technology in testing and using. Due to the lack of relevant technology providers, only 4-bit array size is used.

Thank you for your time and effort. We hope that our responses and modifications will address your concerns well and our revised manuscript can be accepted for publication.

Yours sincerely,

Haotang Xu

14 May. 2023

Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

Email: [email protected]