New Methodology for Parasitic Resistance Extraction and Capacitance Correction in RF AlGaN/GaN High Electron Mobility Transistors

Abstract

This paper presents a novel approach to the efficient extraction of parasitic resistances in high electron mobility transistors (HEMTs). The study reveals that the gate resistance value can be accurately determined under specific forward gate bias conditions (V_g = 1.0 V), although the gate resistance value becomes unreliable beyond this threshold (V_g > 1.0 V) due to potential damage to the Schottky contact. Furthermore, by examining the characteristics of the device under a cold-FET bias condition (V_ds = 0 V), a linear correlation between the gate and drain current is identified, enabling an estimation of the interdependence between the drain and source resistance using the proposed method. The estimation of parasitic pad capacitance (C_pg and C_pd) from Dambrine’s model is refined by incorporating the depletion layer capacitance on the gate side during the pinch-off condition. To validate the accuracy of the extracted parasitic capacitance and resistance values obtained from the new method, small-signal modeling is performed on a diverse range of measured devices.

1. Introduction

Gallium nitride high electron mobility transistors (GaN HEMTs) have been extensively applied in microwave and millimeter-wave power amplifiers due to their high-power density and high-frequency features, making them suitable for applications such as communication, radar, and satellites [1,2,3,4]. Even without doping, the AlGaN/GaN heterostructure’s large conduction band discontinuity (which is related to the difference in electron affinities between the two materials), combined with large piezoelectric and spontaneous polarization effects, result in the formation of an extremely high-density two-dimensional electron gas (2DEG) [5,6]. The high density of 2D electron gas (2-DEG), caused by strong spontaneous and piezoelectric polarization, results in the normal ON operation of AlGaN/GaN HEMTs. However, this operational mode is not suitable for power electronic applications due to safety and system cost considerations. The utilization of GaN-based HFETs shows significant promise in radio-frequency (RF) power and switching applications. The continuous advancements in semiconductor epitaxy, device processing, and system integration have led to the emergence of an industrial supply chain specifically for GaN power devices. It is widely assumed that an appropriate extraction technique for a robust small-signal equivalent circuit is critical for circuit design, process technology assessment, and device performance optimization [7,8]. Such small-signal modeling should encompass a circuit-level description of the device’s nonlinear properties. Small-signal equivalent circuit modeling plays a crucial role in gaining valuable insights into device nonlinearity, particularly in the static sense, when conducted under different bias conditions. It is evident that the accuracy of the small-signal extraction method employed directly impacts the validity of the device modeling.

The important characteristics of AlGaN/GaN HEMTs are high sheet carrier density (n_s >> 1 $\times$ 10¹³ cm⁻²) that produces high I_max, mobility of electron is high ($\mu >$ 1500 cm²/V_s) which suitable for low on-resistance (R_on), high breakdown voltage and high operating channel temperature [9,10,11]. Several groups have investigated the high-performance DC analysis of AlGaN/GaN HEMTs [12,13]. Nonetheless, the theoretical studies of AlGaN/GaN transistor at high temperatures are not developed fully. Ensuring accurate measurements of S-parameters is crucial for determining realistic equivalent circuit parameters. Only with accurate S-parameter measurements can the extracted values hold meaningful physical significance. The accurate characterization of S-parameters serves as a foundation for obtaining reliable and meaningful equivalent circuit parameters.

Moreover, for accurate small-signal models, accurate extraction of parasitic resistances, capacitances, and inductances is required, which affects the whole RF characteristics of the devices. To element the effect of the parasitic components from the DUT, several methods have been discussed in the literature, such as open-short, two-step, and three-step de-embedding techniques [14,15,16,17]. At the beginning, the conventional de-embedding method was used to determine the Y-parameters, but it was only counting the capacitances act as a open circuit ignoring the effect of inductance present in the circuit. Koolen et al. [18], described the efficient analysis of determining parasitic components by considering impedance (Z) which induced in the circuit. They developed the model both considering ‘open’ interconnect pattern (Y_open) as well as ‘short’ pattern (Y_short) to determine the parasitic admittance. This method is still used in the industry for eliminating parasitic components. However, this method’s limitation is to use test dummy pattern which reduces accuracy in high frequencies.

Two step de-embedding [19] method required different calibration types such as SOLT (Short, Open, Load, Thru), TRL (Thru, Reflect, Line) and TRM (Thru, Reflect, Match) chosen to determine accuracy. This method uses only two dummy structures, Pad-Open and a complete short. The Pad-open dummy pattern uses to remove pad parallel impedance and the second one is for removing the series impedance of the interconnection between the line and the DUT (device under test). However, the problem is imperfection of dummy can cause inaccurate calculation of the parasitic components.

In the case of bipolar junction transistor (BJT), more accurate interpretation of S-parameter measurements by employing a three-step de-embedding procedure [16,17]. This procedure involves subtracting the y-parameters of the open circuit, as well as subtracting the z-parameters obtained from on-wafer shorts and through measurements of the Device Under Test (DUT). By considering the physical origins of y- and z-parameters, this three-step approach offers a more desirable solution for achieving accurate results. The steps include subtracting the on-wafer open y-parameters that affect the input and output ports, followed by subtracting the on-wafer z-parameters. This de-embedding technique requires four patterns such as open, thru, short1 and short2. While the three-step de-embedding methods mentioned earlier offer improved characterization of pad contacts in the measurement structure, they have limitations when it comes to achieving high accuracy in the millimeter-wave frequency range. This is mainly due to their reliance on a lumped-parameter interconnection model, which becomes less accurate in higher frequencies. Therefore, these methods are not able to provide the desired level of accuracy when dealing with millimeter-wave frequencies. With the increasing operation frequency of transistors reaching the sub-millimeter-wave range, the complexities of parasitic electromagnetic coupling effects also intensify. Therefore, the accuracy of the three-step de-embedding method, which involves the use of three de-embedding dummies, may be insufficient.

As transistors continue to shrink in size from micrometer to nanometer scale and operating frequencies reach the Terahertz range, the impact of open/short port effects and substrate coupling between input and output pads becomes more pronounced. These effects are not adequately addressed in the previously mentioned method. To enhance the accuracy of de-embedding, additional measurements involving a dummy structure are incorporated into the conventional open-short method.

Extensive research has been conducted to enhance the de-embedding accuracy specifically in the submillimeter-wave range. As a result, multistep de-embedding methods have been explored and developed. These methods aim to provide improved accuracy by incorporating additional steps and techniques to account for the complexities introduced by higher frequencies. Among the various multistep de-embedding methods, four-step de-embedding approaches have gained popularity in addressing the accuracy challenges in the submillimeter-wave range. Examples of these methods include open-short-open-short [20,21], open-open-thru-short [22], through-reflect-line-short [23]. These techniques involve additional steps and measurements to improve the accuracy of de-embedding at higher frequencies. Exploring additional de-embedding standards allows for the consideration of more parasitic parameters. However, as the number of measurement standards increases, the error resulting from measurement uncertainty also tends to rise. This presents a significant challenge in achieving accurate measurements. The trade-off between incorporating more standards to account for additional parasitic parameters and managing the accompanying increase in measurement uncertainty poses a difficult task. In general, the de-embedding methods discussed so far are based on measurements. This means that the de-embedding process is directly implemented using the measured data from the de-embedding structure’s matrix substrate. Nevertheless, these methods exhibit a tradeoff between the complexity of the de-embedding structures and the accuracy of de-embedding, particularly in the high-frequency range. As the complexity of the de-embedding structure increases, it may lead to improved accuracy. However, striking the right balance between complexity and accuracy becomes crucial to ensure practical and reliable de-embedding results at high frequencies.

However, all the parasitic components are not extracted efficiently using those methods. The most convenient method for extracting parasitic components is known as the cold-FET de-embedding technique [1,3,8,24,25,26], where all the parasitic components can be extracted from the cold-FET in various biases. The cold-FET de-embedding technique is a convenient and effective method for extracting parasitic components in semiconductor devices. This technique utilizes a “cold” or non-conducting FET (Field-Effect Transistor) as a reference device to characterize and eliminate the effects of parasitic elements present in the measurement setup [8]. The extracted parasitic components obtained from the cold-FET de-embedding technique provide crucial insights into the device’s performance and aid in developing accurate equivalent circuit models. These models can then be utilized for further analysis, optimization, and design of high-frequency devices and circuits. In contrast, the resistance extraction method also has some drawbacks in the research field, because bias dependency of the resistances is overlooked. Although resistances are frequency independent, they are eventually bias dependent. The well-known equation for resistance extraction contains three basic equations constructed through Z-parameters with four unknown variables [8,27]. Hence, another equation or relationship is required to determine the values of the unknown parameters. Although there are various straightforward research methods for building an additional relationship, none of them are clearly evaluated. To overcome these difficulties, we propose a new method of resistance extraction focusing on an additional equation, which can be applied to determine the unknown variables more conveniently. The aim of this paper is to illustrate this unique method and capacitance correction. In Section 2, materials information and a detailed analysis of the resistance extraction technique are presented. The overall experimental results and discussion are presented in Section 3, and the conclusions are presented in Section 4.

2. Materials and Measurement of the Equivalent Circuit

2.1. Fabrication

The epitaxial layer structures were grown using low-pressure metal-organic chemical vapor deposition (MOCVD) technique on 3-inch SiC wafers. This epitaxial structure consisted of an Al_0.45Ga_0.55N barrier (8 nm), a Ga-polarity GaN channel layer (420 nm), and a GaN buffer layer (270 nm) on top of the SiC substrate (Figure 1a). The device fabrication involved mesa isolation etching, source/drain ohmic contact formation and gate patterning. The mesa isolation etching was performed using a reactive ion etching (RIE) system. Subsequently, the ohmic contacts were formed by standard Ti/Al/Ni/Au (25/160/40/100 nm) metallization on the source and drain regions, followed by rapid thermal annealing (RTA) at 830 °C for 30 s in an N₂ ambient to allow the formation of contacts on the AlGaN/GaN epi-structure. Metallization was performed via the lift-off technique. The Schottky gate contacts were then patterned by photolithography. The Ni/Au (20/300 nm) and Pt/Ti/Pt/Au (8/20/20/300 nm) Schottky gate contacts were fabricated by e-beam evaporation, and Al₂O₃ (3 nm) was deposited as the surface passivation layer. The real device picture showed in (Figure 2b) which is used for the experiment. The basic construction of the device includes two source pad, gate and drain pad with two fingers. Measurements of the current leakage characteristics (I–V) and gate leakage characteristics (I_g–V_g) were evaluated using a Keithley 4200SC semiconductor parameter analyzer and RF measurements were performed by an 8510C Network analyzer.

2.2. Problem Statement

We studied the equivalent circuit topology that was used for the determination of intrinsic elements gm, gd, Cgs, Cgd, Cds, Ri, Rds, and τ which shown in Figure 1c. Additionally, the extrinsic elements were c_pg, c_pd, c_pgd, R_g, R_s, R_d, L_g.pad, L_d.pad, L_s, L_{g_ex_line}, and L_{d_ex_line}. We included line inductance in our reference circuit to obtain better accuracy. We mainly focused on the extraction of parasitic components, which is why the intrinsic elements extraction process is not covered in this paper. At high frequencies, the effect of parasitic capacitances is negligible, while the effects of resistances and inductances are introduced and considered. Under a cold bias condition (V_ds = 0 V), the basic equation for resistance extraction can be written as follows:

$$R_s+R_g+\frac{R_{ch}}{3}=\mathrm{Re}(Z_{11})$$

(1)

$$R_s+\frac{R_{ch}}{2}=\mathrm{Re}(Z_{12})$$

(2)

$$R_d+R_g+R_{ch}=\mathrm{Re}(Z_{22})$$

(3)

These three equations are constructed with four unknown variables. Most of the existing research methodologies use approximations to determine the fourth unknown variable or the high-frequency channel resistance value is ignored. Lu et al. [28] obtained the value of R_s + R_d under a cold-pinched off (V_gs < V_th, V_ds = 0 V) condition. However, there was no maximum or minimum limit included for the V_gs pinch-off condition and the process of extraction was not stated clearly. Dambrine et al. [8] postulated four conditions about the extraction of another unknown variable, which included the conventional method [29]. In their method, the series resistance (R_s) calculation in the DC method always provided higher values. This would be questionable and possibly problematic when calculating the channel resistance from Equation (2). There was also a difference between the DC method and the RF method for resistance extraction. Therefore, the fluctuation of the resistance values is inevitable, resulting in incorrect results. In order to overcome these difficulties and the unstable behavior of resistances, we propose a new method for building the relationship between drain and source resistances that can be expressed with one additional equation.

2.3. New Method of Resistance Extraction

At the cold-FET condition (V_ds = 0 V), the drain current (I_d) does not theoretically flow. However, a small fraction of I_d can flow practically, which is visible from the measured RF data. In this case, the drain current does not discernably change the potential distribution inside the channel and the superposition principle is applied to obtain the drain to source voltage [30], as follows:

$$V_{ds}=(R_s+R_d+R_{ch})I_d+\left(R_s+\frac{R_{ch}}{2}\right)I_g$$

(4)

$$\frac{-I_g}{I_d}=\frac{(R_s+R_d+R_{ch})}{R_s+\frac{R_{ch}}{2}}$$

(5)

We selected AlGaN/GaN HEMT for measurement, adopting a fixed gate width, W_g = 25 and 50 μm, L_sd = 2 μm, and L_g = 30, 70, and 100 nm. The measurement frequency ranges were from 450 MHz to 50 GHz, with a step of 200 MHz. The bias points started from V_g = −7.0 V, and then increased to +2.0 V in 1 V steps. The dependency between I_g and I_d for three gate-length devices, displayed in Figure 2, reveals a linear relationship. Here, the gate current (I_g) is considered an independent variable (x axis), and the drain current (I_d) is maintained as a dependent variable (y axis). The slope of the linear fitting provides the value of I_g/I_d, which was approximately 0.5 in all the gate-length devices. Substituting the value of the I_g/I_d into Equation (5), we can obtain another equation, as follows:

$$R_d\approx 2R_s$$

(6)

The drain resistance (R_d) is almost double the source resistance (R_s).

3. Results and Discussion

3.1. Resistance Extraction from Cold-FET

The bias dependencies of the resistances (R_s, R_d, R_g) are clearly visible in Figure 3a–c, respectively. From Figure 3c, it is evident that for V_gs = 0.0 V at high frequencies (>40 GHz), the gate resistance value was approximately 11 Ω. After increasing the bias (V_gs > 0.0 V), the value of the gate resistance (R_g) at high frequencies was not constant. Depending on the bias condition, R_g was found to be 20 and 25 Ω for higher gate voltages (V_g) of 1.0 and 2.0 V, respectively. This variation in resistance at different gate biases was quite narrow for series resistance (R_s) and drain resistance (R_d). At high frequencies, the values of R_s and R_d were acceptable (on average). We also investigated the parasitic resistance calculation in the L_g = 100 nm device according to our new proposed method. The calculated results are displayed in

Table 1. Parasitic resistance calculations of L_g = 100 nm in bias condition (V_g = −4.0 V) pinch-off region.

Frequency	Rs (Ω)	Rd (Ω)	Rg (Ω)	Rch (Ω)
20 GHz	3.95	7.9	18.12	3.52
25 GHz	1.89	3.78	16.89	7.3
30 GHz	2.63	5.26	16.47	4.52
35 GHz	3.18	6.35	15.25	1.66
40 GHz	1.44	2.88	14.27	5.14
Average	2.62	5.23	16.20	4.42

,

Table 2. Parasitic resistance calculation of L_g = 100 nm in bias condition (V_g = 0.0 V and 1.0 V).

Frequency	Rs (Ω)	Rd (Ω)	Rg (Ω)	Rch (Ω)
20 GHz	1.29	2.58	14.47	13.90
25 GHz	0.87	1.74	14.04	14.74
30 GHz	0.98	1.96	13.49	14.08
35 GHz	1.06	2.12	13.17	13.60
40 GHz	0.80	1.60	12.77	13.98
Average	1.00	2.00	13.58	14.06

and

Table 3. Parasitic resistance calculation of L_g = 100 nm in bias condition (V_g = 2.0 V).

Frequency	Rs (Ω)	Rd (Ω)	Rg (Ω)	Rch (Ω)
20 GHz	1.26	2.52	29.54	13.16
25 GHz	1.02	2.04	24.32	13.48
30 GHz	1.12	2.24	20.51	12.88
35 GHz	1.22	2.44	18.25	12.32
40 GHz	1.06	2.12	16.79	12.42
Average	1.14	2.27	21.88	12.85

R_g displays very high value at V_g = 2.0 V.

for the different bias conditions, where almost the same results were measured at V_g = 0.0 V and V_g = 1.0 V, with little variation. This bias region could be considered a stable position for all the calculated resistances.

For the higher forward gate bias, the electron velocity in the short-gate structures started to saturate, increasing the gate resistance [31].

3.2. Parasitic Capacitance Extraction by Dambrine’s Model

The parasitic capacitances c_pd and c_pg, shown in the small-signal equivalent circuit (Figure 1), can be extracted by the cold-FET de-embedding method below the pinch-off condition. At the pinch-off condition (V_gs < −V_th), the FET equivalent circuit can be expressed by Figure 4. According to Dambrine’s FET model in the pinch-off region, the parasitic capacitance equations can be written as follows:

$$\mathrm{Im}ag(Y_{11})=j\omega \left(C_{pg}+2C_b\right)$$

(7)

$$\mathrm{Im}ag(Y_{12})=\mathrm{Im}ag(Y_{21})=j\omega C_b$$

(8)

$$\mathrm{Im}ag(Y_{22})=j\omega \left(C_{pd}+C_b\right)$$

(9)

where C_b is the depletion layer capacitance in the source and drain sides.

From Dambrine’s cold-FET circuit equation, if the imaginary admittance Imag(Y₁₁) = Imag(Y₂₂), we obtain the following expression:

$$C_{pg}+2C_b=C_{pd}+C_b$$

(10)

$$C_{pd}=C_{pg}+C_b$$

(11)

which results in pad capacitances not being equal from the circuit perspective. We determined that the pad capacitances were as follows: C_pd = 16.7 fF, C_pg = 0.88 fF, and C_b = 15 fF. These values exhibited a huge discrepancy in the symmetrical structure for HEMTs. Moreover, this model overestimated the c_pd pad capacitance. The reason for this result was that there was no given limit of parasitic capacitance extraction at the pinch-off region. We modified the circuit in a way that considered the depletion layer capacitance added in the gate region, as displayed in Figure 5.

Adding the depletion layer capacitances in the pinch-off circuit condition, we can rewrite the modified equations as follows:

$$\mathrm{Im}ag(Y_{11})=j\omega \left(C_{pg}+C_b\right)$$

(12)

$$\mathrm{Im}ag(Y_{12})=\mathrm{Im}ag(Y_{21})=j\omega C_b$$

(13)

$$\mathrm{Im}ag(Y_{22})=j\omega \left(C_{pd}+C_b\right)$$

(14)

Furthermore, imposing the same condition of Imag(Y₁₁) = Imag(Y₂₂), we revealed that C_pd = C_pg.

Figure 6a displays the Y-parameter dependency according to frequency. The parasitic capacitance extraction from MATLAB depicted in Figure 6b indicates that the values for C_pd in Dambrine’s model were overestimated. Applying our corrected method, we estimated the pad capacitances as C_pd = 1.19 fF, C_pg = 0.58 fF, and C_b = 15.2 fF, as shown in Figure 6c. All the capacitance values are provided in

Table 4. Comparison of pad capacitance.

Parameters	Dambrine’s Model	Proposed Model
Cpg (fF)	0.88	0.58
Cpd (fF)	16.7	1.19

for easier comparison.

The important thing to be considered for measuring capacitance is step size. If the step size is high enough (>1 GHz), then there will be difficulty calculating pad capacitance. Figure 7a shows that the large step size around 1 GHz creates difficulties in the calculation of pad capacitances. Those values fluctuate high enough when the frequency range increases. After reducing the step size in the measurement process to about 200 MHz, the values in the low-frequency range (<5 GHz) shown in Figure 7b become suitable.

We simulated the small-signal equivalent circuit model in the ADS 2020 software to provide a comparison between our method and Dambrine’s circuit model. The difference prior to the addition of the depletion layer capacitance is displayed in Figure 8a. The measurement (red line) and modeled (blue close circle) results were perfectly matched after adding capacitance and resistance, as depicted in Figure 8b.

3.3. Model and Measurement Data Validation

We used measured data from ICCAP and modeled the results in ADS software to compare the result with our proposed method. For calculations of the inductance, the Z-parameters can be written as [32]

$$Z_{11}=R_g+R_s+j\omega (L_g+L_s)+\frac{1}{j\omega }\left(\frac{1}{C_g}+\frac{1}{C_s}\right)$$

(15)

$$Z_{22}=R_d+R_s+j\omega (L_d+L_s)+\frac{1}{j\omega }\left(\frac{1}{C_d}+\frac{1}{C_s}\right)$$

(16)

$$Z_{22}=R_s+j\omega L_s+\frac{1}{j\omega C_s}$$

(17)

Multiplying the Z-parameters with $\omega$ and considering the imaginary terms results

$$\mathrm{Im}[\omega Z_{11}]={\omega }^2(L_g+L_s)-\left(\frac{1}{C_g}+\frac{1}{C_s}\right)$$

(18)

$$\mathrm{Im}[Z_{22}]={\omega }^2(L_d+L_s)-\left(\frac{1}{C_d}+\frac{1}{C_s}\right)$$

(19)

$$\mathrm{Im}[Z_{22}]={\omega }^2{L}_s-\frac{1}{C_s}$$

(20)

Therefore, L_g, L_d, L_s can be extracted from the slope of Equations (18)–(20), respectively. The inductance values were extracted from forward gate bias condition V_g = 1.0 V using the least-square-regression method shown in Figure 9.

Figure 10 displays a comparison of the modeled and measurement results for two different gate widths (W_g = 2 $\times 25\mathsf{\mu }\mathrm{m}$ and W_g = 2 $\times 50\mathsf{\mu }\mathrm{m}$) and devices with the same gate length L_g = 100 nm. All the values extracted (intrinsic and extrinsic part) from the small-signal model are listed in

Table 5. Parameters extraction of 2 $\times 25\mathsf{\mu }\mathrm{m}$ and 2 $\times 50\mathsf{\mu }\mathrm{m}$.

Extrinsic/Intrinsic	Model Parameters	Extracted Values $\mathbf{For}2\times 25\mathsf{\mu }\mathbf{m}$	Extracted Values $\mathbf{For}2\times 50\mathsf{\mu }\mathbf{m}$
Extrinsic part	Rg	15 Ω	9.5 Ω
	Rd	26 Ω	8.0 Ω
	Rs	13 Ω	4.2 Ω
	Lg	0.1 pH	4.1 pH
	Ls	20.3 pH	26.3 pH
	Ld	24.5 pH	23.4 pH
Intrinsic part	Cgs	32 fF	45 fF
	Cgd	3.6 fF	12 fF
	Ri	1.38 Ω	1.45 Ω
	Gm	20 mS	26 mS
	τ	0.699 pico sec	1.23 pico sec
	Rds	1500 Ω	1800 Ω
	Cds	1.22 fF	19 fF

. Figure 10a displays the results of 2 $\times 25\mathsf{\mu }\mathrm{m}$ devices. This indicated that, due to incorrect values of drain resistance (R_d), source resistance (R_s), and gate resistance (R_g), the measured data did not correlate with the modeled data. After correcting the capacitance and resistance values, the modeled data accurately matched the measured values. Another device (2 $\times 50\mathsf{\mu }\mathrm{m}$) displayed the same results (Figure 10c,d). Figure 10c presents the data where the resistance values are only taken in the high-frequency range, which creates the problem of matching the S₂₂ parameter due to over-estimating the values of the series (R_s) and drain (R_d) resistances. In the high-frequency range, the values obtained were R_s = 7.2 Ω (average) and R_d = 16.5 Ω. Considering that the channel resistance (R_ch) was completely eliminated, this completely overestimated the results found in 2 $\times 50\mathsf{\mu }\mathrm{m}$ device. In our method, we found that channel resistance still dominated in the high-frequency range. We investigated more than 10 bias points in different gate-length devices (30, 50, 70, 100, and 150 nm), and these results were consistent with our hypothesis.

4. Conclusions

In this paper, we proposed a new method of resistance extraction using a cold-FET circuit and developed a direct extraction method for high-frequency applications of AlGaN/GaN HEMTs. Previous studies have suggested that resistance is an extrinsic element that is not bias-dependent. However, our measurement and data analysis results indicated that the gate resistance (R_g) primarily depends on bias compared to the drain (R_d) and source resistances (R_s). Parasitic capacitance extraction from Dambrine’s model overestimates the C_pd values because it does not remove the depletion layer capacitance in the gate-side region. After adding depletion layer capacitance, the small-signal equivalent circuit exhibited more accurate modeling results with the measurement data.