A Fast Weight Control Strategy for Programmable Linear RAM Based on the Self-Calibrating Erase Operation

Abstract

Computing-in-memory (CIM) has attracted great attention due to the need for breaking through the “memory wall”. Programmable linear random-access memory (PLRAM) for high-precision weight control is proposed to tear down the wall. However, the slow programming algorithm to tune cells limits its application in multi-level memory. Herein, a fast weight control strategy for PLRAM based on the self-calibrating erase operation is presented. The unique sidewall tunneling oxide utilized in PLRAM for bi-directional Fowler–Nordheim tunneling results in the corner-enhanced poly-to-poly tunneling effect and the self-calibrating capability during the erase process. By adopting this strategy, the efficiency of weight tuning in the PLRAM array is improved by 51% compared with the current method. The worst case is 4.9 ms for erasure, which only needs to be verified 10 times. The improvement of weight tuning efficiency means further development in CIM for PLRAM and also shows the significant prospect of PLRAM used in multi-level memory.

1. Introduction

The development of artificial intelligence (AI) leads to a substantial increase in the amount of data to be processed. Memory systems are also required with large capacities and high bandwidth [1]. The phenomenon that memory performance limits data processing is called the “memory wall” [2]. In order to tear down the memory wall, considerable efforts have been devoted to improving memory systems and processors, respectively, based on the von Neumann architecture. Highly parallel graphics processing units contain numerous cores which individually own a dedicated or shared high-throughput connection with the memory to achieve enhanced parallelism [3]. Accelerators such as the tensor processing unit are another way to save both memory bandwidth and processing power [4,5]. From the perspective of memory systems, hybrid memory and high-bandwidth memory are proposed to provide high bandwidth and memory density by using monolithic 3D integration [6,7]. However, the conventional von Neumann architecture is unable to completely break through the memory wall. In this case, non-von Neumann architecture has received widespread interest. Computing-in-memory (CIM) realizes the architecture by performing calculations in the memory array corresponding to the information processed in the human brain by networks of neurons and synapses which can avoid unaffordable latency and energy consumption [8,9]. Emerging non-volatile memory (NVM) devices are suitable for building artificial synapses to achieve CIM because of their low power consumption, compact structure, and compatibility with back-end-of-line processes [10,11,12,13,14,15]. With respect to the aforementioned issues, a new type of flash memory-based memristor, i.e., programmable linear random-access memory (PLRAM), was recently presented [16]. The computing-in-memory (CIM) SoC chip is integrated for multi-keyword spotting which can achieve $>10$ TOPS/W energy efficiency and 94.8%+ accuracy in real-time processing [17].

It is noteworthy that all types of NVM can store more than 1 bit in each memory cell, which can multiply the density of storage. Competitive multi-level cells require the characteristics of precise control over the electrons, fast storage capability, and long-term stability of the stored charge [18]. In other words, PLRAM has the potential to implement multi-bit cells.

Although PLRAM can achieve advanced storage capability, superior data retention, and high energy efficiency [19], the fixed-voltage “program-verification” tuning scheme used in PLRAM at present is inefficient, which contains amounts of verification steps and costs 10 ms for programming in the worst case. The ineffective scheme indicates the low efficiency of product testing which obviously restricts its subsequent advancement in CIM and blocks its application in multi-level memory.

In this work, the fabricated PLRAM cell exhibits a fast and self-calibrating characteristic during erasure. Subsequently, we put forward a more efficient weight control strategy for PLRAM, and 4.9 ms for erasure with only 10 verification steps in the worst case is realized under the quadra-level-cell (QLC, 4-bit/cell) mode test.

2. Physical Characterization Analysis

Figure 1 shows the schematic of the PLRAM cell. It is implemented on a 90 nm CMOS technology platform [16]. PLRAM uses separated sidewall tunneling oxide (TOX); the electron tunnels between the select erase gate (SEG) and the floating gate (FG) via Fowler–Nordheim (F-N) tunneling. By decoupling the gate oxide and TOX, the degradation probability of the oxide during programming and erasing is reduced, and PLRAM also enables the precise control of electrons. Therefore, PLRAM exhibits enhanced transistor reliability and provides considerable synaptic weights. There are two tunneling directions: direction A is the side wall direction and direction B is the corner direction. The tunneling efficiency is identical between programming and erasing in direction A at a given bias since the distribution of the electric field is uniform, see Figure 2a. On the other hand, direction B gains dense electric field distribution due to the effect of point discharge, and the energy band diagram of the tip closed to the floating gate (FG) is steeper when erasing, as shown in Figure 2b. The electron can easily tunnel from FG to SEG. In contrast, the energy band at the corner closed to SEG makes it hard to form a triangular potential barrier during programming, as shown in Figure 2c. The erase efficiency in PLRAM cells will be significantly larger than the programming efficiency under the same condition because of the corner-enhanced poly-to-poly tunneling effect [20].

Figure 3 demonstrates the single-direction program/erase scan in 1805 PLRAM cells. The programming voltage is much larger than the erasing voltage, as summarized in the inset; however, the erase efficiency is still twice as fast as that of the programming. It implies that applying erase operation to weight tuning can realize higher speed.

As depicted in Figure 4a, the electric field in the TOX ($E_{FN}$) is composed of the intrinsic electric field of the electron charge ($E_i$) in the floating gate and the external electric field ($E_{ex}$). The initial $E_{FN}$ is large enough to form a steep triangular barrier in the TOX, giving rise to considerable tunneling current density according to the F-N tunneling formula [21].

$$J_{FN}=\frac{q^3{E}^2}{8\pi h\mathsf{\Phi }}{e}^{-\frac{4{\left(2m\right)}^{1/2}{\mathsf{\Phi }}^{3/2}}{3\hslash qE}}$$

(1)

where ℏ represents the reduced Planck constant, $q$is the charge quantity, $E$ is the electric field strength, $\mathsf{\Phi }$ is the barrier height, and m is the mass of the free electron. A large number of electrons tunnel from FG to SEG, and the threshold voltage decreases rapidly, corresponding to the fast part. The reduction in the number of electrons in the FG leads to the lower $E_i$, further resulting in the diminished $E_{FN}.$ The triangular barrier tends to be flat and $J_{FN}$ becomes insignificant, during which time, the slow stage is formed, shown in Figure 4b. Thus, F-N tunneling changes into direct tunneling when $E_i$ is down to the critical threshold. It is hard for electrons to tunnel from FG into SEG, consistent with the cut-off stage, shown in Figure 4c.

Figure 5 presents the drain current ($I_d$) as a function of erase cycles for different erasing voltages ($∆V_E$) in the PLRAM array. The $I_d$ shows an initial sharp rise, and then a gentle change, and each finally stays almost constant. It illustrates the one-to-one mapping between the erase voltage of PLRAM cells and the tuning results by adopting appropriate erase pulses. Therefore, PLRAM can achieve a self-calibrating erase operation with fewer verification steps.

3. Algorithm and Verification

Figure 6a exhibits a fast weight control strategy based on the self-calibrating erase operation in PLRAM. The scheme mainly contains three steps. The first step is the pre-erase operation, and the erase voltage $V_{LUT}$ is loaded according to the look-up table (LUT). All the cells are divided into the fast cells, the normal cells, and the slow cells, respectively, according to the threshold voltage distribution after the pre-erase, shown in Figure 6b. The second step is the erase cycle with fixed bias ($V_{fix}$) to guarantee fast cells are non-over-erased. The third step is the erase cycle with the increment step pulse program (ISPP) [22] but the cells are only verified at specific cycle times (${PC}_{LUT}$) to make slow cells reach the target window quickly and lower the verification times, shown in Figure 6c.

In order to verify the strategy, a QLC mode test is performed on the PLRAM array. The PLRAM cells are divided into 16 weight windows, and the array cells are adjusted to the target weight, in turn, to verify the efficiency and accuracy of the strategy, as schematically shown in Figure 7. QLC mode has higher storage density at the cost of a smaller memory window compared with the triple-level-cell (TLC, 3-bit/cell).

Figure 8a depicts the weight change process of the worst case in the test, and each curve represents a verification step. The weight distribution reaches the target window after 800 pulses, during which, only 4.9 ms for erase and 10 verification steps are taken. The efficiency of weight tuning in the PLRAM array utilized in our strategy is improved by 51%, and the number of verification steps is significantly reduced, shown in Figure 8b.

Table 1. The comparison between this work and some reported algorithms applied in the QLC. IPNPP represents the incremental positive–negative step pulse programming.

References	This Work	16-16 Two-Step Programming [23]	Three-Step Programming [24]	8-16 Two-Step Programming [25]	IPNPP [26]
Circuit	NOR	NAND	NAND	NAND	NOR
Process	90 nm	70 nm	43 nm	BiCS	55 nm
Verification steps	10	555	About 600	About 455	15

illustrates the comparison between this work and some reported algorithms utilized in the QLC, and our strategy achieves the minimum verification steps. It is confirmed that the time cost of the verification will be sufficiently decreased by adopting the self-calibrating erase operation in the weight tunning. The cumulative distribution function of 4-bit weights is presented in Figure 9. Steep and distinct distribution functions are obtained in each target weight window, indicative of the efficient and accurate weight control.

4. Conclusions

In summary, we have demonstrated a fast weight control strategy for PLRAM based on the self-calibrating erase operation through enhanced F-N tunneling. It achieves a 4.9 ms erase process and only 10 verification steps in the worst case. The efficiency is improved by 51% compared with the current strategy. It is attributed to the corner-enhanced poly-to-poly tunneling effect that occurs in the erase process of PLRAM. These findings provide a solution to low efficiency during the tuning process of the PLRAM array and show that our PLRAM has great potential in the application of multi-level memory.