Small-Signal Model of the NPC + GCC Multilevel Transformerless Inverter in Single-Phase Photovoltaic Power Systems

Abstract

Photovoltaic transformerless inverters are very efficient and economical options for solar-power generation. The absence of the isolation transformer improves the converters’ efficiency, but high-frequency voltage to ground can appear in the photovoltaic string poles. The high capacitance to ground of the photovoltaic generator leads to undesirable high-leakage currents. Using half-bridge topologies dramatically reduces the leakage to ground, and using a multilevel half-bridge inverters improves the output quality compared with classical inverters. The neutral point clamped + generation control circuit (NPC + GCC) topology is a multilevel single-phase transformerless inverter capable of tracking the maximum power point of two photovoltaic sources at the same time. This paper presents the control structure and the dynamic modeling of the NPC + GCC inverter. The pulse-width modulated (PWM) switch model in continuous conduction mode (CCM) was used to obtain the small-signal model of the two switching converters that make up the inverter. The resulting dynamic model was used to quantify the stability margins of both converters’ current and voltage loops.

1. Introduction

Grid-connected photovoltaic (PV) inverters may be divided into two categories: PV inverters with isolation transformer and transformerless PV inverters [1,2,3]. In power converters for renewable energy sources (RES), especially in grid-connected PV inverters, efficiency and cost are vital factors [4,5]. Transformerless inverters present high efficiency and cost less than those with a transformer [6,7]. Hence, many PV transformerless inverter topologies have been presented in the literature [1,8,9,10,11].

The main issue PV transformerless inverters must address is the common-mode voltage. The commutation of inverter switches can produce an alternating common-mode voltage between the PV-panel poles and the ground [12,13,14]. In PV power plants, the parasitic capacitance to ground can reach high values due to the large surface of the PV generator. Typical values vary between 50 and 150 nF/kW for crystalline-silicon cells and reach up to 1 µF/kW for thin-film cells [1]. The alternating component of the common-mode voltage generates a leakage current through these high capacitance values to ground, which may produce serious problems (e.g., the activation of electrical protections, efficiency degradation, and safety problems) [6,15,16]. Figure 1 depicts the parasitic capacitances and the leakage current.

A simple way of reducing the leakage current to ground is the use of half-bridge inverter topologies, in which the midpoint is connected to the neutral point [17]. However, the half-bridge topologies usually present a high level of total harmonic distortion (THD) in their output. In [18], the NPC + GCC transformerless topology for a single-phase grid-connected PV inverter was presented (Figure 2). In this topology, the midpoint of the dc-link of a multilevel half-bridge neutral point clamped (NPC) inverter is used to reduce the leakage current to ground. Using a multilevel topology improves the THD of the output compared with a conventional half-bridge [19,20,21,22]. The more output voltage levels a topology possesses, the lower the level of THD it presents. A variety of topologies, like the cascaded H-bridge (CHB), the flying capacitor (FC), the diode-clamped inverter, the neutral-point clamped (NPC), the Conergy NPC, or the active NPC inverter, were presented in the literature [1]. Due to its cost and simplicity, the NPC is the most widely used topology in low-power systems. Moreover, the use of the midpoint of the input voltage leads to additional benefits in the leakage-current-to-ground reduction [1,21,22,23,24].

Furthermore the generation control circuit (GCC) converter uses the midpoint to provide the highly efficient double-maximum-power-point tracking of two series-connected PV sources, improving the power generation under partial shadowing in PV modules. In fact, the voltage control provided by the GCC converter solves the midpoint voltage balancing, the main drawback of the NPC inverter [25,26]. Partial shadowing is problematic in PV power plants, since a small shadow can dramatically reduce the overall power of a large group of PV modules [27,28], and the GCC circuit improves the partial-shadowing performance of the converter.

The NPC + GCC transformerless topology is formed by two parallel converters: the NPC multilevel inverter (IGBT1 to IGBT4 and D1 to D2), which manages the current injected over the grid; and the GCC DC/DC converter (IGBT5 and IGBT6), which adjusts the midpoint voltage of the dc-link. This pair of converters tracks two different maximum power points (MPP) in the converter’s input (V_PV1 and V_PV2). Compared with a double-stage PV inverter (boost + inverter), the NPC + GCC has better efficiency [18] since the GCC only manages the power difference between the strings and not the full power.

NPC and GCC converters share the input dc-link series-connected capacitors and are connected to the total input voltage. The midpoint is connected to the NPC’s free-wheeling diodes and the GCC’s inductance output port. This paper proposes a control structure and presents the procedure to obtain a small signal dynamic model to control both converters independently. The objective is to control the input voltage in each dc-link independently while the NPC injects a sinusoidal current into the mains grid. Hence, a dual maximum-power-point tracking (MPPT) algorithm will run over the two inputs.

This paper is based on a 5 kW NPC + GCC photovoltaic inverter fed by a pair of PV strings of 3 kW each. Section 2 describes the control structure of the whole system in depth. Section 2.1 and Section 2.2 detail the models of the NPC and the GCC converters. Then, Section 3 and Section 4 detail how the models obtained are used to adjust the current and voltage regulators.

2. Transformerless PV Inverter Control Structure

Figure 3 shows the control structure of the NPC + GCC topology. It consists of a double maximum-power-point tracking (MPPT) perturb and observe (P&O) algorithm and independent control loops for the NPC and the GCC, organized as follows.

The GCC control block consists of a PWM modulator generating the switching signals for IGBT5 and IGBT6, fed by a current compensator (G_I-GCC), adjusting the inductance current. The current reference (I_GCC-REF) is generated by an input voltage compensator (G_V-GCC), which adjusts the voltage of the PV string number 2 (V_PV2).

The NPC control block consists of an in-phase disposition (IPD) PWM modulator, but other modulation multilevel techniques can be considered [29], generating the switching signals for IGBT1 to IGBT4, fed by a current compensator (G_I-NPC), adjusting the current injection into the mains grid. The phase-locked loop (PLL) generates the sinusoidal shape of the current reference (I_NPC-REF) to ensure unity power factor injection. The I_NPC-REF magnitude is generated by the voltage compensator (G_V-NPC), which adjusts the total input voltage of the PV strings PV1 + PV2 (V_DC-REF). Hence, the voltage of PV1 (V_PV1) is indirectly controlled.

The current and control loops are digitally programmed in a Texas Instruments DSP TMS320F28335. All the signals are fed to the DSP controller through analog low-pass filters (LPF) and acquired through a 12-bit ADC running at 32 ksps. The two independent MPPT algorithms are based on the classical perturb and observe (P&O) technique and run by employing the PV input voltage and current values (V_PV1, I_PV1 and V_PV2, I_PV2).

Table 1. Main parameters of the NPC + GCC PV inverter.

Parameter	Value
Input voltage at MPP (VPV-MPP)	2 × 408.8 V
Input current at MPP (IMPP)	7.54 ADC
Maximum PV power (PPV-MAX)	2 × 3.08 kW
GCC switching frequency (fSW-GCC)	16 kHz
NPC switching frequency (fSW-NPC)	16 kHz
Input capacitance (C1 and C2)	2 × 3 mF
GCC inductance (LGCC)	15 mH
NPC inductance (LNPC)	2 mH
LC filter capacitance (COUT)	9.4 µF
Damping resistor (rd)	1 Ω
GCC IGBT switches	IRG4PH40KDPBF (1200 V/15 A)
NPC IGBT switches	APTGL60TL120T3G (1200 V/60 A)
RMS nominal grid voltage (VGRID-RMS)	230 VRMS
Nominal grid frequency (fGRID)	50 Hz
Anti-aliasing filters crossover frequency	16 kHz
ADC sampling frequency	32 kHz
Digital voltage regulators update frequency	32 kHz
Digital current regulators update frequency	32 kHz
MPPT update period	300 ms

summarizes the most critical parameters of the power converter under study. Regarding the voltage rating of the components, it must be noted that the MPP nominal input voltage of each input is 408.8 V. Hence, since the worst-case open circuit voltage in typical PV modules is usually 30% higher, the maximum input voltage is around 530 V. The switches of the GCC must withstand a voltage twice this value. Hence, 1200 V IGBTs are used. The switches in the NPC must withstand 530 V; therefore, a 950 V device is sufficient. However, the limited commercial offer in NPC half-bridge modules leads to the 1200 V device.

In this work, the NPC inverter regulates the total dc-link voltage (V_PV1 + V_PV2), whereas the GCC regulates the voltage V_PV2. Many MPPT methods have been presented in the literature, among which the perturb and observe (P&O) method is a simple but robust MPPT one, being the preferred option in low-to-medium power converters [30]. A double-MPPT P&O algorithm generates the voltage references V_PV1-REF and V_PV2-REF. Figure 4 shows the flowchart algorithm of the implemented double MPPT algorithm. This algorithm is based on the classic P&O with a fixed step size [30,31].

The GCC voltage regulator (G_V-GCC) adjusts the current reference in the inductor (I_GCC-REF) to set the voltage V_PV2 at the desired level. The voltage regulator of the NPC inverter (G_V-NPC) modifies the reference of the output current amplitude, I_OUT-REF, to regulate the total input voltage (V_DC = V_PV1 + V_PV2) at the desired level. Since the GCC regulates V_PV2, this algorithm indirectly regulates the voltage V_PV1.

2.1. Model and Control Structure of the Multilevel Half-Bridge NPC PWM Inverter

In this section, the model and the control structure of the multilevel NPC PWM inverter are described. Figure 3 introduces the NPC PWM inverter control structure. It comprises an MPPT P&O algorithm, an output current control loop, and an input voltage control loop.

The MPPT P&O algorithm (Figure 4) perturbs the voltage reference for V_PV1 (V_PV1-REF). If the power obtained from string PV1 (P_PV1) increases, the next step value of V_PV1-REF will be applied in the same direction. However, if the power decreases, the next step value of V_PV1-REF will be in the opposite direction.

The voltage references (V_PV1-REF, V_PV2-REF) generated by the MPPT algorithms are added to create V_DC-REF, the input voltage reference for the NPC inverter voltage control loop. The voltage regulator (G_V-NPC) adjusts the input voltage to match that reference value. Thus, the output of G_V-NPC is the peak value of the output inductor reference current (I_{OUT-REF_PK}).

The phase-locked loop (PLL) module ensures that the output current is aligned with the grid voltage phase based on an SRF-PLL [32]. It provides information about the phase angle of the grid. The magnitude I_{OUT-REF_PK} multiplied by the cosine of the phase angle provides the instantaneous reference value for the output inductor current (I_OUT-REF). The current regulator (G_I-NPC) adjusts the output current (I_OUT) to match the reference. Furthermore, the current regulator of the NPC inverter must provide a high-quality output waveform, even under distorted grid voltages [33].

The modulator employed In the multilevel NPC inverter uses in-phase disposition (IPD) carrier signals [34]. Figure 5 depicts the IPD modulator concept. The IPD modulator drives the switches IGBT1 to IGBT4 to provide the required inverter output voltage (V_AB). Note that the output voltage waveform has three levels (V_PV1, 0, and −V_PV2).

Different approaches have been published in the literature to obtain a switching converter’s linear model and adjust its control loops. The equivalent matrix structure and mixed logical dynamic (MLD) approaches are specially indicated for NPC inverters with a high number of output voltage levels [35]. Model predictive control (MPC) has fewer bandwidth limitations and a fast dynamic behavior but a variable switching frequency [36]. The modulated model predictive control (MMPC) combines the advantages of the MPC with a constant switching frequency [37]. Fuzzy logic and neural networks controllers can work from imprecise inputs and do not require a precise model [38], but their complexity can be high. Fractional order PID and modulated hysteresis provide very fast transient performance and are easy to implement [39]. The AC small-signal modeling applied to multilevel converters [40] is a powerful technique to obtain a linear model of a switching converter. In this technique, deciding the appropriate control loop structure and determining the variables to be perturbed are essential.

However, when a reduced number of output voltage levels are used, and a constant frequency is desired, the PWM switch model proposed by V.Vorperian for continuous conduction mode (CCM) [41] is a widely used approach. It is a simple and robust method to obtain a linear model of the switching converter, is easy to use and requires a reduced number of equations, thus limiting the mathematical complexity of the model. Additionally, it is unusual to require an ultra-fast dynamic response in PV applications; therefore, Vorperian’s model suits most PV applications well.

In this model of the NPC + GCC inverter, the averaged variables are composed of their operating point (OP) value, X, and their small-signal perturbation around the OP, $\widehat{x}$, as shown in Equation (1). Note that, in a PWM inverter, some of the OP values have a sinusoidal variation with time at a fundamental frequency much lower than the switching frequency.

$$x=X+\widehat{x}$$

(1)

Figure 6 depicts the output current path during a switching period to be studied to identify the active (Act), passive (Pas), and common (Com) terminals of Vorperian’s model. Thus, the active, common and passive terminals are identified, as shown in Figure 7. The inverter can be replaced during the positive half-cycle of the output voltage, V_AB, by the switching cell shown in Figure 7. The study of the negative cycle leads to a circuit equivalent to that presented in this section; thus, only the positive cycle is studied.

The impedance of the electrical grid, L_GRID, must be considered for the dynamic study of the inverter. The ratio between the short-circuit current (I_CC) and the nominal current of the grid (I_N) permits the grid impedance to be estimated. This impedance, assumed to be inductive, is then calculated in the range of 84 µH (strong electrical grid, I_CC = 20·I_N) to 337 µH (weak electrical grid, I_CC = 5·I_N).

Thus, by replacing the inverter with the PWM switch cell model and considering the grid impedance, the model shown in Figure 8 is obtained. The model comprises the operating point circuit (OP) and the small-signal circuit (AC). The previous figures’ points labeled A and B are kept for clarity. In this model, the diodes and switches are considered ideal devices with no voltage drop.

The values of the parameters of the OP circuit are expressed in (2)–(12), and the small-signal transfer functions are shown in (13)–(16), where ‘s’ is the variable of the Laplace transform. The OP circuit provides the value for the parameters ${\mathrm{V}}_{\mathrm{AP}}$, ${\mathrm{I}}_{\mathrm{C}}$, and D to be used in the small-signal equations.

The value of V_AP is constant (2) since it is the DC value of the input voltage.

$${\mathrm{V}}_{\mathrm{AP}}=V_{PV1}$$

(2)

The ${\mathrm{I}}_{\mathrm{C}}$ value is a 50 Hz sinusoidal alternating value. Thus, (3) calculates its precise phasor value. Since the capacitor current in the LCL filter is designed to consume a low current at 50 Hz, the ${\mathrm{I}}_{\mathrm{C}}$ current instantaneous value is almost equal to that injected into the grid and, therefore, is commonly approximated as (4), with a minimum error in most cases. Note that $\theta$ is the instantaneous phase value of the grid voltage.

$$\overrightarrow{{\mathrm{I}}_{\mathrm{C}}}=\frac{\overrightarrow{{\mathrm{V}}_{\mathrm{GRID}}}}{\overrightarrow{Z_C}}+\left(1+\frac{\overrightarrow{{\mathrm{Z}}_{\mathrm{GRID}}}}{\overrightarrow{Z_C}}\right)·\overrightarrow{I_{GRID}}$$

(3)

$${\mathrm{I}}_{\mathrm{C}}\left(\theta \right)\approx \sqrt{2}·I_{GRID-RMS}·\cos \left(\theta \right)$$

(4)

Solving Figure 8a circuit, the precise phasor value for the duty cycle (D) is calculated through (5). Assuming a pure inductive NPC inductor (Z_L-NPC = L_NPC) and grid impedance (Z_G = L_GRID), the real and imaginary parts of D are easily calculated as in (6) and (7). Thus, its magnitude is determined as (8) and its phase value as (9). Hence, the instantaneous value of D is calculated as (10). Note that $\theta$ represents the phase value of the grid voltage, and ${\theta }_D$ the phase delay between the duty cycle phasor and the grid voltage one. However, if the phase delay introduced by the LCL filter at 50 Hz is neglected, the instantaneous value of D can be estimated as in (11), with a minimum error in most cases. Note that $\theta$ is the instantaneous phase value of the grid voltage.

$$\overrightarrow{\mathrm{D}}=\frac{\overrightarrow{V_{GRID}}+\overrightarrow{I_C}·\left[\overrightarrow{Z_{L1}}+\overrightarrow{Z_{GRID}}·\left(1+\frac{\overrightarrow{Z_{L1}}}{\overrightarrow{Z_C}}\right)\right]}{V_{AP}·{\left(1+\frac{\overrightarrow{Z_{GRID}}}{\overrightarrow{Z_C}}\right)}^{}}$$

(5)

$$\Re e\left(\mathrm{D}\right)=\frac{\sqrt{2}·V_{GRID-RMS}}{{\mathrm{V}}_{\mathrm{AP}}·\left(1-{\omega }^2·L_{GRID}·C_{OUT}\right)}$$

(6)

$$\mathbb{I}m\left(D\right)=\frac{\sqrt{2}·I_{C-RMS}·\left[\omega ·\left(L_1+L_{GRID}\right)-{\omega }^3·L_1·L_{GRID}·C_{OUT}\right]}{{\mathrm{V}}_{\mathrm{AP}}·\left(1-{\omega }^2·L_{GRID}·C_{OUT}\right)}$$

(7)

$$\left|\overrightarrow{\mathrm{D}}\right|=\sqrt{{\left(\Re e\left(\mathrm{D}\right)\right)}^2+{\left(\mathbb{I}m\left(D\right)\right)}^2}$$

(8)

$${\theta }_D={\tan }^{-1}\left(\frac{I_{C-RMS}·\left[\omega ·\left(L_1+L_{GRID}\right)-{\omega }^3·L_1·L_{GRID}·C_{OUT}\right]}{V_{GRID-RMS}}\right)$$

(9)

$$D\left(\theta \right)=\sqrt{2}·\left|\overrightarrow{D}\right|·\cos \left(\theta +{\theta }_D\right)$$

(10)

$$D\left(\theta \right)\approx \frac{\sqrt{2}·V_{GRID-RMS}·\cos \left(\theta \right)}{V_{AP}}$$

(11)

Once the OP parameters are obtained, the small-signal model is obtained by solving the circuit of Figure 8b. First, the small-signal characteristic of the PV modules is determined. It is modeled as a dynamic resistor, according to (12).

$$r_{PV}=\frac{V_{MPP}}{I_{MPP}}$$

(12)

From Figure 8b, the duty cycle-to-inductor current transfer function is obtained (15). Additionally, the inductor current-to-input voltage transfer function is of interest (16). The parameters defined in (13) and (14) help to simplify the mathematical functions’ transcription.

$$A\left(s\right)=\frac{\raisebox{1ex}{$L_{GRID}$}\!\left/ \!\raisebox{-1ex}{$s$}\right.+r_d·L_{GRID}·C_{OUT}}{1+r_d·C_{OUT}·s+L_{GRID}·C_{OUT}·s^2}$$

(13)

$$B\left(s\right)=\frac{r_{PV}}{1+r_{PV}·C_{PV}·s}$$

(14)

$$\frac{{\widehat{i}}_C}{\widehat{d}}\left(s\right)=\frac{V_{AP}-B\left(s\right)·I_C·D}{A\left(s\right)·s^2+L_1·s+D^2·B\left(s\right)}$$

(15)

$$\frac{{\widehat{v}}_{PV}}{{\widehat{i}}_C}\left(s\right)=B·\frac{I_C·\left(A\left(s\right)·s^2+L_1·s+2·D^2·B\right)-D·V_{AP}}{V_{AP}-B·I_C·D}$$

(16)

Figure 9 and Figure 10 depict the Bode plots of the mathematical model presented in (2)–(17). Figure 9 shows the Bode diagram of the duty-cycle to inductor current (${\widehat{i}}_C/\widehat{d}$) transfer function, the power being 5 kW and the grid inductance L_GRID = 337 µH. Figure 10 depicts the Bode plots of the inductor current to PV-input voltage (${\widehat{v}}_{PV}/\widehat{i_C}$) transfer function. In both cases, the grid phase, θ, is a running parameter.

2.2. Model and Control Structure of the GCC DC/DC Converter

Figure 3 shows the GCC DC/DC converter [42] and its control loops (current loop, input voltage loop, and MPPT P&O algorithm). The MPPT P&O algorithm, shown in Figure 4, perturbs the voltage reference for V_PV2 (V_PV2-REF). Similarly, as in the case of V_PV1-REF, if the power obtained from string PV2 (P_PV2) increases, the next step in the value of V_PV2-REF will be applied in the same direction. If the power decreases, the sign of the next step will be changed.

The voltage regulator (G_V-GCC) adjusts the voltage V_PV2 to match its reference value (V_PV2-REF). Then, the output of G_V-GCC is the reference value of the inductor current (I_GCC-REF). The voltage of string 2 is adjusted by changing the value of I_GCC-REF. The current regulator, G_I-GCC, must be able to regulate both positive and negative values of I_GCC to provide bidirectional power flow between strings.

Figure 11 shows the modulator used in the GCC converter. The converter switches between the rails of the input voltage; therefore, the voltage at the inductor of the GCC (V_L-GCC) ranges between two voltage levels (V_PV1 and −V_PV2).

The GCC PWM DC/DC converter is modeled using the PWM switch model proposed by V. Vorperian for continuous conduction mode (CCM). To identify the Active (Act), Passive (Pas) and Common (Com) terminals of the Vorperian’s model, the path of the output current is studied (Figure 12) during a switching period (positive current in L_GCC is assumed). Thus, the Act-Com-Pas terminals are identified, as shown in Figure 13, and the DC/DC converter is replaced by the switching cell shown in Figure 13.

Thus, by replacing the GCC converter with the switching cell model, the GCC model shown in Figure 14 is obtained. The model is formed by the operating point circuit (DC) and the small-signal circuit (AC). The values for parameters of the operating point circuit are presented in (17)–(19), whereas (20)–(23) show the small-signal transfer functions.

$${\mathrm{V}}_{\mathrm{AP}}=V_{PV1}+V_{PV2}$$

(17)

$${\mathrm{I}}_{\mathrm{C}}=I_{PV1}-I_{PV2}$$

(18)

$$\mathrm{D}=\frac{V_{PV2}}{V_{PV1}+V_{PV2}}$$

(19)

$${\left.\frac{{\widehat{i}}_C}{\widehat{d}}\left(s\right)\right|}_{{\widehat{i}}_{npc}=0}=\frac{\frac{r_{PV}}{1+r_{PV}·C_{PV}·s}·I_C·\left(2·D-1\right)-V_{AP}}{\frac{r_{PV}}{1+r_{PV}·C_{PV}·s}·\left(1-2·D+2·D^2\right)-L_{GCC}·s}$$

(20)

$${\left.\frac{{\widehat{i}}_C}{{\widehat{i}}_{NPC}}\left(s\right)\right|}_{\widehat{d}=0}=\frac{D·\frac{r_{PV}}{1+r_{PV}·C_{PV}·s}}{\frac{r_{PV}}{1+r_{PV}·C_{PV}·s}·\left(-1+2·D-2·D^2\right)-L_{GCC}·s}$$

(21)

$$\mathrm{A}=\frac{r_{PV}}{1+r_{PV}·C_{PV}·s}$$

(22)

$${\left.\frac{{\widehat{v}}_{PV2}}{{\widehat{i}}_C}\left(s\right)\right|}_{{\widehat{i}}_{npc}=0}=\frac{A·\left[\left(V_{AP}-A·D·I_C\right)·\left(1-D\right)-I_C·\left(L_{GCC}·s+A·D^2\right)\right]}{V_{AP}+A·\left(1-D\right)}$$

(23)

Figure 15 shows the Bode plots for the duty-cycle to inductor current (${\widehat{i}}_C/\widehat{d}$) transfer function. Figure 16 depicts the Bode plots for the inductor current to input PV voltage (${\widehat{v}}_{PV}/{\widehat{i}}_c$) transfer function. In both cases, the dynamic resistance of the photovoltaic string, r_PV, is considered a running parameter. These Bode diagrams are obtained using the mathematical model presented in (17)–(23).

3. Control Design of NPC PWM Inverter

Figure 17 shows the closed-loop control structure designed using the small-signal model of the NPC inverter. In this figure, several transfer functions blocks appear, which are detailed as follows: G_V-NPC represents the input voltage compensator and G_I-NPC the output current compensator for the NPC inverter; del(s) represents the PWM delay; F_m the PWM modulator gain; $\widehat{i_L}/\widehat{d}$ stands for the duty cycle-to-output current transfer function and $\widehat{v_{PV}}/\widehat{i_L}$ for the output current-to-input voltage one; Ri represents the current sensor gain (unitary, due to the digital conversion gain); β represents the voltage sensor gain (unitary, due to the digital conversion gain); and Ant(s) represents the anti-aliasing ADC filters.

Table 2. Gains and transfer functions of the NPC inverter.

Name	Value/Expression
Digital delay of one sampling period (TS = 31.25 µs), del(s)	$e^{-s·T_S}\approx \frac{1-\frac{s·T_S}{2}+\frac{{\left(s·T_S\right)}^2}{12}}{1+\frac{s·T_S}{2}+\frac{{\left(s·T_S\right)}^2}{12}}$
Modulator gain, Fm	1
Current sensor gain, Ri	1
Voltage sensor gain, β	1
$\mathrm{Anti}-\mathrm{aliasing} \mathrm{filter}, \mathrm{Ant}\left(\mathrm{s}\right)$ $\left({\omega }_0=2·\pi ·8\mathrm{kHz}\right)$	$Ant\left(s\right)=\frac{1}{1+\frac{s}{Q·{\omega }_0}+\frac{s^2}{{\omega }_0^2}}$ $Q=\frac{1}{\sqrt{2}}$
Current regulator, GI-NPC(s)	$G_{I-NPC}\left(s\right)=0.05+\frac{10·s}{s^2+7·s+{\left(100·\pi \right)}^2}+\frac{25·s}{s^2+21·s+{\left(300·\pi \right)}^2}+\frac{30·s}{s^2+35·s+{\left(500·\pi \right)}^2}+\frac{35·s}{s^2+49·s+{\left(700·\pi \right)}^2}$
Closed loop response of the output current to its reference	$T_{i-lc}\left(s\right)=\frac{\widehat{i_L}\left(s\right)}{{\widehat{i}}_{L-REF}\left(s\right)}=\frac{1}{R_i}·\frac{T_i\left(s\right)}{1+T_i\left(s\right)}$
Voltage regulator, GV-NPC(s)	$G_{V-NPC}\left(s\right)=\frac{-4·\left(1+\raisebox{1ex}{$s$}\!\left/ \!\raisebox{-1ex}{$20$}\right.\right)}{s}$
Loop gain of the voltage loop, TV(s)	$T_V\left(s\right)=G_{V-NPC}\left(s\right)·T_{i-lc}\left(s\right)·\frac{{\widehat{v}}_{PV}\left(s\right)}{{\widehat{i}}_C\left(s\right)}·\beta$
Closed loop response of the output current to its reference	$\frac{\widehat{v_{PV}}\left(s\right)}{{\widehat{v}}_{PV-REF}\left(s\right)}=\frac{1}{\beta }·\frac{T_V\left(s\right)}{1+T_V\left(s\right)}$

defines several transfer functions of interest.

The current regulator, G_I-NPC, must provide a high gain at the grid frequency and its harmonics, along with enough attenuation at the switching frequency and proper stability margins. G_I-NPC is based on a P + Resonant structure, implemented in a Texas Instruments TMS320F28335 DSP processor. G_I-NPC has been adjusted to obtain an open loop gain of the current loop, whose Bode plots are shown in Figure 18. In the figure, T_i(s) presents a high gain at the grid frequency and its 3rd, 5th, and 7th harmonics, and a low gain at the switching frequency (16 kHz). The stability of the current loop is guaranteed by the stability margins: 0 dB crossover frequency f_Ci = 1.6 kHz, phase margin 50°, and gain margin 10 dB.

The voltage regulator, G_V-NPC, must provide a high gain at DC and a low gain at the grid frequency to minimize the distortion in the output current due to the low-frequency voltage ripple at the DC link, whose frequency agrees with the grid frequency in an NPC half-bridge inverter. The proposed structure for the voltage regulator is a proportional integrator (PI). G_V-NPC is adjusted to obtain the open loop gain (T_V) shown in Figure 19. The stability of the voltage loop is guaranteed by the stability margins: crossover frequency f_CV = 3.4 Hz to 9 Hz, phase margin > 65°, and gain margin > 35 dB. The gain at 50 Hz is −16 dB, thus attenuating the influence of the input voltage ripple in the output current.

4. Control Design of GCC DC/DC Converter

Figure 20 shows the closed-loop control structure using the small-signal model of the GCC converter, where several transfer functions of interest, defined in

Table 3. Gains and transfer functions of the GCC converter.

Name	Value/Expression
Digital delay of one sampling period (TS = 31.25 µs), del(s)	$e^{-s·T_S}\approx \frac{1-\frac{s·T_S}{2}+\frac{{\left(s·T_S\right)}^2}{12}}{1+\frac{s·T_S}{2}+\frac{{\left(s·T_S\right)}^2}{12}}$
Modulator gain, Fm	1
Current sensor gain, Ri	1
Voltage sensor gain, β	1
$\mathrm{Anti}-\mathrm{aliasing} \mathrm{filter}, \mathrm{Ant}\left(\mathrm{s}\right)$ $\left({\omega }_0=2·\pi ·8\mathrm{kHz}\right)$	$Ant\left(s\right)=\frac{1}{1+\frac{s}{Q·{\omega }_0}+\frac{s^2}{{\omega }_0^2}}$ $Q=\frac{1}{\sqrt{2}}$
Current regulator, GI-GCC(s)	$G_{I-GCC}\left(s\right)=\frac{15}{s}·\frac{1+\raisebox{1ex}{$s$}\!\left/ \!\raisebox{-1ex}{$200$}\right.}{1+\raisebox{1ex}{$s$}\!\left/ \!\raisebox{-1ex}{$30000$}\right.}$
Loop gain of the current loop, Ti(s)	$$\begin{gathered} T_i\left(s\right)= \\ {G}_{I-GCC}\left(s\right)·del\left(s\right)·Fm·\frac{{\widehat{i}}_L\left(s\right)}{\widehat{d}\left(s\right)}·Ri·Ant\left(s\right) \end{gathered}$$
Closed loop response of the output current to its reference	$\frac{\widehat{i_L}\left(s\right)}{{\widehat{i}}_{L-REF}\left(s\right)}=\frac{1}{R_i}·\frac{T_i\left(s\right)}{1+T_i\left(s\right)}$
Voltage regulator, GV-GCC(s)	$G_{V-GCC}\left(s\right)=\frac{1+\raisebox{1ex}{$s$}\!\left/ \!\raisebox{-1ex}{$5$}\right.}{s}$
Loop gain of the voltage loop, TV(s)	$T_V\left(s\right)=G_{V-NPC}\left(s\right)·T_{i-lc}\left(s\right)·\frac{{\widehat{v}}_{PV2}\left(s\right)}{{\widehat{i}}_C\left(s\right)}·\beta$
Closed loop response of the output current to its reference	$\frac{{\widehat{v}}_{PV2}\left(s\right)}{{\widehat{v}}_{PV2-REF}\left(s\right)}=\frac{1}{\beta }·\frac{T_V\left(s\right)}{1+T_V\left(s\right)}$

, can be identified.

In this case, the current regulator, G_{I_GCC}, must provide a high gain at DC, enough attenuation at the switching frequency, and proper stability margins. G_{I_GCC} is a PI regulator implemented in the digital controller and adjusted to obtain the open loop gain, T_i(s), shown in Figure 21. The main stability margins observed from this figure are as follows: crossover frequency 350–40 Hz, phase margin > 75°, and gain margin > 20 dB.

The voltage regulator, G_V-GCC, adjusts the voltage V_PV2 to match the reference value, V_PV2-REF. G_V-GCC must provide a high gain at DC to guarantee a null error in tracking the steady state reference current. G_V-GCC is adjusted to obtain the open loop gain (T_V) of Figure 22. The stability margins guarantee the stability of the voltage loop: crossover frequency 6 Hz, phase margin 85°, and gain margin 45 dB.

5. Conclusions

In this paper, the modeling of the NPC + GCC topology is presented. OP (operating point) and AC (small-signal) equivalent circuits for the NPC inverter and GCC DC/DC converter have been obtained. The NPC + GCC topology has a pair of converters working in parallel. As a result, both PV input voltages can be controlled independently. Additionally, its model and stability study are carried out independently as well.

By using the small-signal model presented, both converters’ current and voltage controllers have been designed in the frequency domain. Moreover, the stability margins are obtained and evaluated to ensure the designed control’s robustness.

The low-frequency ripple in the input capacitors, inherent in the half-bridge topologies, is addressed here in the control loops. The designed voltage compensators have a very low gain at the grid frequency. Hence, they do not respond to that ripple.