An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder
Round 1
Reviewer 1 Report
The paper is a description of a hardware implementation of the algorithm proposed by the author in [19].
The proposed implementation significantly reduces the hardware resource consumption compared to the competing solution.
The authors have thoroughly described the prior designs,
and based on them, they have proposed their solution.
The paper describes the design in detail. However, it seems that recreating the author's solution based on the description could be difficult.
Certain statements seem to be unclear. In Algorithm 1, there is a "syndrome check" step (lines 24-25), which may limit the number of iterations. However, it is unclear if that step has been implemented in hardware (no appropriate block in Figure 1, constant number of iterations (10) assumed in the HW description).
In the final design efficiency assessment, it is unclear how the Hu coefficient is calculated. It is described as "a number of F7 MUXs, F8 MUXs, Flip-flops, LUTs, and BRAM bits used by the LDPC decoder". Does it mean that one BRAM bit has the same weight as one flip-flop or one MUX?
In the statement, "Although compared to [23], the proposed decoder has 1.7 times lower throughput and around 2 times higher HUE, it provides better decoding performance and memory efficiency.", the throughput ratio is described as 1.7, while HUE ratio as "around 2". It would be reasonable to apply the same accuracy - "2.4" instead of "around 2".
The statement about "10% decrease of the decoder's memory size" does not agree with the overall memory utilization given in Table 4. I suggest that authors better describe the meaning of both memory usage parameters.
Generally the paper is easy to read. There are some corrections needed regarding usage of articles and commas.
Certain sentences are not clear and could be rewritten for better clarity (e.g., lines: 23, 35-36, 64-65, 77-78, 135-136, 147-148, 206-208, 215-216, 247-249).
Author Response
Please see the attachment.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
This is an interesting article, describing an application of an FPGA implementation of a 5G LDPC decoder. In general, the text and figures are easy to follow and well explained.
The main question addressed is well defined and related to the definition of the problem. Is it possible to implement a hardware-efficient Low-Density Parity-Check (LDPC) decoder?
The previous unexplored area of research is identified. The area of research, LDPC decoders, is well known; but it was identified a good gap in the field with the reduction of hardware resources of FPGA implementation.
The paper presents an FPGA implementation for LDPC decoder architecture using the HOMS algorithm as the decoding kernel. Also, the architecture proposed exploits several techniques, such as pipelining, layered scheduling, appropriate quantization bits, partially parallel structure, and parallel processing datapath units.
The performance analysis of the architecture based on power consumption and delay parameters could be interesting.
Minor comments:
1.- Figure 1, the green line used to connect DECOM and VNU modules is missing some interconnection points. Only one font of text should be used in the figure.
2.- Figure 5, the correct name of modules is comparator.
3.- Figure 1, please explain if the implementation in the FPGA was using intellectual property (IP) modules or it was developed in VHDL or Verilog. It could be explained in section 4.
4.- In line 24 of introduction section, 3GPP should be defined.
5.- In line 321 of subsection 3.4, FTSU should be defined.
6.- Please explain the methodology to obtained the results of the implementation in the FPGA?
English language and style are fine/minor spell check required.
Author Response
Please see the attachment.
Author Response File: Author Response.pdf
