A Flexible Solid-State Marx Modulator Module Based on Discrete Magnetic Coupling Drivers

Abstract

With the increasing and deepening application of high-voltage nanosecond solid-state pulse generators in biological, industrial, and environmental fields, the development of existing pulse generators faces many challenges, such as fixed pulse shapes, the usage of isolated driver power supplies, lower power density, and limited output electrical performance. Hence, a novel high-frequency multilevel nanosecond modular solid-state Marx modulator (SSMM) based on discrete magnetic coupling gate drivers is proposed. The gate voltage of the two MOSFETs can be rapidly synchronized at a high repetition frequency to achieve an amplitude-controlled gate voltage within 100 ns. The feasibility of the driver was verified by PSpice simulation and prototype testing. Moreover, a stackable SSMM module (S²M³) structure is proposed to solve the problem of common-mode interference conducted through the driver, which improves the reusability, scalability, and redundancy of modulators. The characteristic parameters of the developed 14-stage S²M³ are as follows: an output voltage amplitude of 5.45 kV with a 100 ns–50 ms width, a minimum rise time of approximately 18 ns, and a continuous repetition frequency of 100 kHz. S²M³ has the ability to change the pulse shape, and the pulse frequency can reach 2.8 MHz within the burst.

1. Introduction

Different applications have distinct requirements for high-voltage pulses, and conventional pulse power generators can only produce rectangular or exponential waves [1,2,3]. As semiconductor technology advances, semiconductor switches have achieved remarkable improvements in switching speed and power handling capacity, with features such as small size, long lifespan, high switching frequency, and strong controllability gradually supplanting traditional gap switches, enabling the generator to output more adjustable electrical parameters with greater flexibility. The fundamental principle of a multilevel pulse modulator is to control the on-off state of a series of power semiconductor switches by generating adjustable pulses with variable rising/falling times, a flat top, reducing the output voltage rate of change (dv/dt), and reducing peak overshoot. It can also create different waveform shapes. In fields such as low-temperature plasma, pulsed electric field sterilization, electroporation biotechnology, electrical equipment insulation testing, and other pulse power applications, research has become increasingly popular [4,5,6,7].

There are several existing types of multilevel pulse modulators, such as linear transformer drivers (LTD), solid-state pulse power modulators (SSPPM), modular multilevel converters (MMC), and SSMM. Due to the magnetic core, LTD has low efficiency, a large volume, and an output pulse width constrained by the magnetic core characteristics [8]. SSPPM suffers from poor regulation accuracy due to charging voltage imbalances caused by transformer core differences [9]. MMC has modularized redundant scalability hardware features but also obvious drawbacks. It requires a high-voltage DC power supply for capacitor series charging and voltage sensors to ensure capacitor voltage balance [10]. Compared with these generators, SSMM has its own unique advantages. Marx is a kind of electrical circuit that can produce a high-voltage pulse from a low-voltage DC input. It has two basic operation steps: storage capacitor charging in parallel and discharging in series. The main advantage of parallel charging is that it can balance the charge of each stage capacitor without using voltage sensors. Marx pulse generators have various classic circuit topologies [11]. SSMM with the modular Marx multilevel converter diode (M³CD) cells in series stacking mode [12,13,14] has active pull-down characteristics that eliminate the need for pull-down resistors to achieve low loss and high repetition frequency of the output pulse, compared with [15].

Table 1. Comparison of drivers for solid-state pulse generators.

Type of Drivers	Non-Isolated Power Supply	Independent Control of All Switches	Insulation Reliability	Low Cost	Low Volume	Ref
Optocoupler driver	×	√	+	++	++	[16]
Optical fibers driver	×	√	+++	+	+	[9,15,17,18,19]
Series-core magnetic coupling driver	√	×	+++	+++	+++	[20,21,22,23,24]
Self-triggered driver	√	×	+++	+++	+++	[25,26]
Opto-magnetic driver	√	√	++	+	+	[27]
Proposed driver	√	√	++	+++	+++

Note: the number of “+” represents the evaluation level.

shows the key performance characteristics of existing drivers for pulse generators.

The gate drivers of each stage operate on elevated ground during the discharge [11]. In existing multilevel pulse generators, the drivers rely on multiple optical fibers or optocouplers to transmit trigger signals, which the driver chips then amplify to drive power semiconductor switches. Commercial optocoupler drivers typically have insulation of less than 5 kV, while optical fibers offer high isolation and response speed, making them the predominant driver for current multilevel pulse generators. Each optical fiber receiver and driver chip needs an isolated DC voltage of several to tens of volts to function properly. At present, commercially isolated DC-DC [15] converters, high-frequency isolation [16] transformers diode strings [28] and air-isolation modules [29] are the main isolated power supply methods. Miniaturization is the prevailing development trend of pulse generators [30] but numerous trigger optical fibers dispersed in space and the requisite isolated power supply impair space utilization and impede system integration, and fiber optic transceivers are more expensive [9,15,17,18,19]. Although some researchers have employed a self-triggered driver in Marx generators [25,26], it has certain constraints on capacitor charging voltage, and a self-triggered driver cannot control each semiconductor switch independently, which results in a long output pulse tail and a single pulse waveform. Such as series-core magnetic coupling [20,21,22,23,24] drivers, the driving power for all switches comes from the primary winding, which is connected to the half-bridge circuit, and high-voltage coaxial cables are necessary to transmit the drive signals, ensuring insulation while shielding against electromagnetic interference. It is the most economical solution for rectangular pulse generators; however, the ability to adjust the pulse waveform is poor. Opto-magnetic driver: the use of multiple optical fibers to transmit the trigger signals to the primary winding of each pulse transformer for amplification, then the pulse transformer to transmit the drive signals and magnetic isolation of the high-voltage output [27]. In this way, the maximum pulse width of the drive signal is limited by the saturation of the transformer core. Although optical fiber can ensure the synchronization of the signals and eliminate interference from the signal and FPGA controller, the power cost and footprint will increase.

The discrete magnetic coupling driver proposed in this paper is small in size, stable in operation, requires no optical signals for pulse control, has an isolated power supply, and uses high-voltage coaxial cables. The multi-channel trigger signals emitted by the field programmable gate array (FPGA) are transferred to each discrete magnetic coupling driver through a multi-core coaxial shielding cable after level conversion and modulated into bipolar narrow pulses through an independent on/off narrow pulse circuit. The accumulation of transformer remanence and saturation of the transformer core caused by long driving pulse widths are effectively avoided. The narrow pulse and energy are then transferred to the driving circuit through the finger-sized magnetic core to restore the drive signal and control the switching of each MOSFET. The coaxial shielding cable ensures the synchronization and reliability of multi-channel trigger signals.

It is worth noting that some common-mode interference will be conducted to the low-voltage control system through the transformer during the pulse discharge process [31] and the interference level is proportional to the voltage amplitude, repetition frequency, and rising/falling time of the output pulse. Although the common-mode inductor can be added outside the coaxial shielding cable or changed in the PCB design to increase the impedance on the common-mode conduction path, it is impossible to completely cut off the conduction path, which means the low-voltage control system may not work properly when designing pulse power sources with higher output electrical parameters.

Therefore, in this paper, firstly, a S²M³ structure based on the drivers is introduced. The S²M³ has an independent power supply, a Marx circuit, drivers, a control system, optical fiber communication, and synchronous starting. Under the condition of ensuring reliable and stable operation of one module, when several lower voltage modules are serially stacked to generate a higher voltage, the maximum voltage endured by each driver in each module and its common-mode interference intensity to the control system remain constant. In addition, the voltage and current pulse parameters can be expanded flexibly with only a few optical fibers and cable connections when stacked with multiple modules, eliminating the need for additional hardware circuits. The structure can not only enhance the output electrical parameter capability of SSMM but also improve its reusability, scalability, and redundancy, creating a dependable experimental platform for future studies on stacked structures.

The structure of this article is as below: In Section 2, the design of a stackable S²M³ structure, cable connections, and communication between modules are described. In Section 3, the switching timing sequence corresponding to pulse modulation and the working principle of the proposed driver are analyzed in detail, followed by the construction of a simulation model with PSpice, showing the feasibility of the topology and the effect of driving circuit parasitic inductance. In Section 4, a 14-stage S²M³ prototype using the proposed driver was built and tested, showing the production of the desired output characteristic. Finally, in Section 5, the results of this paper are summarized.

2. The Structure of a Stackable S²M³

Figure 1 shows a flexibly stackable S²M³ structure. An S²M³ comprises a Marx circuit, drivers, a control system, a step-down converter, and an optical fiber communication interface. In the n-stage solid-state Marx circuit topology, high-voltage diodes replace the traditional rechargeable inductors so that the output voltage is not boosted during discharge [32] Each stage of the M³CD cell consists of a high-voltage diode $D_{\mathrm{i}}$, a storage capacitor $C_{\mathrm{i}}$, and a half-bridge structure composed of a charging switch ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ and a discharging switch ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$. When all the charging switches ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ are triggered to switch on, the DC power supply charges all the capacitors in parallel to the specified voltage $U_{\mathrm{C}}$ through diode $D_{\mathrm{i}}$, as shown by the blue arrow. However, if a stage ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ is not on, the capacitors $C_{\mathrm{i}+1}$ after the stage will not be charged. Thus, the voltage $U_{\mathrm{C}\mathrm{i}}$ on each capacitor can be expressed as follows:

$$\left[\begin{array}{c}{U}_{\mathrm{C}1}\\ U_{\mathrm{C}2}\\ U_{\mathrm{C}3}\\ ⋮\\ U_{\mathrm{C}n-1}\\ U_{\mathrm{C}n}\end{array}\right]=\left[\begin{array}{c}1\\ {\mathrm{S}}_{\mathrm{b}1}\\ {\mathrm{S}}_{\mathrm{b}1}\cdot {\mathrm{S}}_{\mathrm{b}2}\\ ⋮\\ {\mathrm{S}}_{\mathrm{b}1}\cdot {\mathrm{S}}_{\mathrm{b}2}\cdot \cdots \cdot {\mathrm{S}}_{\mathrm{b}n-3}\cdot {\mathrm{S}}_{\mathrm{b}n-2}\\ {\mathrm{S}}_{\mathrm{b}1}\cdot {\mathrm{S}}_{\mathrm{b}2}\cdot \cdots \cdot {\mathrm{S}}_{\mathrm{b}n-3}\cdot {\mathrm{S}}_{\mathrm{b}n-2}\cdot {\mathrm{S}}_{\mathrm{b}n-1}\end{array}\right]\left[V_{\mathrm{dc}}\right]$$

(1)

where ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ or ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ denotes the state of each switch 1 is ON, and 0 is OFF. Simultaneously, the switches ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ provide a low-impedance discharge path for the stray capacitor $C_{\mathrm{s}}$ on the load to eliminate the slow tail of the pulse, as indicated by the green arrow.

When the switches ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ are off and the switches ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ are on, all capacitors are connected in series according to the purple arrow to generate a high-voltage pulse on the load. If a stage ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ is not triggered or switched on later than other switches, the current will flow from the body diode of ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ to the load, and the $C_{\mathrm{i}}$ fails to enter the discharge loop. The pulse voltage amplitude on load can be expressed as follows:

$$\left[U_{\mathrm{Load}}\right]={\left[\begin{array}{c}{\mathrm{S}}_{\mathrm{a}1}\\ {\mathrm{S}}_{\mathrm{a}2}\\ {\mathrm{S}}_{\mathrm{a}3}\\ ⋮\\ {\mathrm{S}}_{\mathrm{a}n-1}\\ {\mathrm{S}}_{\mathrm{a}n}\end{array}\right]}^T\left[\begin{array}{c}{U}_{\mathrm{C}1}\\ U_{\mathrm{C}2}\\ U_{\mathrm{C}3}\\ ⋮\\ U_{\mathrm{C}n-1}\\ U_{\mathrm{C}n}\end{array}\right]$$

(2)

The circuit has a simple topology, and its modular circuit features enable it to be expanded flexibly [33,34,35,36] to increase output voltage, current, adjustable level number, or generate bipolar positive and negative pulses. In this way, hardware layout and selection are not required, reducing design time and cost. Several expansion modes of power circuits are shown in Figure 2a–d.

Due to common-mode conduction interference, the output pulse amplitude of the generator based on discrete magnetic coupling drivers cannot be very high; however, the proposed driver can achieve a relatively low output pulse amplitude with a minimized volume, which can make the SSMM a compact structure and is conducive to the stacking study of S²M³ at a small volume and low cost. SSMM typically requires an additional DC power supply for the low-voltage control system, a high-frequency charging power supply or a low-voltage DC power supply to provide isolated power to the driver, and a high-voltage DC power supply for the energy storage capacitor. In contrast, discrete magnetically coupled drivers avoid the power consumed by multiple fiber emitters in the control system while eliminating the need to supply power for driver isolation. Therefore, it is convenient to use a step-down DC-DC converter to convert the first-stage storage capacitor from high voltage to low voltage DC to supply power to the control system and drivers. A transistor-transistor logic (TTL) signal is used to realize the closed-loop control of the converter. The way it works makes the reference ground potential of each module change regardless of the output potential relative to the ground of multiple S²M³s; however, it always matches the potential of the low voltage side of its own first-stage energy storage capacitor, which not only avoids exceeding the maximum electrical insulation level of the driver; however, maintains the intensity of the common mode interference of each module control system, which improves the reliability and stability of S²M³ output. In addition, S²M³s only need one external high-voltage DC power supply; therefore, the system is more integrated.

Figure 3 shows the optical fiber communication between modules. To facilitate communication between modules, each module comprises two sets of optical fiber-optic transceivers for communication and synchronous starting. The PC user interface employs UART communication to configure parameters for each module over communication fibers. The starting signal of the module will be calibrated by the main control chip for synchronous starting. Multiple S²M³s transmit starting signals and control signals through optical fiber interconnection to achieve module control and cooperative operation. As the main control chip, an FPGA with excellent synchronization and EMC capability is used. When the FPGA controller in each module receives the synchronous starting signal, it sends trigger signals that determine the ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ and ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ on/off states. By modifying the trigger signal timing sequence, a S²M³ can independently output nanosecond pulse parameters of adjustable rising/falling time, amplitude, pulse width, and frequency, or modules can collaborate to expand the electrical parameter capability.

3. Operation Principle of Proposed S²M³

3.1. Switching Timing Sequence under Pulse Modulation

Additional resistors or inductors are inserted into the charging loop to diminish the surge current [15,37]. The values of resistance and inductance are determined by the capacity of the storage capacitor, the charging time, and the number of M³CD cells, which will influence the charging speed and constrain the enhancement of the pulse repetition frequency. Under the magnetic coupling driving condition, there is no need for an additional power system to isolate the power supply, and the benefit of a convenient and controllable driving voltage under the system can be exploited. The driving voltage of the charging switch can be controlled when the initial voltage of the storage capacitor is lower for soft start, so that the ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ can operate in the constant current area to limit surge charging current. In the process of repetition frequency discharge, the ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ can be fully turned on by increasing the driving voltage, which will not affect the charging speed and prevent the cumulative effect of voltage top-up caused by insufficient charging at high repetition frequency. Voltage sensors and other control signals are not required for lower cost and complexity than charging from a current-controlled input source [35] or current source [22].

Since ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ and ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ can be on or off at distinct times, for each M³CD cell, the output pulse waveform is modified by rationally controlling the time when the storage capacitor is inserted or bypassed in the discharge loop, so as to satisfy the demands of different loads. Figure 4 illustrates the time sequence of trigger signals corresponding to three different classical pulse waveforms. It is assumed that the energy-storage capacitor voltage in the three stages is charged to $U_{\mathrm{C}}$ before discharge. The specific control timing of key parameters can be explained as follows.

(1) Pulse 1 ($t_{\mathrm{a}1}\le t\le t_{\mathrm{a}3}$): At time $t_{\mathrm{a}1}$ switches ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ are turned on simultaneously; when switches ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ are in the off state, the fastest rising edge is obtained on the load, and the rising time is denoted as $t_{\mathrm{r}}$, which is not only proportional to the turn-on time of the MOSFETs but also to the ratio of the stray inductance $L_{\mathrm{s}\mathrm{d}}$ of the discharge loop and the load resistance $R_{\mathrm{L}\mathrm{o}\mathrm{a}\mathrm{d}}$ (see the following formula):

$$t_{\mathrm{r}}\propto L_{\mathrm{sd}}/R_{\mathrm{Load}}$$

(3)

According to the set duty ratio and pulse repetition frequency, the duration of the trigger signal is regulated and the magnitude of the FWHM is adjusted. $t_{\mathrm{d}\mathrm{e}\mathrm{a}\mathrm{d}}$ indicates the dead time between switches ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ and ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ trigger signals to prevent short circuit of the bridge arm in M³CD cells. At time $t_{\mathrm{a}2}$, switches ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ turn on while switches ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ are completely off. While the storage capacitors are charging, $C_{\mathrm{s}}$ will discharge through ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ to obtain a fast falling edge. Because the $t_{\mathrm{d}\mathrm{e}\mathrm{a}\mathrm{d}}$ is so brief, $U_{\mathrm{L}\left(t\right)}$ is approximately a rectangular pulse. Conversely, if switches ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ are not on, the falling time is $t_{\mathrm{f}-\mathrm{m}\mathrm{a}\mathrm{x}}$, the voltage of the load can be computed in the following equations:

$$U_{\mathrm{L}(t)}=N{U}_{\mathrm{C}}{e}^{-\frac{t}{R_{\mathrm{Load}}{C}_{\mathrm{s}}}}$$

(4)

$$t_{\mathrm{f}-\max }=2.2R_{\mathrm{Load}}{C}_{\mathrm{s}}$$

(5)

(2) Pulse 2 ($t_{\mathrm{b}1}\le t\le t_{\mathrm{b}4}$): Clearly, if trigger signals fail to have good synchronization, it will affect the rise/fall times of the output pulse [18]. At time $t_{\mathrm{b}1}$, ${\mathrm{S}}_{\mathrm{a}1}$ is switched on, and $U_{\mathrm{C}1}$ first discharges from the ${\mathrm{S}}_{\mathrm{b}2}$ body diode to the load. $t_{\mathrm{d}\mathrm{i}}$ is the relative delay time of each stage of storage capacitor in series or by pass in the discharge loop. Due to the stray inductance and capacitance of the discharge loop, when $t_{\mathrm{d}\mathrm{i}}$ < $t_{\mathrm{r}-\mathrm{m}\mathrm{i}\mathrm{n}}$, the pulse rising time can be adjusted smoothly. For a discharge loop containing an n-stage M³CD cell, $t_{\mathrm{r}}$ can be estimated according to the following equation:

$$t_{\mathrm{r}}\approx t_{\mathrm{r}-\min }+{\displaystyle \sum _{i=1}^{n-1}{t}_{\mathrm{di}}}(0\le t_{\mathrm{di}}\le t_{\mathrm{r}-\min })$$

(6)

Similarly, at time $t_{\mathrm{b}2}$, ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ delay off, if $t_{\mathrm{d}\mathrm{i}}$ < $t_{\mathrm{f}-\mathrm{m}\mathrm{a}\mathrm{x}}$, the falling time $t_{\mathrm{f}}$ can be estimated according to the following equation:

$$t_{\mathrm{f}}\approx t_{\mathrm{f}-\max }+{\displaystyle \sum _{i=1}^{n-1}{t}_{\mathrm{di}}}(0\le t_{\mathrm{di}}\le t_{\mathrm{f}-\max })$$

(7)

After a brief $t_{\mathrm{d}\mathrm{e}\mathrm{a}\mathrm{d}}$, at time $t_{\mathrm{b}3}$, the switches ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ are on. Compared with [19] there will be no significant step phenomenon in the control sequence under low resistance loads. When fewer M³CD cells participate in the discharge, $t_{\mathrm{d}\mathrm{i}}$ should be set shorter to reduce pulse rising/falling edge oscillation [17]. Unlike traditional rectangular pulses, the high-voltage triangular waveform pulse $U_{\mathrm{L}\left(t\right)}$ has a slower, smoother rising and falling edge, reducing EMI in the system. Multiple delay trigger signals instead of prolonged Miller platform duration [38] lower switching losses.

(3) Pulse 3 ($t_{\mathrm{c}1}\le t\le t_{\mathrm{c}2n+1}$): When $t_{\mathrm{d}\mathrm{i}}$ > $t_{\mathrm{r}-\mathrm{m}\mathrm{i}\mathrm{n}}$ or $t_{\mathrm{d}\mathrm{i}}$ > $t_{\mathrm{f}-\mathrm{m}\mathrm{a}\mathrm{x}}$, a relatively obvious step wave will appear at the rising/falling edge of the pulse. FIFO control is usually used to achieve capacitor voltage balance. According to the idea of nearest-level modulation, the timing sequence has the ability to mimic $u_{\mathrm{L}\left(t\right)}$ [39]. Different parts of $u_{\mathrm{L}\left(t\right)}$ is approximated by the superposition of equal voltage steps $U_{\mathrm{C}}$ produced by each M³CD cell, regardless of what the exact waveform is like in each part. Thus, the insertion of a specific number of capacitors at a certain time interval [$t_{\mathrm{c}\mathrm{i}}$,$t_{\mathrm{c}\mathrm{i}+1}$] and [$t_{\mathrm{c}\mathrm{j}}$,$t_{\mathrm{c}\mathrm{j}+1}$] can generate an approximate waveform of $u_{\mathrm{L}\left(t\right)}$. When capacitors are not inserted, $u_{\mathrm{L}\left(t\right)}$ is 0. The switching moments $t_{\mathrm{c}\mathrm{i}}$ and $t_{\mathrm{c}\mathrm{j}}$ can be computed according to the following equation:

$$\{\begin{array}{l}{u}_{\mathrm{L}}(t_{\mathrm{ci}})=(i-\frac{1}{2})U_{\mathrm{C}},i=1,2,\cdots ,n\\ u_{\mathrm{L}}(t_{c\mathrm{j}})=(2n-j+\frac{1}{2})U_{\mathrm{C}},j=n+1,n+2,\cdots 2n\end{array}$$

(8)

The above three control modes can be combined freely. When the load changes, the switching timing sequence can be adjusted to match the impedance of the S²M³ with the impedance of the load, and different pulse waveforms can be output to meet the requirements of the load. Compared with adding hardware delay to the drive circuit [21], it has higher accuracy and flexibility.

3.2. The Working Process of Proposed Driver

The structure of a discrete magnetic coupling driver is shown in Figure 5. Multiple trigger signals are decomposed by an on/off narrow pulse circuit for a positive turn-on drive signal and a negative turn-off drive signal. The ring transformer will isolate and transmit the drive signal $V_{\mathrm{T}}$ to the gate drive circuit for restoration. By adjusting the voltage $U_{\mathrm{L}\mathrm{V}}$, the driving voltage amplitude of the switch can be easily changed to realize the switch’s operation in different working areas. The details of the operational principle can be analyzed as shown in Figure 6.

(1) Turn-on Transient State [As Shown in Figure 6a]: Taking the on/off of discharge switches ${\mathrm{S}}_{\mathrm{a}1}$ and ${\mathrm{S}}_{\mathrm{a}2}$ as an example. $R_3$ and $C_1$ constitute a series RC circuit, as performed $C_2$ and $R_4$. When $V_{\mathrm{a}1}$, a trigger signal, reaches a high level, $C_1$ begins to charge, while $C_2$ quickly discharges to inverter $T_{\mathrm{i}}$ through $R_4$ paralleling schottky diode $D_6$. The speed of discharge is determined by the driving capacity of $T_{\mathrm{i}}$. $V_{{\mathrm{T}}_{\mathrm{c}\mathrm{i}-\mathrm{H}}}$ and $V_{{\mathrm{T}}_{\mathrm{c}\mathrm{i}-\mathrm{L}}}$ are respectively the high threshold voltage and low threshold voltage of the window comparator $T_{\mathrm{c}\mathrm{i}}$. At this point, input voltage $V_{{\mathrm{T}}_{\mathrm{c}2-\mathrm{i}\mathrm{n}}}$ of $V_{{\mathrm{T}}_{\mathrm{c}2}}$ is fixed at a negative value equal to forward voltage drop of $D_6$, when $V_{{\mathrm{T}}_{\mathrm{c}2-\mathrm{i}\mathrm{n}}}$ < $V_{{\mathrm{T}}_{\mathrm{c}2-\mathrm{L}}}$, ${\mathrm{S}}_3$ turns on. The input voltage $V_{{\mathrm{T}}_{\mathrm{c}1-\mathrm{i}\mathrm{n}}}$ of $V_{{\mathrm{T}}_{\mathrm{c}1}}$ can be computed according to the following equation:

$$V_{\mathrm{Tc}1\_\mathrm{in}}=V_{\mathrm{a}1}{e}^{-\frac{t}{R_3{C}_1}}$$

(9)

When $V_{{\mathrm{T}}_{\mathrm{c}1-\mathrm{i}\mathrm{n}}}$ < $V_{{\mathrm{T}}_{\mathrm{c}1-\mathrm{L}}}$, switch ${\mathrm{S}}_1$ is off, the positive drive signal time $t_{\mathrm{s}\mathrm{p}}$ can be derived combining Formula (9) as shown in the following equation:

$$t_{\mathrm{sp}}=R_3{C}_1\ln \frac{V_{\mathrm{a}1}}{V_{\mathrm{Tc}1-\mathrm{L}}}$$

(10)

On the secondary side of the transformer, the positive drive signal first turns on $Q_2$ and the current will pass through diodes $D_1$ and $D_4$ to the capacitors $C_{\mathrm{s}1}$ and gate capacitors $C_{\mathrm{g}\mathrm{s}}$ of switches ${\mathrm{S}}_{\mathrm{a}1}$ and ${\mathrm{S}}_{\mathrm{a}2}$ Meanwhile, the gate capacitor of $Q_1$ is reversely charged, keeping $Q_1$ at a negative voltage that prevents it from turning on erroneously because the magnetic field energy stored in the magnetic core and the electric field energy stored in the equivalent capacitance will generate a recoil voltage on the secondary side of the transformer after the positive drive signal ends. $t_{\mathrm{s}\mathrm{p}}$ is limited by the cores, and it needs to meet the following expression [23]:

$${\displaystyle {\int }_0^{t_{\mathrm{sp}}}{V}_{\mathrm{T}}dt=}{\displaystyle {\int }_0^{B_{\mathrm{s}}}N\beta A_{\mathrm{w}}dB=}N\beta A_{\mathrm{w}}{B}_{\mathrm{s}}$$

(11)

where N is the number of turns on the primary side, β is the packing factor, $A_{\mathrm{w}}$ is the cross-sectional area of the magnetic core, and $B_{\mathrm{s}}$ is saturation flux.

(2) Turn-on/off Holds State [As Shown in Figure 6b]: Turn-on time $T_{\mathrm{w}}$ for switches ${\mathrm{S}}_{\mathrm{a}1}$ and ${\mathrm{S}}_{\mathrm{a}2}$ depends on the dead time between the positive and negative drive signals. At the time, $Q_1$ and $Q_2$ are off in the dead time, and the electrical power of $C_{\mathrm{s}1}$ and $C_{\mathrm{g}\mathrm{s}}$ is unable to be released. If the trigger signal is longer, the $V_{\mathrm{g}\mathrm{s}}$ holding time is mainly determined by the zero gate voltage drain current $I_{\mathrm{D}\mathrm{S}\mathrm{S}}$ of $Q_1$. The maximum conduction time of the switch can be calculated according to the following equations:

$$T_{\mathrm{w}-\max }=\frac{(C_{\mathrm{s}1}+C_{\mathrm{gs}})(V_{\mathrm{T}}-V_{\mathrm{th}})}{I_{\mathrm{DSS}}}$$

(12)

where $V_{\mathrm{t}\mathrm{h}}$ is the threshold voltage of the switch. $C_{\mathrm{s}1}$ affects the output pulse width of S²M³ and can reduce bridge arm crosstalk to some extent [40]. Since the primary side inductance of the transformer has a short continuous flow process, an appropriate increase of $R_2$ in turn-on hold state can further prevent $Q_1$ from being mistakenly turned on due to the transfer of residual energy in the inductance to the secondary side of the transformer. Moreover, when $T_{\mathrm{w}}$ < $t_{\mathrm{s}\mathrm{p}}$, the turn-on holds state disappears.

(3) Turn-off Transient State [As Shown in Figure 6c]: When $V_{\mathrm{a}1}$ is low, the circuit works similarly to the turn-on transient state. ${\mathrm{S}}_2$ and ${\mathrm{S}}_4$ are on, and a negative turn-off drive signal appears on the primary side of the transformer. The duration of the negative drive signal $t_{\mathrm{s}\mathrm{n}}$ can be derived as shown in the following equation:

$$t_{\mathrm{sn}}=R_4{C}_2\ln (\frac{V_{\mathrm{a}1}}{V_{\mathrm{Tc}2\_\mathrm{L}}})$$

(13)

with $Q_1$ turns on, the current will charge the $V_{\mathrm{g}\mathrm{s}}$ to a negative voltage through diodes $D_2$ and $D_3$. The amplitude of the voltage depends on $t_{\mathrm{s}\mathrm{n}}$ and $R_2$. Since there is no discharge circuit on the secondary side of the transformer, $V_{\mathrm{g}\mathrm{s}}$ stays almost constant. A negative bias voltage makes the switch turn off reliably and reduces the parasitic conduction caused by the MOSFET Miller capacitor to some extent. The anti-EMI capability of the system will be improved.

The proposed driving circuit uses high-speed switching diodes $D_1$–$D_4$ to prevent current from flowing through the body diodes of $Q_1$ and $Q_2$. Otherwise, the slow reverse recovery time would cause $V_{\mathrm{g}\mathrm{s}}$ to drop when positive and negative drive signals reach 0. The short-circuit protection resistor $R_{\mathrm{p}}$ limits the short-circuit energy by changing the operating point of the switches ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ in the active region during a fault. The relationship between short circuit current $I_{\mathrm{c}}$ and $V_{\mathrm{g}\mathrm{s}}$ as shown in the following expression:

$$V_{\mathrm{gs}}=V_{\mathrm{T}}-I_{\mathrm{c}}{R}_{\mathrm{p}}$$

(14)

$R_{\mathrm{p}}$ is very low and negligible in normal operation. $R_{\mathrm{g}}$ reduces the gate voltage oscillation and surge current of the MOSFET in the drive loop.

3.3. Simulation of Proposed Driver

A simulation model was established by PSpise 17.4 simulation software, and the influence of changing positive and negative drive signal pulse width and stray inductance on gate voltage was studied by using the global parameter scanning function. $Q_1$ and $Q_2$ are PSpice models for the MOSFETs DMG4822SSD provided by the manufacturer. The UCC27517 integrated chip includes a push-pull circuit and Schmidt trigger, with high and low threshold voltages of 2.2 V and 1.2 V, respectively. The specific parameters are shown in

Table 2. Main simulation parameters of the driver.

Parameter	Value
$R_1$,$R_2$	1 $\mathsf{\Omega }$
$C_{\mathrm{s}1}$,$C_{\mathrm{g}\mathrm{s}}$	3 $\mathrm{n}\mathrm{F}$
$R_{\mathrm{g}}$	3 $\mathsf{\Omega }$
$R_{\mathrm{p}}$	0.08 $\mathsf{\Omega }$

.

When the width of the trigger signal $V_{\mathrm{a}1}$ is 500 $\mathrm{n}\mathrm{s}$. The pulse widths of the different positive drive signals and the corresponding gate voltage are shown in Figure 7a,b. Here, $C_1$ is 200, 300, 400, 500, 700 $\mathrm{p}\mathrm{F}$, respectively. $R_1$ is 300 $\mathsf{\Omega }$. $C_2$ and $R_2$ are 300 $\mathrm{p}\mathrm{F}$ and 300 $\mathsf{\Omega }$ respectively. The positive drive signal pulse width can be adjusted, and the maximum gate voltage amplitude becomes stable as the drive signal pulse width increases. Figure 7c,d show pulse widths of the different negative drive signals and the corresponding gate voltage. Here, $R_2$ is 200, 300, 400, 500, 700 $\mathsf{\Omega }$, $C_1$ and $R_1$ are 300 $\mathrm{p}\mathrm{F}$ and 400 $\mathsf{\Omega }$ respectively. Such as the positive drive signals, the reverse voltage is caused by stray inductance $L_{\mathrm{s}}$ of the drive loop, and the amplitude of $V_{\mathrm{g}\mathrm{s}}$ is controllable when the width of the trigger signal $V_{\mathrm{a}1}$ is 200 $\mathrm{n}\mathrm{s}$, and $C_1$ and $R_1$ are 400 $\mathrm{p}\mathrm{F}$ and 900 $\mathsf{\Omega }$ respectively. Since the pulse width of the trigger signal is smaller than that of the positive drive signal, there is no dead time between the positive and negative drive signals, and the drive signal and the corresponding gate voltages are shown in Figure 7e.

Obviously, the gate voltage will be lower than the drive voltage because of the high-speed switching diodes’ voltage drop and drive resistance in the drive loop on the secondary side of the transformer, which will affect the switching performance of the MOSFETs and the width of the S²M³ maximum output pulse. In the process of setting up the rising edge of the pulse, the stray inductance resonates with the gate capacitance to increase $V_{\mathrm{g}\mathrm{s}}$. Figure 7f presents the waveforms of the gate voltage with the different stray inductances, including 0.01, 0.08, 0.12, 0.16, and 0.20 $\mathrm{\mu }\mathrm{H}$. Here, the pulse width of the trigger signal $V_{\mathrm{a}1}$ is 1 $\mathrm{\mu }\mathrm{s}$, $C_1$ and $R_1$ are 300 $\mathrm{p}\mathrm{F}$ and 400 $\mathsf{\Omega }$, $C_2$ and $R_2$ are 300 $\mathrm{p}\mathrm{F}$ and 150 $\mathsf{\Omega }$.

4. Experimental Results

To demonstrate the operation of the proposed S²M³ and validate the simulation structure, a prototype is developed, as shown in Figure 8a. The prototype includes a high-voltage charging power supply, an auxiliary power supply, an FPGA controller, a 14-stage Marx, and a high-voltage output circuit. The auxiliary power supply is a commercial DC-DC converter module that can handle a maximum input DC voltage of 430 V. In Figure 8b, space is reserved in the middle for larger storage capacitors that can remain idle when only a narrow pulse with a fast rising edge is output.

For drivers, the isolation voltage level of each driver depends on the distance between the primary and secondary windings and the insulation strength between the core and the windings. The drivers of each stage operate at a stepped-up ground potential when capacitors discharge in series, and the maximum isolation voltage should be ${nV}_{\mathrm{d}\mathrm{c}}$. The selection of the same size core for each driver guarantees the modularity of the circuit structure. The gate driver and the width and height are implemented within the dimensions of 23 (W) mm × 44 (H) mm, which can be allowed to operate reliably at voltage levels above 10 kV. The driver has stable operation, low circuit loss, and a simple power supply. By sharing a ring core to drive two MOSFETs, it compensates for the lower input voltage of the auxiliary power supply and improves the compactness of the overall volume.

Since the S²M³ outputs a multilevel pulse, the discharge loop passes through the body diode of the charging switches. A long reverse recovery time may exacerbate pulse-rising edge oscillations. Here, the charging switches choose SiC MOSFETs (CMW120R080M1) with a short reverse recovery time. Additionally, since the maximum voltage of switches in actual operation is around $V_{\mathrm{d}\mathrm{c}}$, from the perspective of cost, the selection of discharge switches with good on/off characteristics of Si MOSFETs (IPP50R280CE). The amorphous magnetic cores with higher permeability are selected, and the stray inductance of the drive loop is changed by changing the number of turns of the winding.

Differential probe RP1025D (Rigol, Ltd., Soochow, China) was used to test drivers. Here, $C_1$ and $C_2$ is 200 $\mathrm{p}\mathrm{F}$, $R_3$ is 960 $\mathsf{\Omega }$, $R_4$ is 360 $\mathsf{\Omega }$. As shown in Figure 9a, the primary side waveform of the transformer is a positive and negative narrow pulse. Although the rising/falling edge of gate voltage will slow down when the turns ratio is 2:2, the amplitude of $V_{\mathrm{g}\mathrm{s}}$ be increased to compensate for driving voltage loss. Figure 9b shows the voltage waveforms of the driver signals and the 200 $\mathrm{n}\mathrm{s}$ gate voltage at the 2:2 turn ratio. Rapidly increasing and decreasing $V_{\mathrm{g}\mathrm{s}}$ are crucial for a nanosecond output pulse, where there is no dead time between positive and negative drive signals and slight voltage oscillations are insufficient to affect circuit operation.

Figure 9c visually displays the gate voltage waveform during 100 $\mathrm{k}\mathrm{H}\mathrm{z}$ high repetition operation. The amplitude of gate voltage reduces due to the permeability of the amorphous magnetic core decreasing near 100 $\mathrm{k}\mathrm{H}\mathrm{z}$. Without replacing the magnetic core material, the magnetic core operating point can be magnetized from the third quadrant of the hysteresis loop by increasing the time of the negative drive signal. As shown in Figure 9d, the blue waveform represents switches’ ${\mathrm{S}}_{\mathrm{a}\mathrm{i}}$ gate voltage, while the red waveform represents switches’ ${\mathrm{S}}_{\mathrm{b}\mathrm{i}}$ gate voltage. It can be found that the amplitude of $V_{\mathrm{g}\mathrm{s}}$ is increased in this way.

The probe was P6015A (Tektronix, Ltd., Beaverton, OR, USA). The oscilloscope used was the DSO-X3024T (bandwidth 200 $\mathrm{M}\mathrm{H}\mathrm{z}$, Keysight, Ltd., Santa Rosa, CA, USA). Under a 5 $\mathrm{k}\mathsf{\Omega }$ high-voltage noninductive resistor with different $V_{\mathrm{d}\mathrm{c}}$, the pulse width is 2 $\mathrm{\mu }\mathrm{s}$ and the frequency is 10 $\mathrm{k}\mathrm{H}\mathrm{z}$. The load voltage waveform is shown in Figure 10a. When $V_{\mathrm{d}\mathrm{c}}$ is regulated between 100 $\mathrm{V}$ and 400 $\mathrm{V}$, load voltage varies between 1.2 $\mathrm{k}\mathrm{V}$ and 5.45 $\mathrm{k}\mathrm{V}$. With a charging voltage of 400 $\mathrm{V}$, the output voltage efficiency of the generator is 97.3%. The top overshoot of the output pulse is mainly due to underdamped oscillation caused by discharge loop equivalent series inductance and MOSFETs fast switching speeds. Additionally, after the pulse ends, the active pull-down circuit starts working to obtain a rapid falling edge. Figure 10b illustrates the waveforms with widths ranging from 100 to 500 $\mathrm{n}\mathrm{s}$. At this time, the charging voltage is set to 150 $\mathrm{V}$, the frequency is 10 $\mathrm{k}\mathrm{H}\mathrm{z}$, and the load is a 200 $\mathsf{\Omega }$ high-voltage noninductive resistor. The output pulse’s rising and falling edges with different pulse widths are almost the same. The above can fully verify the pulse amplitude and pulse width, which can be flexibly adjusted.

In order to test the output performance of the generator at high frequency and the ability to output with a long pulse width. In the $V_{\mathrm{d}\mathrm{c}}$ is 400 $\mathrm{V}$ and the load is 5 $\mathrm{k}\mathsf{\Omega }$, 100 $\mathrm{k}\mathrm{H}\mathrm{z}$ continuous high repetition frequency pulse test result is shown in Figure 10c. It can be proven that stable gate driving is possible. Figure 10d shows a pulse waveform with a pulse width of 50 $\mathrm{m}\mathrm{s}$ under a no-load condition where the active pull-down circuit is not set to work. The pulse falling edge is about 18 $\mathrm{m}\mathrm{s}$ which can significantly limit the performance of the S²M³ at high repetition frequencies.

The switching timing sequence of multiplex delay is tested with a 200 $\mathsf{\Omega }$ load in Figure 10e. Figure 10a shows a pulse train with different voltage amplitudes and pulse widths that can output 2.8 $\mathrm{M}\mathrm{H}\mathrm{z}$ for the burst operation within the safety switching margin by inserting or bypassing varying numbers of capacitors at different times. Figure 10f shows the experimental results of smooth adjustment of the rising and falling edges. There are six turn-on delays. If all turn-on delays $t_{\mathrm{d}\mathrm{i}}$ are 0 ns, the minimum rising time $t_{\mathrm{r}}$ is about 18 $\mathrm{n}\mathrm{s}$. When $t_{\mathrm{d}\mathrm{i}}$ = 10 $\mathrm{n}\mathrm{s}$, there is no obvious step phenomenon at the rising edge, and $t_{\mathrm{r}}$ is about 68 $\mathrm{n}\mathrm{s}$, which is similar to the calculation of Formula (6). When $t_{\mathrm{d}\mathrm{i}}$ = 20 ns, it is remarkable that there is an obvious step trend in the process of rising edge; however, the trend decreases with increasing numbers of inserted capacitors due to discharge loop stray inductance changes. The step pulse can be generated when $t_{\mathrm{d}\mathrm{i}}$ = 100 $\mathrm{n}\mathrm{s}$. The dynamic adjustment range of $t_{\mathrm{r}}$ and $t_{\mathrm{f}}$ mainly depends on switching speed and different load parameters. This verifies that the proposed S²M³ can flexibly adjust pulse shapes under the different switch timing sequences as previously described.

5. Conclusions

In this article, a multilevel nanosecond S²M³ based on discrete magnetic coupling drivers is developed, and the following conclusions are drawn.

(1)

The proposed driver uses a magnetic coupling method instead of an optical signal for pulse control there is no need for a separate power source for isolating. As a consequence, the volume and cost of the modulator can be reduced.

(2)

Discrete magnetic coupling drivers have the ability to output long pulse widths and synchronous or delayed driving of all solid-state switches, enabling the pulse generator to change the pulse shape.

(3)

The negative gate voltage amplitude can be adjusted to prevent MOSFET parasitic conduction and ensure its reliable turn-off, and the positive gate voltage amplitude of charging switches can be controlled for soft start.

(4)

S²M³ has a compact structure and simple communication between modules; the maximum voltage endured by each driver in each S²M³ and its interference intensity to the controller remain constant when modules are serially stacked to generate higher voltage, which facilitates cascading and expansion of voltage and current parameters in the future.

(5)

At present, the output parameters obtained are as follows. The prototype has a voltage amplitude up to 5.45 $\mathrm{k}\mathrm{V}$ with 100 $\mathrm{k}\mathrm{H}\mathrm{z}$ within the continuation and 2.8 $\mathrm{M}\mathrm{H}\mathrm{z}$ within the burst. The pulse shapes can be altered, and the pulse width is continuously adjustable within 100 $\mathrm{n}\mathrm{s}$ to 50 $\mathrm{m}\mathrm{s}$.

On the other hand, the proposed gate driver is compatible with other solid-state switches. A push-pull circuit with a larger current flow capacity can increase and decrease gate voltage more rapidly, reducing switch synchronization errors and drive pulse width. Furthermore, using ferrite cores with superior high-frequency characteristics can improve pulse repetition frequency.