A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing

Abstract

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works.

1. Introduction

Successive approximation register (SAR) analog-to-digital converters (ADCs) are attractive medium resolution applications for the development of the CMOS technologies because of their amplifier-free structure, small area and high energy efficiency [1,2,3,4,5]. For a 10 b resolution, the sampling rate limit of conventional SAR ADC is around 320 MS/s in 20 nm CMOS [5]. To achieve higher speeds while ensuring the precision of ADC, numerous new structures have been recently reported. The 2 b/cycle SAR converts 2-bit data in a single comparison cycle, achieving high speeds by reducing the number of cycles [6]. However, this approach is sensitive to accuracy issues caused by comparator offset and input common-mode (CM) voltage variation due to the use of three comparators. Another high-speed structure is hybrid pipelined-SAR ADC, which divides the entire SAR ADC into multi-stage to operate in parallel [7,8]. While the pipelined-SAR structure can operate at a high sample rate, the design of inter-stage amplifiers in advanced technology poses challenges and requires several calibration techniques to ensure accuracy. These techniques, in turn, result in additional power consumption and occupied area. Subranging SAR ADCs reduce the settling time of the first few MSBs to increase speed while enough redundancy range or compensation are needed because of gain mismatch [9,10,11]. Furthermore, the time-interleaved (TI) SAR ADCs are widely favored for the implementation of high-speed ADCs. In contrast to single-channel ADCs, TI-ADCs interweave multi-channel sub-ADCs to operates at a multiplied sample rate. The sub-ADCs can be implemented by a variety of ADC structures, such as SAR, VCO, pipeline, etc. Since SAR ADCs have the merits of low power and hardware overhead, they are the first choice for time-interleaving with acceptable costs to achieve higher ADC sampling rate. However, inter-channel nonidealities, such as time skews, gain mismatch and comparator offset mismatch introduced by device mismatch, which induce time-dependent errors into the spectrum and limit the accuracy of TI-SAR ADC. Each sub-ADC typically adopts a simplified structure to minimize non-ideal effects and maintain ADC linearity. In TI-SAR ADC, time skews and gain mismatch can be addressed through off-chip digital calibration algorithms and with an on-chip tunable device. However, this article primarily focuses on the offset mismatch resulting from non-idealities in the comparators, as this factor has the potential to impact the dynamic performance of the ADC.

In recent years, numerous methods have been proposed to address the offset mismatch issue in SAR ADC. In [12,13,14], a background calibration was applied in comparators to compensate offset, where the analog calibration voltage needs to be refreshed periodically, occupying additional conversion time and power. Foreground offset calibration, which relies on a differential capacitor array [15,16,17], is another popular approach. Nevertheless, the introduction of additional capacitive load in this method degrades the speed of the comparators. Alternatively, the ADCs discussed in [18,19] utilize CDACs to calibrate offset voltage of high-speed comparator. However, a notable drawback of this approach is the increased area requirement for additional arithmetic circuits.

In this paper, we propose a novel TI-SAR ADC based on comparator multiplexing to address the offset mismatch bottleneck. With a switching circuit, the comparator can operate almost continuously across multiple channels, allowing for a reduction in the number of comparators. This not only lowers the hardware cost but also minimizes the impact of offset. The comparator multiplexing structure enables the use of a small calibration-free comparator, meeting the offset requirements and ensuring ADC dynamic performance without significant power or speed penalties. In this article, we present a 10-bit 400 MS/s TI-SAR ADC implemented in 40 nm CMOS, employing comparator multiplexing. Split CDACs and double-tail dynamic comparators with clock decoupling are applied to eliminate comparator input common mode shift and reduce offset dynamic variation. With the impact of offset, the proposed design shows excellent precision improvement compared to the conventional one.

The remainder of this paper is organized as follows. The design considerations of the proposed comparator multiplexing TI-SAR ADC are introduced in Section 2. Detailed circuit implementation is described in Section 3, followed by the simulated results in Section 4. Finally, a conclusion is drawn in Section 5.

2. Design Considerations

2.1. Conventional Architecture of TI-SAR ADC

Figure 1 illustrates the conventional architecture of N-channel TI-SAR ADC. This architecture comprises an analog interleaver, N sub-SAR ADCs, digital MUX and calibration circuits. A comparator, a differential CDAC, bootstrapped switch and multiple logic circuits form the basic structure of each sub-SAR ADC. The analog interleaver is responsible for feeding the analog input signal into each channel in turn and generating N clock signals with equal phase difference to drive each sub-ADC sequentially. And then, sub-ADCs alternately output digital codes which are selected sequentially by digital MUX and the final digital output will be produced. To mitigate clock skews and inter-channel gain mismatch, tunable capacitors can be incorporated into the clock generator within the interleaver. These capacitors help reduce clock skews using a foreground digital calibration algorithm. However, offset mismatch can vary with input and PVT conditions, thereby limiting the dynamic performance of the ADC. Consequently, considerable effort is typically required to minimize the offset and achieve 10-bit accuracy.

2.2. Offset Mismatch in TI-SAR ADC

As an important module of TI-SAR ADC, the comparators determine the correctness of bit-cycles, and their offset mismatch will introduce periodic error during data conversion [20]. The relationship between the signal-to-noise-and-distortion ratio (SNDR) of the ADC and the offset mismatch of the comparator can be expressed as [18]

$$SNDR\approx 20{\mathit{log}}_{10}\left(\frac{V_A}{\sqrt{2}{\sigma }_{om}}\right)-10{\mathit{log}}_{10}\left(1-\frac{1}{N}\right)$$

(1)

where $V_A$ represents the input signal amplitude and ${\sigma }_{om}$ represents the standard deviation of equivalent offset voltage. N denotes the total number of comparators utilized in the ADC. To illustrate, in a dual-channel TI SAR ADC aiming for a 62 dB SNDR (10-bit resolution) with $V_A$ set at 0.9 V, it is necessary to optimize the comparator offset voltage to be less than 0.7 mV. The offset voltage in a comparator is closely related to the threshold-voltage and process transconductance of transistors, as well as the comparator area and overdrive voltage of input pair. This relationship can be expressed as

$${\sigma }_{os}\propto {\sigma }_{Vt}+{\left(V_{gs}-V_{th}\right)}_{in}\left({\sigma }_K/K+{\sigma }_{W/L}/\left(W/L\right)\right)$$

(2)

where ${\sigma }_{Vt}$, ${\sigma }_K$ and ${\sigma }_{W/L}$ represent standard deviation of transistors threshold-voltage, process transconductance and width-to-length ratio, respectively. Additionally, the process transconductance mismatch is associated with the mobility mismatch ${\sigma }_u$, which along with ${\sigma }_{Vt}$, are inversely correlated with the square root of device area [20].

$${\sigma }_{Vt}\&{\sigma }_u\propto 1/\sqrt{WL}$$

(3)

This means either a large area and power consumption or circuit calibrations will be needed for low-offset comparator design. Additionally, maintaining a constant and low input common mode voltage is crucial to reduce the overdrive voltage and minimize the equivalent input offset voltage. However, this requirement also leads to smaller bias current and longer comparator integration time, creating a trade-off between speed and accuracy. Furthermore, any asymmetry in the layout will introduce offset, the input differential pairs of the comparator should be designed symmetrically enough to cancel parameter gradient.

2.3. Comparator Multiplexing TI-SAR ADC

To enhance the accuracy, optimization area, power consumption and speed, a novel TI-SAR ADC based on comparator multiplexing is proposed. The architecture of this ADC is illustrated in Figure 2. Unlike conventional TI-SAR ADCs, each channel in the proposed one does not contain an individual comparator and corresponding asynchronous comparator clock generator, which are integrated into the comparator array. To mitigate the impact of offset mismatch on ADC accuracy and reduce hardware costs, each comparator is switched to different channels using a bootstrapped (BT) switch array. The kick back noise is reduced by the double-tail structure in the comparator. The output digital code of each channel is integrated by MUX, which is no different from the conventional structure of TI-SAR ADC.

In conventional TI-SAR ADC, offset mismatch can lead to fixed spurious whose amplitude depends on offset mismatch at the integer multiple of each channel sampling frequency [21]. By utilizing a comparator multiplexing architecture, the total comparator number in the proposed ADC is reduced since each comparator can be switched to any channel and remain operational for most of the time. In contrast, conventional ADCs only activate the comparators during the conversion phase and leave them idle during the sampling phase. Consequently, the utilization rate of comparator rises in the proposed structure. Additionally, as the number of comparators and associated asynchronous comparator clock generators decreases, the SNDR of TI-SAR ADC improves according to (1).

In a conventional TI-SAR ADC, when the duty cycle of single channel input clock is denoted as p (where p < 100%, representing conversion phase) and the clock cycle is T, the total conversion time is N × p × T for a N-channel TI-SAR ADC. Based on comparator multiplexing architecture, the number of comparators should be more than N × p (usually N in conventional structure) since the operating time of one comparator is from p × T to T. In the case of a 10-bit resolution, the value of p is typically smaller than 75% to allow for a sufficiently long sampling time, ensuring sampling accuracy. For example, if the duty cycle of conversion phase is 75%, a 64-channel comparator multiplexing TI-SAR ADC would normally use at least 48 comparators. In general, ADCs with higher duty cycle clocks can achieve higher sampling rate. However, they also impose more constraints on the design of the clock generator than the clock of 50% duty cycle [22]. By employing comparator multiplexing, the comparators can switch between every channel and realize the single-comparator operating time of nearly T. Additionally, an additional comparator controlled by pseudo-random signals can be applied in the proposed ADC. This extra comparator randomly switches with a comparator that would be assigned to a new channel in the next conversion. However, random switching would significantly increase the complexity of the switch network. Therefore, further study and analysis are required to extend it to multi-comparator scenarios.

3. Circuit Implementation

3.1. Dual-Channel TI-SAR ADC

In order to highlight the advantages of the comparator multiplexing structure, we propose a dual-channel TI-SAR ADC that utilizes only one comparator, thereby eliminating the impact of offset mismatch. Figure 3 illustrates the architecture and corresponding time diagram of the proposed dual-channel TI-SAR ADC with comparator multiplexing. This TI-SAR ADC configuration comprises a clock divider (CLKM), a multiplexed comparator with bootstrapped switch array, a multiplexer (MUX) array and two channel modules. Each module consists of a differential CDAC, bootstrapped sampling switches and SAR logic control circuit. Note that each channel contains neither a comparator nor an asynchronous comparator clock generator. Two channel modules share a comparator as well as an asynchronous comparator clock generator externally. The CLKM module divides external 400 MHz clock (CK) into two 200 MHz sub-clocks (CK1, CK2) for each channel, which will generate control signals further for switches and MUXs. As a result, no extra control signal generator is needed for the BT switch array and MUX array. The timing diagram in Figure 3 shows the detail of the clock signals. During the high phase of CK1 (channel 1 sampling phase) and the low phase of CK2 (channel 2 data conversion phase), the switchable comparator is connected to channel 2 for data conversion. The sub-clocks have a duty cycle close to 50% for channel sampling, which helps simplify the design of the S/H circuit. Following the sampling phase in each channel, a short switching phase (CS) is allocated for the comparator switching between two channels, without incurring a speed penalty for the ADC.

The switch array is designed to connect the CDAC in each channel to the switchable comparator. In order to ensure signal linearity, differentially bootstrapped switches are used in the array. The control signals of these bootstrapped switches are in phase with the clock of the connected channel. With the exception of the narrow switching phase, the multiplexed comparator remains in a state of continuous comparing and resetting, maximizing the speed of the TI ADC. The multiplexer array is responsible for switching the multiplexed comparator between SAR logic blocks. The SAR logic receives the comparison output from the multiplexed comparator in conversion phase, while blocks the output in sampling phase. After receiving comparison results, the output voltage of the CDAC is updated for the next bit-cycle. Simultaneously, the asynchronous comparator clock generator is triggered by the comparator regeneration indication signal. Once the 10-bit cycles have been accomplished, the asynchronous comparator clock generator generates a complete signal, indicating that the 10-bit digital output (Dout1 or Dout2) were ready. This complete signal will control an output MUX to select channel digital outputs alternately.

3.2. Split CDAC

The architecture of split CDAC in the proposed TI-SAR ADC is displayed in Figure 4. With the split CDAC structure applied, there is almost no VCM shift at the comparator input [23]. To enhance linearity during sampling, the bottom plate sampling technique is employed, which reduces the presence of parasitic MOS capacitors on the sampling node. Bootstrapped switches are utilized to improve sampling accuracy and facilitate the transfer of residue from CDAC to comparators. Figure 5 illustrates the schematic diagram of the proposed SAR logic designed for CDAC configuration. Customized latch and logic circuits are specifically designed to work in conjunction with split CDAC. Numerous control signals are generated to properly configure each capacitor during the conversion and sampling phase. The control relationship between the signal and the capacitor switch is shown at the bottom of Figure 5. A set of four signals, SWPP, SWPN, SWNP, SWNN, determines whether the bottom plate of positive side capacitors should be connected to VRP or VRN. During the sampling phase, the bottom plate is disconnected from the VRP and VRN and connected to the input signal VIN, controlled by the bootstrapped signal. The bottom plate of negative side capacitor is controlled by the inverted signals SWPPB, SWPNB, SWNPB and SWNNB. In the conversion phase, only one of the two split capacitors associated with each bit is activated, either switching to VRP or VRN, based on the final comparison results. The purpose of implementing split CDAC switch logic is to prevent continuous switching of the reference voltage and simplify the design of the reference voltage buffers. The pulse signal SC is generated after each comparison completed and this enables the results of the comparator to set the switching signal. The behavior of the MSB switching control signal during different phases is summarized in

Table 1. The status of the MSB switching control signal at different phases.

Bit	Phase		CK1/2	BT	SWPP	SWNN	SWPN	SWNP
MSB	Sampling		1	1	1	0	0	1
	Charge transfer		0	0	0	1	0	1
	conversion	Q = 1	0	0	1	1	1	1
		Q = 0	0	0	0	0	0	0

. The discussion above focuses on the SAR logic of the MSB capacitor, which is similar to the other capacitors, except for the LSB capacitor. The LSB capacitor utilizes half of the switching control signal and a simplified SAR logic circuit. Overall, this proposed SAR logic offers reduced hardware overhead and latency compared to traditional static CMOS logic. Moreover, the capacitance weight of each bit in CDAC is differed, therefore the CDAC switch and its driving buffer are carefully sized according to the weight of each bit.

3.3. Unit Capacitor

The unit capacitor is determined so that the thermal noise would not become bottle-neck to proposed structure, assuming the unit capacitance value is $C_u$ and the total single-ended sampling capacitance of CDAC is $C_s$. Since a differential structure is employed in proposed SAR ADC, the relationship between these capacitances can be expressed as

$$C_s=512C_u$$

(4)

The kT/C noise due to the differential structure should be doubled, therefore the noise power generated by the sampling capacitor in SAR ADC is

$$\overline{V_n^2}=\frac{2kT}{C_s}$$

(5)

The sampling noise power must satisfy the SNR requirement by being less than or equal to the quantization noise power

$$\overline{V_n^2}\le \frac{{\Delta }^2}{12}$$

(6)

$$\Delta =\frac{V_r}{2^N}$$

(7)

where $V_r$ represents reference voltage. The unit capacitance limited by the requirement of 10-bit resolution with a 0.9 V $V_r$ can be expressed as

$$C_u\ge 0.251 \mathrm{fF}$$

(8)

Considering the non-ideal factors, such as capacitor mismatch, the proposed unit capacitor value in this design is 2 fF.

3.4. Double-Tail Dynamic Comparator with Clock Decoupling

Figure 6 presents the schematic of the double-tail dynamic comparator with clock decoupling [24]. A pre-amplifier (with gain of 31.2 dB in our design) would be typically employed as the first stage of comparator. The second stage consists of a latch, which serves to restore the voltage difference obtained from the first stage. During the low phase of the CLK signal, the N and P nodes are charged to a high level, resetting the latch, while the output Q and QN are set to low level. Conversely, during the high phase of the CLK signal, the pre-amplifier stage activates, leading to the discharge of the two output nets of the pre-amplifier. Due to the variation in input voltage value, the discharging rates at N and P points also differ. This voltage discrepancy induces positive feedback in the latch, ultimately causing one output port to stabilize at a high level and the other at a low level. The comparison results, received and restored by MUX, are subsequently processed during the conversion phase of the channel.

Compared to the conventional structure, a decoupling MOS capacitor is included in the gate of input pair. When the comparator clock’s edge rises, the voltage at the input MOS source rapidly decreases, and the falling edge is coupled to the comparator input through a gate-source parasitic capacitor, leading to the additional common-mode and differential-mode signal interference on CDAC. This interference can impact the offset of the comparator and the accuracy of the comparison results. To mitigate this issue, a clock decoupling capacitor is added to the input of comparator. The rising edge of clock is coupled to the CDAC, neutralizing the coupling effect of the falling edge. The clock decoupling capacitor employs a MOS capacitor to match the gate-source parasitic capacitor of input pair. By introducing a properly sized clock decoupling capacitor, the comparator’s accuracy has been significantly enhanced.

3.5. BT Switch

Figure 7 shows the schematic of the BT switch, which connects the channel and the comparator. To ensure the linearity of the results, the BT switch commonly generates a boost signal to maintain a constant turn-on resistance for the switch transistors. The circuit utilizes a sampling clock denoted as CK, with M8 representing the switch transistor. During the low state of CK (known as the holding phase of the BT switch), the bottom plate of the bootstrap capacitor C is connected to ground through M3, while the top plate of C is charged to a high voltage through M4. Simultaneously, M8 turns off, thereby maintaining the output port in its current state. Conversely, during the high state of CK (known as the sampling phase of the BT switch), the bottom plate of C is connected to the source of M8 through M7, and the top plate of C is connected to the gate of M8 through M5. In this phase, the gate-source voltage of M8, which is equal to the voltage difference between the top and bottom plates of C, remains unchanged. In the case of the dual-channel TI-SAR ADC proposed in this paper, both the sampling phase of the BT switch and the conversion phase of the channel share the same clock, eliminating the need for additional signal generation.

4. Simulation Results

To validate the proposed technique, two 10-bit 400 MS/s TI-SAR ADCs were fabricated using 40 nm CMOS. One ADC incorporates the proposed comparator multiplexing approach, while the other follows conventional design principles. The same circuit modules, e.g., dual-channel structure, double-tail dynamic comparators, CDACs and the same 0.9 V supplies were applied in these TI-SAR ADCs. The only differences between the two ADCs are the number of comparators and the associated control circuits.

The results of the Monte Carlo simulation consisting of 200 runs are presented in Figure 8. The standard deviation (σ) of the comparator offset voltage is approximately 6.5 mV. However, this value falls short of meeting the requirements of a conventional 10-bit TI-SAR ADC, as stated in Equation (1). Nonetheless, the compact size of the comparators, along with the implementation of an asynchronous comparator clock generator, account for only 19% and 12% of total power consumption, respectively. Figure 9 illustrates the simulated ENOBs and SFDRs for both the proposed and the conventional TI-SAR ADCs, considering different levels of comparator offset mismatch. The results indicate that the proposed dual-channel TI-SAR ADC with comparator multiplexing exhibits immunity to offset mismatch, while the conventional one is sensitive to it. Furthermore, Figure 10 showcases the simulated spectra of the proposed and the conventional ADCs when subjected to 6σ comparator offset and Nyquist input. The proposed comparator multiplexing architecture significantly enhances the ADC ENOB from 5.0-bit to 9.7-bit and boosts the SFDR from 32.2 dB to 77.2 dB, with a mere 9.1% increase in power consumption.

The standard deviation (σ) of the capacitor used in BT switch is approximately 100 aF. Considering the mismatch among BT switches, a variation of 6σ (approximately 0.6fF) is introduced for the capacitor C, as well as 10% scale mismatch of the switch transistor M8. The simulated spectrum of proposed ADCs, considering the mismatch among BT switches, is presented in Figure 11. Notably, no noticeable performance degradation was observed due to the mismatch of BT switches.

Table 2. Performance comparison with the state-of-the-art SAR ADCs.

Specifications	This Work *,a		[5] b	[6] b	[18] b	[25] a	[26] a	[27] b
Technology	40 nm	40 nm	65 nm	40 nm	65 nm	180 nm	40 nm	65 nm
Architecture	Comp. mux. TI-SAR	TI-SAR	TI- Subranging Pipe-SAR	2 b/cycle SAR	Partial-Interleaving Pipe-SAR	Two Comp. SAR	TI- SAR	TI- Subranging SAR
Num. of channels	2	2	3	1	1/2	1	18	2
Calibration	no	no	yes	no	yes	yes	yes	yes
Resolution (bit)	10	10	11	10	10	10	10	10
Sampling Rate (MS/s)	400	400	450	300	500	50	2000	700
SNDR @Nyq. (dB)	60.2 (w/offset)	31.9 (w/offset)	56.2	47.0	52.9	61.3	52.3	53.3
SFDR @Nyq. (dB)	77.2	32.2	65.5	63.0	66.0	75.3	62.0	70.4
Power (mW)	2.40	2.20	7.40	2.10	8.20	6.60	10.5	9.50
FOM @Nyq. (fJ/conv.-step)	7.2	171.9	31.2	38.3	46.0	139.4	24.2	36.0

* Simulation results with 6σ offset mismatch. ^a Simulated result. ^b Measured results.

summarizes the proposed TI -SAR ADC and compares it to the state-of-the-art works. Our work achieves an outstanding FOM of 7.2 fJ/conv.-step.

5. Conclusions

This paper presents a novel dual-channel 10-bit 400 MS/s TI-SAR ADC featuring a switchable calibration-free comparator. The proposed dual-channel comparator multiplexing ADC structure eliminates comparator offset mismatch, leading to a significant improvement in ADC dynamic performance without incurring substantial hardware or power overhead. To improve accuracy, the design incorporates split CDAC and clock decoupling techniques. BT switches were utilized to connect channels and multiplexing comparators while maintaining a constant turn-on resistance in the switch transistors. Simulation results demonstrated a 6σ offset mismatch. The proposed 400 MS/s dual-channel TI-SAR ADC achieved 9.7-bit ENOB and 77.2 dB SFDR with an excellent FOM of 7.2 fJ/conv.-step.