Design of Efficient Concurrent Dual-Frequency Doherty Power Amplifier Based on Step Impedance Low-Pass Filter

Abstract

In view of the peak-to-average power ratio (PAPR) of wireless communication base stations, a Doherty power amplifier with high efficiency maintained at output power back-off (OBO) can effectively solve the problem of low efficiency of the traditional power amplifier at the point of power back-off. In this paper, we propose a method to implement a dual-frequency Doherty power amplifier (DPA) using a step-impedance low-pass filter to improve the bandwidth and efficiency of the DPA at output power back-off (OBO). Step impedance low-pass filters are used to solve the bandwidth limitations in traditional impedance converters and improve the efficiency of Doherty power amplifiers to a certain extent. In order to verify the proposed scheme, an efficient concurrent dual-band Doherty power amplifier operating at 2.0/3.5 GHz is designed and fabricated for the first range 1 (FR1) of 5G applications. In the measured results, the concurrent dual-band DPA achieves a saturated output power of 44 dBm and drain efficiency of 62% with a 6 dB back-off efficiency of 53% at 2.0 GHz and a saturated output power of 43.5 dBm and drain efficiency of 68% with a 6 dB back-off efficiency of 58% at 3.5 GHz.

1. Introduction

With the increase in the communication rate [1], the demand for communication capacity at the base station increases; therefore, high spectrum efficiency and high data rate orthogonal frequency division multiplexing (OFDM) signals [2] are one of the main modulation signals used today. Since OFDM signals are composed of multiple independently modulated subcarrier signals superimposed on each other, when the phases are the same, the superimposed signals tend to generate large instantaneous power peaks, resulting in a high peak-to-average power ratio (PAPR). This modulating signal tends to enter the nonlinear region of the power amplifier, and in order to avoid large distortion, the power amplifier is generally operated at the output power back-off point. Traditional power amplifiers have low power-added efficiency (PAE) at the output power back-off (OBO), resulting in large energy loss. The Doherty power amplifier (DPA) is based on the principle of active load modulation [3] to maintain high efficiency at OBO. A concurrent multi-band Doherty power amplifier [4,5] can achieve a reasonable allocation of spectrum resources and reduce interference to adjacent channel signals. Compared with the traditional multi-channel single-frequency power amplifier, the concurrent dual-band Doherty design structure can also effectively reduce system size and cost as well as have good back-off efficiency [6].

In 2012, Rawat et al. [7] used a T-type or π-type network structure to implement concurrent dual-frequency Doherty power amplifiers. The conventional quarter-wavelength impedance converter is replaced by a T-type or π-type structure and is equivalent in both frequency bands at the same time. Through the derivation of theory and formula, the solution is verified mathematically. However, the whole solution process is complicated and involves solving transcendental equations, and the result of the solution may not conform to the physical size, such as the negative solution. In this regard, Rawat et al. gave another solution by adding a T-shaped structure to match the impedance value to a transition impedance value, i.e., a one-step impedance matching process is divided into a two-step transformation to 50 Ω, which has similarities with the principle of step impedance matching. In 2012, Paul et al. [8] designed a dual-frequency Doherty power amplifier operating at 1.8 GHz and 2.4 GHz using the theory of harmonic suppression, and its efficiency in the power back-off region reached 60% and 44%, respectively. In 2016, Songbai He’s team at the University of Electronic Science and Technology of China [9] designed a dual-band Doherty power amplifier by using the transistor’s parasitic parameters directly as part of the impedance transformation and achieved 63% and 51% power back-off point efficiencies at 1.8 GHz and 2.6 GHz, respectively. In 2016, Serkan and Ahmet, University of Issyk-Kul, applied the real frequency technique to the design of dual-band matching networks [10]. The real frequency technique was used to synthesize a matching network with the dual-band response of a bandpass prototype while combining low-pass (LP) and high-pass (HP) sections in a cascade and optimizing under LP and HP frequency transformation. Finally, the dual-band matching network has 300 MHz and 500 MHz bandwidth at 1 GHz and 2 GHz, respectively. In 2016, Prof. S. Boumaiza’s group at the University of Waterloo [11], Canada, implemented a concurrent dual-band Doherty amplifier with a 300 MHz bandwidth by improving the π-shaped output combining network. In the same year, Alessandro Cidronali et al. [12] proposed a new method of compensated impedance inverters for absorbing the output capacitance and extending the DPA bandwidth by introducing a half-wavelength transmission line as an offset line in the peak amplifier branch. In 2020, it was mentioned in reference [13] that a phase–period matching network can be used as a multi-band impedance inverter, bias element, and phase compensator to realize a multi-band Doherty power amplifier. A six-band dual-mode Doherty power amplifier is finally realized by using reciprocal gate bias in the same way as the reference [14]. In one of these modes, the dual-frequency Doherty amplifier can obtain a bandwidth of 400 MHz. For high PAPR multi-band system applications, broadband DPAs and dual-band DPAs [15,16,17,18,19,20,21] are widely used.

Although the above studies provide good solutions for the design of concurrent dual-band Doherty amplifiers, the structure and calculation are complicated. In order to further simplify the design difficulty and extend the dual-band bandwidth, in this paper, we propose a method to realize a dual-band Doherty power amplifier using a step-impedance low-pass filter. A conventional Doherty power amplifier consists of a combination of a carrier power amplifier and a peak power amplifier. As shown in Figure 1, the input power is split in two by a Wilkinson power divider, and both the carrier and peak power amplifiers are connected with phase compensation lines used to achieve phase alignment of the signals from the carrier and peak power amplifiers as well as an open-circuit state for the peak power amplifier. The impedance matching at the junction point is achieved through an impedance converter. In this paper, we propose an efficient dual-band DPA to achieve dual-band matching by employing a fourth-order step impedance filter in the input and output matching network and post-matching network. Step impedance filters are simple and easy to implement and can be used as low-pass filters, as well as dual-band, matched networks. Due to the broadband matching characteristics of the step impedance low-pass filter, the operating bandwidth of the dual-frequency can be effectively extended, which can meet the multi-frequency and multi-standard requirements of the current communication system well. Finally, in this paper, a concurrent dual-band Doherty power amplifier operating at 2.0/3.5 GHz for FR1 of 5G applications is designed, with good results.

2. Design of Concurrent Dual-Band Doherty Power Amplifier

2.1. Design of Carrier Power Amplifier

The Doherty power amplifier consists of a carrier power amplifier and a peak power amplifier. The carrier power amplifier is designed first. The step impedance filter uses alternating microstrip lines of high or low characteristic impedance, which allows broadband impedance matching as well as dual-frequency point matching. The carrier power amplifier uses a fourth-order step impedance filter structure for both input matching and output matching. In particular, the output matching network achieves 50 Ω at output power saturation and 25 Ω impedance matching at 3 dB back-off.

The traditional design method is to first determine the fourth-order low-pass filter to be designed by using the design table and then calculate the required parameters of the bandpass filter based on the formula conversion. A microstrip filter design is usually a prototype circuit design method based on a comprehensive design. The prototype circuit is a low-frequency lumped circuit with inductors and capacitors as components, as shown in Figure 2. In the actual process, the prototype circuit parameters can be converted to the actual filter component values according to the filter design index requirements and according to certain transformation relations. The specifications of the designed filter are shown below.

The cut-off frequency is fc = 2 GHz; the passband maximum attenuation is Lar = 0.2 dB; the stopband side frequency is fs = 4 GHz; and the stopband minimum attenuation is Las = 34 dB.

The characteristic impedance of the input and output transmission lines is Zc = 50 Ω, the relative permittivity of the microstrip substrate material is ε = 3.66, and the substrate thickness is h = 0.762 mm.

There are several filter design models, such as the Butterwolf prototype filter, elliptic function filter, Chebyshev filter, and so on. In this paper, the Chebyshev filter is used; firstly, the order of the filter is determined (selected equal ripple waveforms and capacitive input ladder network) and calculated as follows:

(1) The normalized frequency is calculated as follows:

Q = f_s/f_c = 4/2

(1)

Take the filter order N = 5.

(2) When L_ar = 0.2 dB, the normalized value of the equal-ripple low-pass filter element is g₁ = g₅ = 1.3394; g₂ = g₄ = 1.3370; g₃ = 2.1660; and g₆ is equal to 1. The L and C low-pass filter circuits designed in this paper are shown in Figure 2.

Using a capacitive input ladder network, the real values of each component in the figure are calculated as follows:

$$C_1=C_5=g_1/2\pi f_c{Z}_c$$

(2)

$$C_3=g_3/2\pi f_c{Z}_c$$

(3)

$$L_2=L_4=g_2{Z}_c/2\pi f_c$$

(4)

In the process of calculating the structural size of the filter, there are generally the following requirements for the selected high- or low-impedance transmission line:

$$Z_{oh}\ge \frac{g_L{Z}_c}{\pi /4}$$

(5)

$$Z_{oL}\le \frac{\pi Z_c}{4g_c}$$

(6)

Z_oh is the calculated characteristic impedance of the high-impedance line when the high-impedance line is selected as the transmission line, and Z_oL is the calculated characteristic impedance of the low-impedance line. In the actual selection process, Z_oh = 100 is generally the best choice for the high-impedance line if the selected low microstrip line is too long or if the selected high microstrip line is too fine and difficult to process. Finally, the pahse constant of the high-impedance line is Z_oh = 101 Ω, that of the low-impedance line is Z_oL = 10 Ω. β is the phase constant in this paper.

For a high-impedance line, when ${\mathsf{\epsilon }}_{\mathrm{r}}$ = 3.66 and ${\mathrm{Z}}_{\mathrm{c}}=101 \mathsf{\Omega }$, one can obtain w/h = 0.1 and the following relationship:

$$\lambda /{\lambda }_{TEM}=1.28$$

(7)

$${\lambda }_{TEM}=\frac{{\lambda }_0}{\sqrt{{\epsilon }_r}}$$

(8)

$$\lambda ={\lambda }_g=\frac{{\lambda }_0}{\sqrt{{\epsilon }_{re}}}$$

(9)

After derivation, one obtains

$${\mathsf{\lambda }}_{\mathrm{g}}=1.28{\mathsf{\lambda }}_{\mathrm{T}\mathrm{E}\mathrm{M}}=1.28\frac{{\mathsf{\lambda }}_0}{\sqrt{{\mathsf{\epsilon }}_{\mathrm{r}}}}$$

(10)

$${\epsilon }_{re}={\left(\frac{{\lambda }_0}{{\lambda }_g}\right)}^2$$

(11)

Thus, the phase velocity of the high-impedance line and the high-impedance line length can be derived as

$$V_{ph}=\frac{c}{\sqrt{{\epsilon }_{re}}}$$

(12)

$$l_2=l_4=\frac{V_{ph}{L}_2}{Z_c}$$

(13)

Similarly, for low-impedance lines, when ${\mathsf{\epsilon }}_{\mathrm{r}}$ = 3.66 and ${\mathrm{Z}}_{\mathrm{c}}$ = 10 Ω, there is the following relationship: w/h = 10 and ${\mathsf{\lambda }/\mathsf{\lambda }}_{\mathrm{T}\mathrm{E}\mathrm{M}}=1.08$, so the calculation formula is as follows:

$${\mathsf{\epsilon }}_{\mathrm{re}}={\left(\frac{{\mathsf{\lambda }}_0}{\mathsf{\lambda }}\right)}^2={\left(\frac{{\mathsf{\lambda }}_0}{1.08{\mathsf{\lambda }}_{\mathrm{TEM}}}\right)}^2={\left(\frac{\sqrt{{\mathsf{\epsilon }}_{\mathrm{r}}}}{1.08}\right)}^2$$

(14)

And, ${\mathrm{V}}_{\mathrm{P}\mathrm{L}}=\frac{\mathrm{c}}{\sqrt{{\mathsf{\epsilon }}_{\mathrm{r}\mathrm{e}}}}$ low-impedance line length is as follows:

$$l_1=l_5=V_{PL}{C}_1{Z}_c$$

(15)

$$l_3=V_{PL}{C}_3{Z}_c$$

(16)

For the width of the microstrip line, the width and length of the actual microstrip line are calculated based on the impedance and the required electrical length using the microstrip line calculator tool, where the input and output microstrip line characteristic impedance is Zc = 50 Ω. Parameters are determined by low-pass filter prototyping and finally simulated by ADS. The amplitude–frequency response and S-parameters of the microstrip line filter are simulated using ADS to analyze whether the performance of the microstrip filter reaches the design specifications, and the microstrip line parameters are adjusted accordingly.

The step impedance low-pass microstrip filter is shown in Figure 3. Step-impedance converters can realize impedance conversion in the wide band range, and in this paper, a step impedance converter is chosen to implement the input and output matching networks, as well as the impedance conversion at the merging point. The step impedance converter has a similar structure to the impedance filter and can realize the transition from 25 Ω to 50 Ω at saturation output power and OBO The bandwidth limitation of the traditional quarter-wavelength impedance converter is solved.

The RF bias circuit is the direct current circuit of the power amplifier that isolates AC and conducts DC as a way to protect the DC power supply. In order to bring the gate and drain input impedances to infinity, a T-type dual-frequency bias circuit is used based on the equivalent quarter-wavelength methodology, as described in reference [22]. Additionally, the gate bias is connected in series with a 28 Ω resistor to limit the gate bias current, thus protecting the transistor from being burned due to excessive current flow. Large 10 uf, medium 100 nf, and small 16 pf capacitors are connected in parallel to the gate and drain power ports to filter out spurious signals at various frequencies.

The carrier power amplifier operates in two frequency bands, 2.0 GHz/3.5 GHz, and the overall circuit is shown in Figure 4. Both the input and output matching networks use a step impedance filter structure, and the gate and drain are both T-type dual-band bias circuits. In addition, in the 3.5 GHz band, the saturated output power reaches about 41 dBm, and the efficiency reaches about 70%; at this time, the matching impedance value is 50 Ω; back off 3 dB output power, the efficiency reaches about 60%, at this time the matching impedance value is 25 Ω, so that a quarter-wavelength impedance converter can be eliminated, and also can avoid bandwidth limitation, and the same is true in the 2 GHz band. The CGH40010F transistor is not stable in the full frequency band, and in order to prevent self-excited oscillations, there have been some research results, such as the Rollett approach and the Nyquist method in the stability network in reference [23], which achieves good results in preventing self-excited oscillations caused by parallel two-way power amplifiers in Doherty mode. In order to simplify the design approach, in this paper, the RC parallel network is added to the input matching network to improve the stability of the overall circuit and prevent the transistors from being damaged due to self-excited oscillations.

The simulation results of the carrier power amplifier are shown in Figure 5. When the input power is set to 29 dBm, the output power in the 3.4–3.6 GHz band reaches 40.1–40.4 dBm, and the power additive efficiency is 64–72%; when the output power in the 1.9–2.1 GHz band reaches 40.5–41.3 dBm, the power additive efficiency is 60–66%.

2.2. Design of Peak Power Amplifier

The Doherty Power Amplifier is based on the active load principle, and the concurrent dual-band DPA is designed as a symmetrical power amplifier with the same overall circuit structure for the carrier and peak power amplifiers. During power fallback, the peak power amplifier needs to be open at the merge point to prevent the signal from the carrier power amplifier from being transmitted to the peak power amplifier. The designed concurrent dual-band Doherty power amplifier adds a section of microstrip line with a characteristic impedance of 50 Ω behind the isolation capacitor at the output of the peak power amplifier and adjusts the phase of the voltage by adjusting the length of the microstrip line, so as to make the output port present an open-circuit state in two frequency bands during power fallback. As shown in Figure 6, the output port is shown to be open-circuit in both frequency bands at OBO.

Due to the difference in certain parameters (e.g., gate voltage, input power, etc.) between the carrier power amplifier and the peak power amplifier, the phase of the output signal will change. In order to increase the output power, it is necessary to add a piece of microstrip line with a characteristic impedance of 50 Ω to the output port of the carrier power amplifier, and by adjusting the length of the microstrip line, it makes the two signals have the same phase in the two frequency bands. As shown in Figure 7a,b are the resultant plots of the phase of the output signals of the carrier and peak power amplifiers in the 3.4–3.6 GHz and 1.9–2.1 GHz bands, respectively. As can be seen from the plots, the curves of the signal phases of the peak power amplifier and the carrier power amplifier basically coincide in the two frequency bands.

As shown in Figure 8, the saturated output power of the peak power amplifier at 3.4–3.6 GHz is 40–41 dBm, with a drain efficiency of 54–65%. At 1.9–2.1 GHz, the saturated output power is 40–40.2 dBm, and drain efficiency is 50–61%. The drain and gate voltages of the peak power amplifier are 28 V and −5.4 V, respectively, and the input power is 29 dBm. The drain and gate voltages of the peak power amplifier and carrier power amplifier and the saturated output power of the peak power amplifier basically reach the same level; the power additive efficiencies all reach more than 50%, and the subsequent overall circuits have to be adjusted and optimized.

3. Broadband Wilkinson Power Divider

Typically, the input port of a Doherty power amplifier requires a power splitter to split the input power in half. The bandwidth of an ordinary Wilkinson splitter cannot meet most of the engineering applications, so widening the bandwidth of the power splitter became the focus of current research. So far, the method of bandwidth expansion by multilevel impedance conversion has been widely used in the design of power dividers. Due to the multi-stage impedance converter having a lot of small amplitude and different phase reflected waves, the reflected waves can be suppressed when superimposed so that the bandwidth can be broadened. The power divider designed in this paper is to broaden the bandwidth by cascading three levels of λ/4 step impedance converters, which is shown schematically in Figure 9.

In this paper, a Chebyshev impedance converter is used to implement the bandwidth extension of the Wilkinson power divider. The Chebyshev polynomial can be expressed as

$${\mathrm{T}}_{\mathrm{n}}\left(\mathrm{x}\right)=2·{\mathrm{T}}_{\mathrm{n}-1}\left(\mathrm{x}\right)-{\mathrm{T}}_{\mathrm{n}-2}\left(\mathrm{x}\right)$$

(17)

Let $\mathrm{x}=\mathrm{c}\mathrm{o}\mathrm{s}\left(\mathsf{\theta }\right)$, where |x|< 1; then, the Chebyshev polynomial can be expressed as follows:

$${\mathrm{T}}_{\mathrm{n}}\left(\cos \mathsf{\theta }\right)=\cos \left(\mathrm{n}\mathsf{\theta }\right)$$

(18)

To make the response of Equation (18) have equal ripples, it is necessary to replace $\mathrm{c}\mathrm{o}\mathrm{s}\left(\mathsf{\theta }\right)$ with $\mathrm{c}\mathrm{o}\mathrm{s}\left(\mathsf{\theta }\right)/\mathrm{c}\mathrm{o}\mathrm{s}{\mathsf{\theta }}_{\mathrm{m}}$, where ${\mathsf{\theta }}_{\mathrm{m}}$ and $\mathsf{\pi }-{\mathsf{\theta }}_{\mathrm{m}}$ are the upper and lower frequencies of the passband, respectively. Then, the above equation can be written as

$${\mathrm{T}}_{\mathrm{n}}\left(\frac{\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }}{\mathrm{c}\mathrm{o}\mathrm{s}{\mathsf{\theta }}_{\mathrm{n}}}\right)={\mathrm{T}}_{\mathrm{n}}\left(\mathrm{s}\mathrm{e}\mathrm{c}{\mathsf{\theta }}_{\mathrm{n}}\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }\right)=\mathrm{c}\mathrm{o}\mathrm{s}\mathrm{n}\left[\mathrm{a}\mathrm{r}\mathrm{c}\mathrm{c}\mathrm{o}\mathrm{s}\left(\frac{\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }}{\mathrm{c}\mathrm{o}\mathrm{s}{\mathsf{\theta }}_{\mathrm{m}}}\right)\right]$$

(19)

The total reflection coefficient of the converter can be obtained by making $\mathrm{\Gamma }\left(\mathsf{\theta }\right)$ proportional to the passband of the Chebyshev equal ripple and combining it with Equation (19).

$$\mathrm{\Gamma }\left(\mathsf{\theta }\right)=2{\mathrm{e}}^{-\mathrm{j}\mathrm{n}\mathsf{\theta }}\left[{\mathrm{\Gamma }}_0\mathrm{c}\mathrm{o}\mathrm{s}\mathrm{N}\mathsf{\theta }+{\mathrm{\Gamma }}_1\mathrm{c}\mathrm{o}\mathrm{s}\left(\mathrm{N}-2\right)\mathsf{\theta }+\cdots +{\mathrm{\Gamma }}_{\mathrm{n}}\mathrm{c}\mathrm{o}\mathrm{s}\left(\mathrm{N}-2\mathrm{n}\right)+\cdots \right]=\mathrm{A}{\mathrm{e}}^{-\mathrm{j}\mathrm{N}\mathsf{\theta }}{\mathrm{T}}_{\mathrm{N}}\left(\mathrm{s}\mathrm{e}\mathrm{c}{\mathsf{\theta }}_{\mathrm{m}}\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }\right)$$

(20)

The last term of the formula obtained in Equation (20) is $\frac{1}{2}{\mathrm{\Gamma }}_{N/2}$ when N is even, and ${\mathrm{\Gamma }}_{\left(\mathrm{N}-1\right)/2}\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }$ when N is odd, where ${\mathrm{\Gamma }}_0,{\mathrm{\Gamma }}_1,{\mathrm{\Gamma }}_2,{\mathrm{\Gamma }}_3$ are the amplitude of the reflection coefficient at the impedance gradient point. A is an undetermined constant, so $\mathsf{\theta }=0$ can be obtained as follows:

$$\mathrm{A}=\frac{{\mathrm{R}}_{\mathrm{L}}-{\mathrm{Z}}_0}{{\mathrm{R}}_{\mathrm{L}}+{\mathrm{Z}}_0}·\frac{1}{{\mathrm{T}}_{\mathrm{N}}\left(\mathrm{s}\mathrm{e}\mathrm{c}{\mathsf{\theta }}_{\mathrm{m}}\right)}$$

(21)

If the amplitude of the maximum allowable reflection coefficient in the passband is ${\mathrm{\Gamma }}_{\mathrm{m}}$, then we can obtain ${\mathrm{\Gamma }}_{\mathrm{m}}=\left|\mathrm{A}\right|$ from Equation (20), because in the passband for ${\mathsf{\theta }}_m<\mathsf{\theta }<\mathsf{\pi }-{\mathsf{\theta }}_m$ there is $\left|sec{\mathsf{\theta }}_{m}cos\mathsf{\theta }\right|<1$, So there is $\left|sec{\mathsf{\theta }}_{m}cos\mathsf{\theta }\right|\le 1$ in the same range.

The following can be derived:

$${\mathrm{T}}_{\mathrm{N}}\left(\sec {\mathsf{\theta }}_{\mathrm{m}}\right)=\frac{1}{{\mathrm{\Gamma }}_{\mathrm{m}}}\left|\frac{{\mathrm{R}}_{\mathrm{L}}-{\mathrm{Z}}_0}{{\mathrm{R}}_{\mathrm{L}}+{\mathrm{Z}}_0}\right|\approx \frac{1}{2{\mathrm{\Gamma }}_{\mathrm{m}}}\left|\ln \frac{{\mathrm{R}}_{\mathrm{L}}}{{\mathrm{Z}}_0}\right|$$

(22)

$$\mathrm{s}\mathrm{e}\mathrm{c}{\mathsf{\theta }}_{\mathrm{m}}=\mathrm{c}\mathrm{o}\mathrm{s}\mathrm{h}\left[\frac{1}{\mathrm{N}}\mathrm{a}\mathrm{r}\mathrm{c}\mathrm{o}\mathrm{s}\mathrm{h}\left(\left|\frac{\mathrm{l}\mathrm{n}{\mathrm{R}}_{\mathrm{L}}/{\mathrm{Z}}_0}{2{\mathrm{\Gamma }}_{\mathrm{m}}}\right|\right)\right]$$

(23)

$${\mathrm{\Gamma }}_{\mathrm{n}}=\frac{1}{2}\mathrm{l}\mathrm{n}\frac{{\mathrm{Z}}_{\mathrm{n}+1}}{{\mathrm{Z}}_{\mathrm{n}}}$$

(24)

An ultra-wideband Wilkinson power splitter composed of a third-order Wilkinson power splitter is designed. Then, the impedance of each level is calculated, and N = 3 is substituted into Equation (20) to obtain the following:

$$\mathrm{\Gamma }\left(\mathsf{\theta }\right)=2{\mathrm{e}}^{-\mathrm{j}3\mathsf{\theta }}\left[{\mathrm{\Gamma }}_0\mathrm{c}\mathrm{o}\mathrm{s}3\mathsf{\theta }+{\mathrm{\Gamma }}_1\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }\right]=\mathrm{A}{\mathrm{e}}^{-\mathrm{j}3\mathsf{\theta }}{\mathrm{T}}_3\left(\mathrm{s}\mathrm{e}\mathrm{c}{\mathsf{\theta }}_{\mathrm{m}}\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }\right)$$

(25)

The following is obtained by $\mathrm{A}={\mathrm{\Gamma }}_{\mathrm{m}}=0.1$:

$$\mathrm{s}\mathrm{e}\mathrm{c}{\mathsf{\theta }}_{\mathrm{m}}=\mathrm{c}\mathrm{o}\mathrm{s}\mathrm{h}\left[\frac{1}{\mathrm{N}}\mathrm{a}\mathrm{r}\mathrm{c}\mathrm{o}\mathrm{s}\mathrm{h}\left(\left|\frac{\mathrm{l}\mathrm{n}{\mathrm{R}}_{\mathrm{L}}/{\mathrm{Z}}_0}{2{\mathrm{\Gamma }}_{\mathrm{m}}}\right|\right)\right]=\cos \mathrm{h}\left[\frac{1}{3}\mathrm{arcosh}\left(\frac{\ln \left(100/50\right)}{2\times 0.1}\right)\right]=1.21$$

(26)

Since $\mathrm{c}\mathrm{o}\mathrm{s}\mathrm{n}\mathsf{\theta }$ can be expanded as the sum of polynomials of the form $\mathrm{c}\mathrm{o}\mathrm{s}\left(\mathrm{n}-2\mathrm{m}\right)\mathsf{\theta }$, it follows from Equation (19) when n = 3:

$${\mathrm{T}}_3\left(\mathrm{s}\mathrm{e}\mathrm{c}{\mathsf{\theta }}_{\mathrm{m}}\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }\right)=\mathrm{s}\mathrm{e}{\mathrm{c}}^3{\mathsf{\theta }}_{\mathrm{m}}\left(\mathrm{c}\mathrm{o}\mathrm{s}3\mathsf{\theta }+3\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }\right)-3\mathrm{s}\mathrm{e}\mathrm{c}{\mathsf{\theta }}_{\mathrm{m}}\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }$$

(27)

The following is further available:

$$2\left[{\mathrm{\Gamma }}_0\mathrm{c}\mathrm{o}\mathrm{s}3\mathsf{\theta }+{\mathrm{\Gamma }}_1\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }\right]=\mathrm{A}\mathrm{s}\mathrm{e}{\mathrm{c}}^3{\mathsf{\theta }}_{\mathrm{m}}\left(\mathrm{c}\mathrm{o}\mathrm{s}3\mathsf{\theta }+3\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }\right)-3\mathrm{A}\mathrm{s}\mathrm{e}\mathrm{c}{\mathsf{\theta }}_{\mathrm{m}}\mathrm{c}\mathrm{o}\mathrm{s}\mathsf{\theta }$$

(28)

It can be solved through Equation (28) that ${\mathrm{\Gamma }}_0=0.0886,{\mathrm{\Gamma }}_1=0.0842$. According to the symmetry, ${\mathrm{\Gamma }}_2={\mathrm{\Gamma }}_1,{\mathrm{\Gamma }}_3={\mathrm{\Gamma }}_0$, and substituting the value of ${\mathrm{\Gamma }}_0,{\mathrm{\Gamma }}_1,{\mathrm{\Gamma }}_2,{\mathrm{\Gamma }}_3$ into Equation (24) can calculate Z1 = 81.7 Ω, Z2 = 69.1 Ω, and Z3 = 58.4 Ω. The calculation of the isolation resistance is overly complicated and can be obtained by consulting the table: R1 = 119.2 Ω, R2 = 226.7 Ω, and R3 = 314.3 Ω.

The calculation of all key parameters of the Wilkinson power divider is completed, as shown in Figure 10.

The simulation results of the designed broadband Wilkinson power amplifier are shown in Figure 11, and S11 is less than −20 dB in both 1–4 GHz bands, which satisfies the radiation coefficient requirement at the input port. S22 is less than −25 dB in the 1–4 GHz band and also satisfies the reflection coefficient requirement of the output port, and S33 and S22 have the same index because of the symmetrical structure. S23 is less than −23 dB in the 1–4 GHz band, which basically meets the isolation requirement between port 2 and port 3. S21 is −3.1 dB in the 1–4 GHz band, which shows that the output power of port 2 is 1/2 of the input power of port 1. In the same way, since the Wilkinson power divider is a symmetrical structure, the output power of port 3 is 1/2 of the input power of port 1. All the specifications of the designed broadband Wilkinson power divider satisfy the design requirements.

4. Results and Discussion

The basic sub-circuit of the designed concurrent dual-band Doherty power amplifier is realized, and all the circuit units are combined into the final circuit. The topology of the overall circuit consists of a broadband Wilkinson power divider, a carrier power amplifier, a peak power amplifier, and an impedance converter, as shown in Figure 12. To further validate the proposed design, physical fabrication and testing were carried out. The fabricated DPA is shown in Figure 13. Here, a 10 W Cree GaN transistor (CGH40010F) is used as the active device, and the substrate material used is Rogers4350B with a thickness of 0.762 mm, dielectric constant of 3.66, and tangent loss of 0.0037. The gate bias voltages for the carrier amplifier and the peak amplifier are −2.9 V and −5.4 V, respectively, and the drain bias voltages of both are 28 V.

The testing system consists of a vector network analyzer, a spectrum analysis instrument, a signal source, a driving stage power amplifier, an attenuator, a DC power supply, and a power amplifier to be tested. The photo of the measuring device is shown in Figure 14.

The overall circuit of the designed concurrent dual-band Doherty power amplifier is simulated and tested for drain efficiency and output power, as shown in Figure 15 and Figure 16. As shown in Figure 15, the simulation results show that the saturated drain efficiency of the concurrent dual-band Doherty power amplifier is 60–63%, the saturated output power reaches 43–44 dBm in the 1.9–2.1 GHz band, and the drain efficiency is 53–60% at the 6 dB back-off point. In the 3.4–3.6 GHz band, the concurrent dual-band power amplifier has a drain efficiency of 65–72% and saturated output power of 44–44.2 dBm, with drain efficiencies of 54–62% at the 6 dB back-off point.

The test results of the designed dual-band DPA in the 1.5–4.5 GHz band are shown in Figure 16. After testing, a bandwidth of about 200 MHz is available in both bands. The saturated output power reaches 43.4–43.7 dBm in the 2 GHz band, and drain efficiency reaches 57–65%; the 6 dB back-off efficiency is 49.7–57.4%. In the 3.5 GHz band, the saturated output power reaches 43.7–44.4 dBm, and drain efficiency reaches 65–71%; the 6 dB back-off efficiency is 53–65%. Near the 2.6 GHz band, the drain efficiency is almost zero, and the output power is below 40 dBm. In this design, the parallel dual-band Doherty power amplifier has an isolation band with trapping characteristics in the middle of the two bands and a transmission zero at about 2.6 GHz. The power amplifier is usually followed by a filter, which can be filtered using a dual-band bandpass filter to achieve better performance specifications.

The nonlinearity metrics of the power amplifier are also important, and here, the adjacent channel leakage ratio (ACPR) is used to measure the linearity of the designed concurrent dual-band Doherty power amplifier. Based on the WCMDA standard protocol of 3GPP, a 64 K modulated signal with a bandwidth of 5 MHz is used for testing. The results are shown in Figure 17, where the adjacent channel leakage ratios are tested for two frequency bands with frequency centers of 2.0 GHz and 3.5 GHz, respectively. As can be seen from the figure, after digital pre-distortion (DPD), the power values of the first and second adjacent channels are very small relative to the power of the main channel. This indicates that the transmitted signal has little interference with other signals and meets the requirements of international standards. Compared with other concurrent dual-band Doherty power amplifiers at home and abroad, as shown in

Table 1. Performance comparison between this paper and other similar literature studies.

Ref.	Frequency/GHz	DE@Sat/DE@OBO/%	Output Power@Sat/@OBO/dBm
[3]	1.42/2.4	69.8/61 and 65.8/52.8	43.5/37.5 and 43.6/37.6
[7]	1.8/2.4	64/60 and 54/44	43/37 and 43/37
[8]	0.85/2.33	47.5/45 and 41/35	44/38 and 42.5/36.5
[10]	1.96/3.5	59.5/50.8 and 49.6/42.9	39.2/33.1 and 29.1/24.8
[11]	1.42/2.24	69/61 and 65.8/52.8	43.5/37.5 and 43.6/37.6
[20]	2.6/3.5	55.8/49.6 and 55.2/49.3	43.3/38.5 and 43.6/38.5
[21]	2.14/2.6	64.4/50 and 69/57	43.25/37.25 and 43.3/37.3
This work	2.0/3.5	66/55 and 71/62	44.2/38.2 and 43.8/37.8

, the concurrent dual-band Doherty power amplifier designed in this paper has certain advantages. The output power and efficiency have high specifications.

5. Conclusions

In this paper, a concurrent dual-band Doherty power amplifier operating at 2.0/3.5 is designed, and the designed power amplifier is simulated and physically tested. The test results show that the designed concurrent dual-band Doherty power amplifier achieves a saturated output power and drain efficiency of 44 dBm and 62%, respectively, and a 6 dB back-off efficiency of 53% in the 2 GHz band. The saturated output power and drain efficiency in the 3.5 GHz band reached 43.8 dBm and 68%, respectively, and the 6 dB back-off efficiency reached 58%. Finally, the power amplifier was also tested for the nonlinearity metric ACPR, which showed that the power in the adjacent channel was small relative to the power in the main channel. This design can provide an excellent solution for concurrent dual-band Doherty power amplifiers. In addition to this, the low-pass filter has a large bandwidth, and the use of real frequency techniques to enable precise matching of the saturation and fallback impedances of the dual-band may result in a larger bandwidth and better fallback efficiency.